2 * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
3 * Author:Mark Yao <mark.yao@rock-chips.com>
5 * This software is licensed under the terms of the GNU General Public
6 * License version 2, as published by the Free Software Foundation, and
7 * may be copied, distributed, and modified under those terms.
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
17 #include <linux/kernel.h>
18 #include <linux/component.h>
20 #include "rockchip_drm_vop.h"
21 #include "rockchip_vop_reg.h"
23 #define VOP_REG_VER_MASK(off, _mask, s, _write_mask, _major, \
24 _begin_minor, _end_minor) \
28 .write_mask = _write_mask, \
30 .begin_minor = _begin_minor, \
31 .end_minor = _end_minor,}
33 #define VOP_REG(off, _mask, s) \
34 VOP_REG_VER_MASK(off, _mask, s, false, 0, 0, -1)
36 #define VOP_REG_MASK(off, _mask, s) \
37 VOP_REG_VER_MASK(off, _mask, s, true, 0, 0, -1)
39 #define VOP_REG_VER(off, _mask, s, _major, _begin_minor, _end_minor) \
40 VOP_REG_VER_MASK(off, _mask, s, false, \
41 _major, _begin_minor, _end_minor)
44 static const uint32_t formats_win_full[] = {
61 static const uint32_t formats_win_lite[] = {
72 static const struct vop_scl_extension rk3288_win_full_scl_ext = {
73 .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
74 .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
75 .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
76 .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
77 .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
78 .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
79 .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
80 .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
81 .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
82 .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
83 .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
84 .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
85 .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
86 .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
87 .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
88 .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
89 .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
90 .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
91 .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
92 .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
93 .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
96 static const struct vop_scl_regs rk3288_win_full_scl = {
97 .ext = &rk3288_win_full_scl_ext,
98 .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
99 .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
100 .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
101 .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
104 static const struct vop_win_phy rk3288_win01_data = {
105 .scl = &rk3288_win_full_scl,
106 .data_formats = formats_win_full,
107 .nformats = ARRAY_SIZE(formats_win_full),
108 .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
109 .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
110 .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 4),
111 .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
112 .xmirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 21, 3, 2, -1),
113 .ymirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 22, 3, 2, -1),
114 .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
115 .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
116 .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
117 .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
118 .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
119 .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
120 .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
121 .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffffffff, 0),
122 .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xffffffff, 0),
125 static const struct vop_win_phy rk3288_win23_data = {
126 .data_formats = formats_win_lite,
127 .nformats = ARRAY_SIZE(formats_win_lite),
128 .gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
129 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4),
130 .format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
131 .rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
132 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
133 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
134 .yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
135 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
136 .src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
137 .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
140 static const struct vop_win_phy rk3288_area1_data = {
141 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 5),
142 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO1, 0x0fff0fff, 0),
143 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST1, 0x1fff1fff, 0),
144 .yrgb_mst = VOP_REG(RK3288_WIN2_MST1, 0xffffffff, 0),
145 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 16),
148 static const struct vop_win_phy rk3288_area2_data = {
149 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 6),
150 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO2, 0x0fff0fff, 0),
151 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST2, 0x1fff1fff, 0),
152 .yrgb_mst = VOP_REG(RK3288_WIN2_MST2, 0xffffffff, 0),
153 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 0),
156 static const struct vop_win_phy rk3288_area3_data = {
157 .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 7),
158 .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO3, 0x0fff0fff, 0),
159 .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST3, 0x1fff1fff, 0),
160 .yrgb_mst = VOP_REG(RK3288_WIN2_MST3, 0xffffffff, 0),
161 .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 16),
164 static const struct vop_win_phy *rk3288_area_data[] = {
170 static const struct vop_ctrl rk3288_ctrl_data = {
171 .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
172 .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
173 .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
174 .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
175 .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
176 .vact_st_end_f1 = VOP_REG(RK3288_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
177 .vs_st_end_f1 = VOP_REG(RK3288_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
178 .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
179 .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
180 .vpost_st_end_f1 = VOP_REG(RK3288_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
181 .dsp_interlace = VOP_REG(RK3288_DSP_CTRL0, 0x1, 10),
182 .auto_gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
183 .dsp_layer_sel = VOP_REG(RK3288_DSP_CTRL1, 0xff, 8),
184 .post_lb_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 18, 3, 2, -1),
185 .global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1),
186 .overlay_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 16, 3, 2, -1),
187 .core_dclk_div = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 4, 3, 4, -1),
188 .p2i_en = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 5, 3, 4, -1),
189 .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
190 .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
191 .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
192 .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
193 .pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0xf, 4, 3, 0, 1),
194 .rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 16, 3, 2, -1),
195 .hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 20, 3, 2, -1),
196 .edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 24, 3, 2, -1),
197 .mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 28, 3, 2, -1),
199 .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
200 .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
202 .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12),
203 .dsp_ccir656_avg = VOP_REG(RK3288_DSP_CTRL0, 0x1, 20),
204 .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
205 .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0),
206 .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
208 .afbdc_rstn = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 3),
209 .afbdc_en = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 0),
210 .afbdc_sel = VOP_REG(RK3399_AFBCD0_CTRL, 0x3, 1),
211 .afbdc_format = VOP_REG(RK3399_AFBCD0_CTRL, 0x1f, 16),
212 .afbdc_hreg_block_split = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 21),
213 .afbdc_hdr_ptr = VOP_REG(RK3399_AFBCD0_HDR_PTR, 0xffffffff, 0),
214 .afbdc_pic_size = VOP_REG(RK3399_AFBCD0_PIC_SIZE, 0xffffffff, 0),
216 .xmirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 22),
217 .ymirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 23),
219 .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0),
221 .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
225 * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
226 * special support to get alpha blending working. For now, just use overlay
227 * window 3 for the drm cursor.
230 static const struct vop_win_data rk3288_vop_win_data[] = {
231 { .base = 0x00, .phy = &rk3288_win01_data,
232 .type = DRM_PLANE_TYPE_PRIMARY },
233 { .base = 0x40, .phy = &rk3288_win01_data,
234 .type = DRM_PLANE_TYPE_OVERLAY },
235 { .base = 0x00, .phy = &rk3288_win23_data,
236 .type = DRM_PLANE_TYPE_OVERLAY,
237 .area = rk3288_area_data,
238 .area_size = ARRAY_SIZE(rk3288_area_data), },
239 { .base = 0x50, .phy = &rk3288_win23_data,
240 .type = DRM_PLANE_TYPE_CURSOR,
241 .area = rk3288_area_data,
242 .area_size = ARRAY_SIZE(rk3288_area_data), },
245 static const int rk3288_vop_intrs[] = {
252 static const struct vop_intr rk3288_vop_intr = {
253 .intrs = rk3288_vop_intrs,
254 .nintrs = ARRAY_SIZE(rk3288_vop_intrs),
255 .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
256 .status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
257 .enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
258 .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
261 static const struct vop_data rk3288_vop = {
262 .version = VOP_VERSION(3, 1),
263 .feature = VOP_FEATURE_OUTPUT_10BIT,
264 .intr = &rk3288_vop_intr,
265 .ctrl = &rk3288_ctrl_data,
266 .win = rk3288_vop_win_data,
267 .win_size = ARRAY_SIZE(rk3288_vop_win_data),
270 static const int rk3368_vop_intrs[] = {
287 static const struct vop_intr rk3368_vop_intr = {
288 .intrs = rk3368_vop_intrs,
289 .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
290 .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0),
291 .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16),
292 .status = VOP_REG_MASK(RK3368_INTR_STATUS, 0x3fff, 0),
293 .enable = VOP_REG_MASK(RK3368_INTR_EN, 0x3fff, 0),
294 .clear = VOP_REG_MASK(RK3368_INTR_CLEAR, 0x3fff, 0),
297 static const struct vop_win_phy rk3368_win23_data = {
298 .data_formats = formats_win_lite,
299 .nformats = ARRAY_SIZE(formats_win_lite),
300 .gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0),
301 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4),
302 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5),
303 .ymirror = VOP_REG(RK3368_WIN2_CTRL1, 0x1, 15),
304 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20),
305 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0),
306 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0),
307 .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0),
308 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0),
309 .src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
310 .dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xff, 0),
313 static const struct vop_win_phy rk3368_area1_data = {
314 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 8),
315 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 9),
316 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 23),
317 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO1, 0x0fff0fff, 0),
318 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST1, 0x1fff1fff, 0),
319 .yrgb_mst = VOP_REG(RK3368_WIN2_MST1, 0xffffffff, 0),
320 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 16),
323 static const struct vop_win_phy rk3368_area2_data = {
324 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 12),
325 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 13),
326 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 26),
327 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO2, 0x0fff0fff, 0),
328 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST2, 0x1fff1fff, 0),
329 .yrgb_mst = VOP_REG(RK3368_WIN2_MST2, 0xffffffff, 0),
330 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR2_3, 0x1fff, 0),
333 static const struct vop_win_phy rk3368_area3_data = {
334 .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 16),
335 .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 17),
336 .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 29),
337 .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO3, 0x0fff0fff, 0),
338 .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST3, 0x1fff1fff, 0),
339 .yrgb_mst = VOP_REG(RK3368_WIN2_MST3, 0xffffffff, 0),
340 .yrgb_vir = VOP_REG(RK3368_WIN2_VIR2_3, 0x1fff, 16),
343 static const struct vop_win_phy *rk3368_area_data[] = {
349 static const struct vop_win_data rk3368_vop_win_data[] = {
350 { .base = 0x00, .phy = &rk3288_win01_data,
351 .type = DRM_PLANE_TYPE_PRIMARY },
352 { .base = 0x40, .phy = &rk3288_win01_data,
353 .type = DRM_PLANE_TYPE_OVERLAY },
354 { .base = 0x00, .phy = &rk3368_win23_data,
355 .type = DRM_PLANE_TYPE_OVERLAY,
356 .area = rk3368_area_data,
357 .area_size = ARRAY_SIZE(rk3368_area_data), },
358 { .base = 0x50, .phy = &rk3368_win23_data,
359 .type = DRM_PLANE_TYPE_CURSOR,
360 .area = rk3368_area_data,
361 .area_size = ARRAY_SIZE(rk3368_area_data), },
364 static const struct vop_data rk3368_vop = {
365 .version = VOP_VERSION(3, 2),
366 .feature = VOP_FEATURE_OUTPUT_10BIT,
367 .intr = &rk3368_vop_intr,
368 .ctrl = &rk3288_ctrl_data,
369 .win = rk3368_vop_win_data,
370 .win_size = ARRAY_SIZE(rk3368_vop_win_data),
373 static const struct vop_intr rk3366_vop_intr = {
374 .intrs = rk3368_vop_intrs,
375 .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
376 .line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0),
377 .line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16),
378 .status = VOP_REG_MASK(RK3366_INTR_STATUS0, 0xffff, 0),
379 .enable = VOP_REG_MASK(RK3366_INTR_EN0, 0xffff, 0),
380 .clear = VOP_REG_MASK(RK3366_INTR_CLEAR0, 0xffff, 0),
383 static const struct vop_data rk3366_vop = {
384 .version = VOP_VERSION(3, 4),
385 .feature = VOP_FEATURE_OUTPUT_10BIT,
386 .intr = &rk3366_vop_intr,
387 .ctrl = &rk3288_ctrl_data,
388 .win = rk3368_vop_win_data,
389 .win_size = ARRAY_SIZE(rk3368_vop_win_data),
392 static const uint32_t vop_csc_y2r_bt601[] = {
393 0x00000400, 0x0400059c, 0xfd25fea0, 0x07170400,
394 0x00000000, 0xfffecab4, 0x00087932, 0xfff1d4f2,
397 static const uint32_t vop_csc_y2r_bt601_12_235[] = {
398 0x000004a8, 0x04a80662, 0xfcbffe6f, 0x081204a8,
399 0x00000000, 0xfff2134e, 0x00087b58, 0xffeeb4b0,
402 static const uint32_t vop_csc_r2y_bt601[] = {
403 0x02590132, 0xff530075, 0x0200fead, 0xfe530200,
404 0x0000ffad, 0x00000200, 0x00080200, 0x00080200,
407 static const uint32_t vop_csc_r2y_bt601_12_235[] = {
408 0x02040107, 0xff680064, 0x01c2fed6, 0xffb7fe87,
409 0x0000ffb7, 0x00010200, 0x00080200, 0x00080200,
412 static const uint32_t vop_csc_y2r_bt709[] = {
413 0x000004a8, 0x04a8072c, 0xfddeff26, 0x087304a8,
414 0x00000000, 0xfff08077, 0x0004cfed, 0xffedf1b8,
417 static const uint32_t vop_csc_r2y_bt709[] = {
418 0x027500bb, 0xff99003f, 0x01c2fea5, 0xfe6801c2,
419 0xffd7fe68, 0x00010200, 0x00080200, 0x00080200,
422 static const uint32_t vop_csc_y2r_bt2020[] = {
423 0x000004a8, 0x04a806b6, 0xfd66ff40, 0x089004a8,
424 0x00000000, 0xfff16bfc, 0x00058ae9, 0xffedb828,
427 static const uint32_t vop_csc_r2y_bt2020[] = {
428 0x025300e6, 0xff830034, 0x01c1febd, 0xfe6401c1,
429 0x0000ffdc, 0x00010200, 0x00080200, 0x00080200,
432 static const uint32_t vop_csc_r2r_bt709_to_bt2020[] = {
433 0xfda606a4, 0xff80ffb5, 0xfff80488, 0xff99ffed,
434 0x0000047a, 0x00000200, 0x00000200, 0x00000200,
437 static const uint32_t vop_csc_r2r_bt2020_to_bt709[] = {
438 0x01510282, 0x0047002c, 0x000c03ae, 0x005a0011,
439 0x00000394, 0x00000200, 0x00000200, 0x00000200,
442 static const struct vop_csc_table rk3399_csc_table = {
443 .y2r_bt601 = vop_csc_y2r_bt601,
444 .y2r_bt601_12_235 = vop_csc_y2r_bt601_12_235,
445 .r2y_bt601 = vop_csc_r2y_bt601,
446 .r2y_bt601_12_235 = vop_csc_r2y_bt601_12_235,
448 .y2r_bt709 = vop_csc_y2r_bt709,
449 .r2y_bt709 = vop_csc_r2y_bt709,
451 .y2r_bt2020 = vop_csc_y2r_bt2020,
452 .r2y_bt2020 = vop_csc_r2y_bt2020,
454 .r2r_bt709_to_bt2020 = vop_csc_r2r_bt709_to_bt2020,
455 .r2r_bt2020_to_bt709 = vop_csc_r2r_bt2020_to_bt709,
458 static const struct vop_csc rk3399_win0_csc = {
459 .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 0),
460 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1),
461 .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 2),
462 .y2r_offset = RK3399_WIN0_YUV2YUV_Y2R,
463 .r2r_offset = RK3399_WIN0_YUV2YUV_3X3,
464 .r2y_offset = RK3399_WIN0_YUV2YUV_R2Y,
467 static const struct vop_csc rk3399_win1_csc = {
468 .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 8),
469 .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 9),
470 .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 10),
471 .y2r_offset = RK3399_WIN1_YUV2YUV_Y2R,
472 .r2r_offset = RK3399_WIN1_YUV2YUV_3X3,
473 .r2y_offset = RK3399_WIN1_YUV2YUV_R2Y,
476 static const struct vop_win_data rk3399_vop_win_data[] = {
477 { .base = 0x00, .phy = &rk3288_win01_data, .csc = &rk3399_win0_csc,
478 .type = DRM_PLANE_TYPE_PRIMARY },
479 { .base = 0x40, .phy = &rk3288_win01_data, .csc = &rk3399_win1_csc,
480 .type = DRM_PLANE_TYPE_OVERLAY },
481 { .base = 0x00, .phy = &rk3368_win23_data,
482 .type = DRM_PLANE_TYPE_OVERLAY,
483 .area = rk3368_area_data,
484 .area_size = ARRAY_SIZE(rk3368_area_data), },
485 { .base = 0x50, .phy = &rk3368_win23_data,
486 .type = DRM_PLANE_TYPE_CURSOR,
487 .area = rk3368_area_data,
488 .area_size = ARRAY_SIZE(rk3368_area_data), },
491 static const struct vop_data rk3399_vop_big = {
492 .version = VOP_VERSION(3, 5),
493 .csc_table = &rk3399_csc_table,
494 .feature = VOP_FEATURE_OUTPUT_10BIT | VOP_FEATURE_AFBDC,
495 .intr = &rk3366_vop_intr,
496 .ctrl = &rk3288_ctrl_data,
497 .win = rk3399_vop_win_data,
498 .win_size = ARRAY_SIZE(rk3399_vop_win_data),
501 static const struct vop_win_data rk3399_vop_lit_win_data[] = {
502 { .base = 0x00, .phy = &rk3288_win01_data, .csc = &rk3399_win0_csc,
503 .type = DRM_PLANE_TYPE_PRIMARY },
505 { .base = 0x00, .phy = &rk3368_win23_data,
506 .type = DRM_PLANE_TYPE_CURSOR,
507 .area = rk3368_area_data,
508 .area_size = ARRAY_SIZE(rk3368_area_data), },
513 static const struct vop_data rk3399_vop_lit = {
514 .version = VOP_VERSION(3, 6),
515 .csc_table = &rk3399_csc_table,
516 .intr = &rk3366_vop_intr,
517 .ctrl = &rk3288_ctrl_data,
518 .win = rk3399_vop_lit_win_data,
519 .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data),
522 static const struct vop_data rk322x_vop = {
523 .version = VOP_VERSION(3, 7),
524 .feature = VOP_FEATURE_OUTPUT_10BIT,
525 .intr = &rk3366_vop_intr,
526 .ctrl = &rk3288_ctrl_data,
527 .win = rk3368_vop_win_data,
528 .win_size = ARRAY_SIZE(rk3368_vop_win_data),
531 static const struct vop_scl_regs rk3066_win_scl = {
532 .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
533 .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
534 .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
535 .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
538 static const struct vop_win_phy rk3036_win0_data = {
539 .scl = &rk3066_win_scl,
540 .data_formats = formats_win_full,
541 .nformats = ARRAY_SIZE(formats_win_full),
542 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
543 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
544 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
545 .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
546 .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
547 .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
548 .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
549 .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
550 .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
551 .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16),
552 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18),
553 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0)
556 static const struct vop_win_phy rk3036_win1_data = {
557 .data_formats = formats_win_lite,
558 .nformats = ARRAY_SIZE(formats_win_lite),
559 .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
560 .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
561 .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
562 .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
563 .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
564 .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
565 .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
566 .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
567 .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19),
568 .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1)
571 static const struct vop_win_data rk3036_vop_win_data[] = {
572 { .base = 0x00, .phy = &rk3036_win0_data,
573 .type = DRM_PLANE_TYPE_PRIMARY },
574 { .base = 0x00, .phy = &rk3036_win1_data,
575 .type = DRM_PLANE_TYPE_CURSOR },
578 static const int rk3036_vop_intrs[] = {
585 static const struct vop_intr rk3036_intr = {
586 .intrs = rk3036_vop_intrs,
587 .nintrs = ARRAY_SIZE(rk3036_vop_intrs),
588 .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
589 .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
590 .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
591 .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
594 static const struct vop_ctrl rk3036_ctrl_data = {
595 .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
596 .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
597 .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24),
598 .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
599 .dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8),
600 .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
601 .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
602 .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
603 .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
604 .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
607 static const struct vop_data rk3036_vop = {
608 .version = VOP_VERSION(2, 2),
609 .ctrl = &rk3036_ctrl_data,
610 .intr = &rk3036_intr,
611 .win = rk3036_vop_win_data,
612 .win_size = ARRAY_SIZE(rk3036_vop_win_data),
615 static const struct of_device_id vop_driver_dt_match[] = {
616 { .compatible = "rockchip,rk3036-vop",
617 .data = &rk3036_vop },
618 { .compatible = "rockchip,rk3288-vop",
619 .data = &rk3288_vop },
620 { .compatible = "rockchip,rk3368-vop",
621 .data = &rk3368_vop },
622 { .compatible = "rockchip,rk3366-vop",
623 .data = &rk3366_vop },
624 { .compatible = "rockchip,rk3399-vop-big",
625 .data = &rk3399_vop_big },
626 { .compatible = "rockchip,rk3399-vop-lit",
627 .data = &rk3399_vop_lit },
628 { .compatible = "rockchip,rk322x-vop",
629 .data = &rk322x_vop },
632 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
634 static int vop_probe(struct platform_device *pdev)
636 struct device *dev = &pdev->dev;
639 dev_err(dev, "can't find vop devices\n");
643 return component_add(dev, &vop_component_ops);
646 static int vop_remove(struct platform_device *pdev)
648 component_del(&pdev->dev, &vop_component_ops);
653 struct platform_driver vop_platform_driver = {
655 .remove = vop_remove,
657 .name = "rockchip-vop",
658 .owner = THIS_MODULE,
659 .of_match_table = of_match_ptr(vop_driver_dt_match),
663 module_platform_driver(vop_platform_driver);
665 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
666 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
667 MODULE_LICENSE("GPL v2");