drivers/gpu/drm/rockchip/rockchip_vop_reg.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drmP.h>
  16
  17 #include <linux/kernel.h>
  18 #include <linux/component.h>
  19
  20 #include "rockchip_drm_vop.h"
  21 #include "rockchip_vop_reg.h"
  22
  23 #define VOP_REG_VER_MASK(off, _mask, s, _write_mask, _major, \
  24                          _begin_minor, _end_minor) \
  25                 {.offset = off, \
  26                  .mask = _mask, \
  27                  .shift = s, \
  28                  .write_mask = _write_mask, \
  29                  .major = _major, \
  30                  .begin_minor = _begin_minor, \
  31                  .end_minor = _end_minor,}
  32
  33 #define VOP_REG(off, _mask, s) \
  34                 VOP_REG_VER_MASK(off, _mask, s, false, 0, 0, -1)
  35
  36 #define VOP_REG_MASK(off, _mask, s) \
  37                 VOP_REG_VER_MASK(off, _mask, s, true, 0, 0, -1)
  38
  39 #define VOP_REG_VER(off, _mask, s, _major, _begin_minor, _end_minor) \
  40                 VOP_REG_VER_MASK(off, _mask, s, false, \
  41                                  _major, _begin_minor, _end_minor)
  42
  43
  44 static const uint32_t formats_win_full[] = {
  45         DRM_FORMAT_XRGB8888,
  46         DRM_FORMAT_ARGB8888,
  47         DRM_FORMAT_XBGR8888,
  48         DRM_FORMAT_ABGR8888,
  49         DRM_FORMAT_RGB888,
  50         DRM_FORMAT_BGR888,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_BGR565,
  53         DRM_FORMAT_NV12,
  54         DRM_FORMAT_NV16,
  55         DRM_FORMAT_NV24,
  56         DRM_FORMAT_NV12_10,
  57         DRM_FORMAT_NV16_10,
  58         DRM_FORMAT_NV24_10,
  59 };
  60
  61 static const uint32_t formats_win_lite[] = {
  62         DRM_FORMAT_XRGB8888,
  63         DRM_FORMAT_ARGB8888,
  64         DRM_FORMAT_XBGR8888,
  65         DRM_FORMAT_ABGR8888,
  66         DRM_FORMAT_RGB888,
  67         DRM_FORMAT_BGR888,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_BGR565,
  70 };
  71
  72 static const struct vop_scl_extension rk3288_win_full_scl_ext = {
  73         .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
  74         .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
  75         .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
  76         .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
  77         .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
  78         .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
  79         .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
  80         .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
  81         .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
  82         .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
  83         .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
  84         .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
  85         .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
  86         .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
  87         .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
  88         .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
  89         .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
  90         .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
  91         .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
  92         .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
  93         .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
  94 };
  95
  96 static const struct vop_scl_regs rk3288_win_full_scl = {
  97         .ext = &rk3288_win_full_scl_ext,
  98         .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
  99         .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
 100         .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
 101         .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
 102 };
 103
 104 static const struct vop_win_phy rk3288_win01_data = {
 105         .scl = &rk3288_win_full_scl,
 106         .data_formats = formats_win_full,
 107         .nformats = ARRAY_SIZE(formats_win_full),
 108         .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
 109         .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
 110         .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 4),
 111         .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
 112         .xmirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 21, 3, 2, -1),
 113         .ymirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 22, 3, 2, -1),
 114         .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
 115         .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
 116         .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
 117         .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
 118         .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
 119         .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
 120         .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
 121         .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffffffff, 0),
 122         .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xffffffff, 0),
 123 };
 124
 125 static const struct vop_win_phy rk3288_win23_data = {
 126         .data_formats = formats_win_lite,
 127         .nformats = ARRAY_SIZE(formats_win_lite),
 128         .gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
 129         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4),
 130         .format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
 131         .rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
 132         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
 133         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
 134         .yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
 135         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
 136         .src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
 137         .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
 138 };
 139
 140 static const struct vop_win_phy rk3288_area1_data = {
 141         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 5),
 142         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO1, 0x0fff0fff, 0),
 143         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST1, 0x1fff1fff, 0),
 144         .yrgb_mst = VOP_REG(RK3288_WIN2_MST1, 0xffffffff, 0),
 145         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 16),
 146 };
 147
 148 static const struct vop_win_phy rk3288_area2_data = {
 149         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 6),
 150         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO2, 0x0fff0fff, 0),
 151         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST2, 0x1fff1fff, 0),
 152         .yrgb_mst = VOP_REG(RK3288_WIN2_MST2, 0xffffffff, 0),
 153         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 0),
 154 };
 155
 156 static const struct vop_win_phy rk3288_area3_data = {
 157         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 7),
 158         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO3, 0x0fff0fff, 0),
 159         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST3, 0x1fff1fff, 0),
 160         .yrgb_mst = VOP_REG(RK3288_WIN2_MST3, 0xffffffff, 0),
 161         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 16),
 162 };
 163
 164 static const struct vop_win_phy *rk3288_area_data[] = {
 165         &rk3288_area1_data,
 166         &rk3288_area2_data,
 167         &rk3288_area3_data
 168 };
 169
 170 static const struct vop_ctrl rk3288_ctrl_data = {
 171         .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
 172         .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 173         .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
 174         .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 175         .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
 176         .vact_st_end_f1 = VOP_REG(RK3288_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
 177         .vs_st_end_f1 = VOP_REG(RK3288_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
 178         .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
 179         .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
 180         .vpost_st_end_f1 = VOP_REG(RK3288_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
 181         .post_scl_factor = VOP_REG(RK3288_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
 182         .post_scl_ctrl = VOP_REG(RK3288_POST_SCL_CTRL, 0x3, 0),
 183
 184         .dsp_interlace = VOP_REG(RK3288_DSP_CTRL0, 0x1, 10),
 185         .auto_gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
 186         .dsp_layer_sel = VOP_REG(RK3288_DSP_CTRL1, 0xff, 8),
 187         .post_lb_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 18, 3, 2, -1),
 188         .global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1),
 189         .overlay_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 16, 3, 2, -1),
 190         .core_dclk_div = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 4, 3, 4, -1),
 191         .p2i_en = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 5, 3, 4, -1),
 192         .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11),
 193         .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
 194         .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
 195         .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
 196         .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
 197         .pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0xf, 4, 3, 0, 1),
 198         .dp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 16, 3, 2, -1),
 199         .rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 16, 3, 2, -1),
 200         .hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 20, 3, 2, -1),
 201         .edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 24, 3, 2, -1),
 202         .mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 28, 3, 2, -1),
 203
 204         .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
 205         .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
 206
 207         .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12),
 208         .dsp_ccir656_avg = VOP_REG(RK3288_DSP_CTRL0, 0x1, 20),
 209         .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
 210         .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0),
 211         .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
 212
 213         .afbdc_rstn = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 3),
 214         .afbdc_en = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 0),
 215         .afbdc_sel = VOP_REG(RK3399_AFBCD0_CTRL, 0x3, 1),
 216         .afbdc_format = VOP_REG(RK3399_AFBCD0_CTRL, 0x1f, 16),
 217         .afbdc_hreg_block_split = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 21),
 218         .afbdc_hdr_ptr = VOP_REG(RK3399_AFBCD0_HDR_PTR, 0xffffffff, 0),
 219         .afbdc_pic_size = VOP_REG(RK3399_AFBCD0_PIC_SIZE, 0xffffffff, 0),
 220
 221         .xmirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 22),
 222         .ymirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 23),
 223
 224         .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0),
 225
 226         .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
 227 };
 228
 229 /*
 230  * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
 231  * special support to get alpha blending working.  For now, just use overlay
 232  * window 3 for the drm cursor.
 233  *
 234  */
 235 static const struct vop_win_data rk3288_vop_win_data[] = {
 236         { .base = 0x00, .phy = &rk3288_win01_data,
 237           .type = DRM_PLANE_TYPE_PRIMARY },
 238         { .base = 0x40, .phy = &rk3288_win01_data,
 239           .type = DRM_PLANE_TYPE_OVERLAY },
 240         { .base = 0x00, .phy = &rk3288_win23_data,
 241           .type = DRM_PLANE_TYPE_OVERLAY,
 242           .area = rk3288_area_data,
 243           .area_size = ARRAY_SIZE(rk3288_area_data), },
 244         { .base = 0x50, .phy = &rk3288_win23_data,
 245           .type = DRM_PLANE_TYPE_CURSOR,
 246           .area = rk3288_area_data,
 247           .area_size = ARRAY_SIZE(rk3288_area_data), },
 248 };
 249
 250 static const int rk3288_vop_intrs[] = {
 251         DSP_HOLD_VALID_INTR,
 252         FS_INTR,
 253         LINE_FLAG_INTR,
 254         BUS_ERROR_INTR,
 255 };
 256
 257 static const struct vop_intr rk3288_vop_intr = {
 258         .intrs = rk3288_vop_intrs,
 259         .nintrs = ARRAY_SIZE(rk3288_vop_intrs),
 260         .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
 261         .status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
 262         .enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
 263         .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
 264 };
 265
 266 static const struct vop_data rk3288_vop = {
 267         .version = VOP_VERSION(3, 1),
 268         .feature = VOP_FEATURE_OUTPUT_10BIT,
 269         .intr = &rk3288_vop_intr,
 270         .ctrl = &rk3288_ctrl_data,
 271         .win = rk3288_vop_win_data,
 272         .win_size = ARRAY_SIZE(rk3288_vop_win_data),
 273 };
 274
 275 static const int rk3368_vop_intrs[] = {
 276         FS_INTR,
 277         FS_NEW_INTR,
 278         ADDR_SAME_INTR,
 279         LINE_FLAG_INTR,
 280         LINE_FLAG1_INTR,
 281         BUS_ERROR_INTR,
 282         WIN0_EMPTY_INTR,
 283         WIN1_EMPTY_INTR,
 284         WIN2_EMPTY_INTR,
 285         WIN3_EMPTY_INTR,
 286         HWC_EMPTY_INTR,
 287         POST_BUF_EMPTY_INTR,
 288         PWM_GEN_INTR,
 289         DSP_HOLD_VALID_INTR,
 290 };
 291
 292 static const struct vop_intr rk3368_vop_intr = {
 293         .intrs = rk3368_vop_intrs,
 294         .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
 295         .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0),
 296         .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16),
 297         .status = VOP_REG_MASK(RK3368_INTR_STATUS, 0x3fff, 0),
 298         .enable = VOP_REG_MASK(RK3368_INTR_EN, 0x3fff, 0),
 299         .clear = VOP_REG_MASK(RK3368_INTR_CLEAR, 0x3fff, 0),
 300 };
 301
 302 static const struct vop_win_phy rk3368_win23_data = {
 303         .data_formats = formats_win_lite,
 304         .nformats = ARRAY_SIZE(formats_win_lite),
 305         .gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0),
 306         .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4),
 307         .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5),
 308         .ymirror = VOP_REG(RK3368_WIN2_CTRL1, 0x1, 15),
 309         .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20),
 310         .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0),
 311         .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0),
 312         .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0),
 313         .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0),
 314         .src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
 315         .dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xff, 0),
 316 };
 317
 318 static const struct vop_win_phy rk3368_area1_data = {
 319         .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 8),
 320         .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 9),
 321         .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 23),
 322         .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO1, 0x0fff0fff, 0),
 323         .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST1, 0x1fff1fff, 0),
 324         .yrgb_mst = VOP_REG(RK3368_WIN2_MST1, 0xffffffff, 0),
 325         .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 16),
 326 };
 327
 328 static const struct vop_win_phy rk3368_area2_data = {
 329         .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 12),
 330         .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 13),
 331         .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 26),
 332         .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO2, 0x0fff0fff, 0),
 333         .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST2, 0x1fff1fff, 0),
 334         .yrgb_mst = VOP_REG(RK3368_WIN2_MST2, 0xffffffff, 0),
 335         .yrgb_vir = VOP_REG(RK3368_WIN2_VIR2_3, 0x1fff, 0),
 336 };
 337
 338 static const struct vop_win_phy rk3368_area3_data = {
 339         .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 16),
 340         .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 17),
 341         .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 29),
 342         .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO3, 0x0fff0fff, 0),
 343         .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST3, 0x1fff1fff, 0),
 344         .yrgb_mst = VOP_REG(RK3368_WIN2_MST3, 0xffffffff, 0),
 345         .yrgb_vir = VOP_REG(RK3368_WIN2_VIR2_3, 0x1fff, 16),
 346 };
 347
 348 static const struct vop_win_phy *rk3368_area_data[] = {
 349         &rk3368_area1_data,
 350         &rk3368_area2_data,
 351         &rk3368_area3_data
 352 };
 353
 354 static const struct vop_win_data rk3368_vop_win_data[] = {
 355         { .base = 0x00, .phy = &rk3288_win01_data,
 356           .type = DRM_PLANE_TYPE_PRIMARY },
 357         { .base = 0x40, .phy = &rk3288_win01_data,
 358           .type = DRM_PLANE_TYPE_OVERLAY },
 359         { .base = 0x00, .phy = &rk3368_win23_data,
 360           .type = DRM_PLANE_TYPE_OVERLAY,
 361           .area = rk3368_area_data,
 362           .area_size = ARRAY_SIZE(rk3368_area_data), },
 363         { .base = 0x50, .phy = &rk3368_win23_data,
 364           .type = DRM_PLANE_TYPE_CURSOR,
 365           .area = rk3368_area_data,
 366           .area_size = ARRAY_SIZE(rk3368_area_data), },
 367 };
 368
 369 static const struct vop_data rk3368_vop = {
 370         .version = VOP_VERSION(3, 2),
 371         .feature = VOP_FEATURE_OUTPUT_10BIT,
 372         .intr = &rk3368_vop_intr,
 373         .ctrl = &rk3288_ctrl_data,
 374         .win = rk3368_vop_win_data,
 375         .win_size = ARRAY_SIZE(rk3368_vop_win_data),
 376 };
 377
 378 static const struct vop_intr rk3366_vop_intr = {
 379         .intrs = rk3368_vop_intrs,
 380         .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
 381         .line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0),
 382         .line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16),
 383         .status = VOP_REG_MASK(RK3366_INTR_STATUS0, 0xffff, 0),
 384         .enable = VOP_REG_MASK(RK3366_INTR_EN0, 0xffff, 0),
 385         .clear = VOP_REG_MASK(RK3366_INTR_CLEAR0, 0xffff, 0),
 386 };
 387
 388 static const struct vop_data rk3366_vop = {
 389         .version = VOP_VERSION(3, 4),
 390         .feature = VOP_FEATURE_OUTPUT_10BIT,
 391         .intr = &rk3366_vop_intr,
 392         .ctrl = &rk3288_ctrl_data,
 393         .win = rk3368_vop_win_data,
 394         .win_size = ARRAY_SIZE(rk3368_vop_win_data),
 395 };
 396
 397 static const uint32_t vop_csc_y2r_bt601[] = {
 398         0x00000400, 0x0400059c, 0xfd25fea0, 0x07170400,
 399         0x00000000, 0xfffecab4, 0x00087932, 0xfff1d4f2,
 400 };
 401
 402 static const uint32_t vop_csc_y2r_bt601_12_235[] = {
 403         0x000004a8, 0x04a80662, 0xfcbffe6f, 0x081204a8,
 404         0x00000000, 0xfff2134e, 0x00087b58, 0xffeeb4b0,
 405 };
 406
 407 static const uint32_t vop_csc_r2y_bt601[] = {
 408         0x02590132, 0xff530075, 0x0200fead, 0xfe530200,
 409         0x0000ffad, 0x00000200, 0x00080200, 0x00080200,
 410 };
 411
 412 static const uint32_t vop_csc_r2y_bt601_12_235[] = {
 413         0x02040107, 0xff680064, 0x01c2fed6, 0xffb7fe87,
 414         0x0000ffb7, 0x00010200, 0x00080200, 0x00080200,
 415 };
 416
 417 static const uint32_t vop_csc_y2r_bt709[] = {
 418         0x000004a8, 0x04a8072c, 0xfddeff26, 0x087304a8,
 419         0x00000000, 0xfff08077, 0x0004cfed, 0xffedf1b8,
 420 };
 421
 422 static const uint32_t vop_csc_r2y_bt709[] = {
 423         0x027500bb, 0xff99003f, 0x01c2fea5, 0xfe6801c2,
 424         0xffd7fe68, 0x00010200, 0x00080200, 0x00080200,
 425 };
 426
 427 static const uint32_t vop_csc_y2r_bt2020[] = {
 428         0x000004a8, 0x04a806b6, 0xfd66ff40, 0x089004a8,
 429         0x00000000, 0xfff16bfc, 0x00058ae9, 0xffedb828,
 430 };
 431
 432 static const uint32_t vop_csc_r2y_bt2020[] = {
 433         0x025300e6, 0xff830034, 0x01c1febd, 0xfe6401c1,
 434         0x0000ffdc, 0x00010200, 0x00080200, 0x00080200,
 435 };
 436
 437 static const uint32_t vop_csc_r2r_bt709_to_bt2020[] = {
 438         0xfda606a4, 0xff80ffb5, 0xfff80488, 0xff99ffed,
 439         0x0000047a, 0x00000200, 0x00000200, 0x00000200,
 440 };
 441
 442 static const uint32_t vop_csc_r2r_bt2020_to_bt709[] = {
 443         0x01510282, 0x0047002c, 0x000c03ae, 0x005a0011,
 444         0x00000394, 0x00000200, 0x00000200, 0x00000200,
 445 };
 446
 447 static const struct vop_csc_table rk3399_csc_table = {
 448         .y2r_bt601              = vop_csc_y2r_bt601,
 449         .y2r_bt601_12_235       = vop_csc_y2r_bt601_12_235,
 450         .r2y_bt601              = vop_csc_r2y_bt601,
 451         .r2y_bt601_12_235       = vop_csc_r2y_bt601_12_235,
 452
 453         .y2r_bt709              = vop_csc_y2r_bt709,
 454         .r2y_bt709              = vop_csc_r2y_bt709,
 455
 456         .y2r_bt2020             = vop_csc_y2r_bt2020,
 457         .r2y_bt2020             = vop_csc_r2y_bt2020,
 458
 459         .r2r_bt709_to_bt2020    = vop_csc_r2r_bt709_to_bt2020,
 460         .r2r_bt2020_to_bt709    = vop_csc_r2r_bt2020_to_bt709,
 461 };
 462
 463 static const struct vop_csc rk3399_win0_csc = {
 464         .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 0),
 465         .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1),
 466         .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 2),
 467         .y2r_offset = RK3399_WIN0_YUV2YUV_Y2R,
 468         .r2r_offset = RK3399_WIN0_YUV2YUV_3X3,
 469         .r2y_offset = RK3399_WIN0_YUV2YUV_R2Y,
 470 };
 471
 472 static const struct vop_csc rk3399_win1_csc = {
 473         .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 8),
 474         .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 9),
 475         .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 10),
 476         .y2r_offset = RK3399_WIN1_YUV2YUV_Y2R,
 477         .r2r_offset = RK3399_WIN1_YUV2YUV_3X3,
 478         .r2y_offset = RK3399_WIN1_YUV2YUV_R2Y,
 479 };
 480
 481 static const struct vop_win_data rk3399_vop_win_data[] = {
 482         { .base = 0x00, .phy = &rk3288_win01_data, .csc = &rk3399_win0_csc,
 483           .type = DRM_PLANE_TYPE_PRIMARY },
 484         { .base = 0x40, .phy = &rk3288_win01_data, .csc = &rk3399_win1_csc,
 485           .type = DRM_PLANE_TYPE_OVERLAY },
 486         { .base = 0x00, .phy = &rk3368_win23_data,
 487           .type = DRM_PLANE_TYPE_OVERLAY,
 488           .area = rk3368_area_data,
 489           .area_size = ARRAY_SIZE(rk3368_area_data), },
 490         { .base = 0x50, .phy = &rk3368_win23_data,
 491           .type = DRM_PLANE_TYPE_CURSOR,
 492           .area = rk3368_area_data,
 493           .area_size = ARRAY_SIZE(rk3368_area_data), },
 494 };
 495
 496 static const struct vop_data rk3399_vop_big = {
 497         .version = VOP_VERSION(3, 5),
 498         .csc_table = &rk3399_csc_table,
 499         .feature = VOP_FEATURE_OUTPUT_10BIT | VOP_FEATURE_AFBDC,
 500         .intr = &rk3366_vop_intr,
 501         .ctrl = &rk3288_ctrl_data,
 502         .win = rk3399_vop_win_data,
 503         .win_size = ARRAY_SIZE(rk3399_vop_win_data),
 504 };
 505
 506 static const struct vop_win_data rk3399_vop_lit_win_data[] = {
 507         { .base = 0x00, .phy = &rk3288_win01_data, .csc = &rk3399_win0_csc,
 508           .type = DRM_PLANE_TYPE_PRIMARY },
 509         { .phy = NULL },
 510         { .base = 0x00, .phy = &rk3368_win23_data,
 511           .type = DRM_PLANE_TYPE_CURSOR,
 512           .area = rk3368_area_data,
 513           .area_size = ARRAY_SIZE(rk3368_area_data), },
 514         { .phy = NULL },
 515 };
 516
 517
 518 static const struct vop_data rk3399_vop_lit = {
 519         .version = VOP_VERSION(3, 6),
 520         .csc_table = &rk3399_csc_table,
 521         .intr = &rk3366_vop_intr,
 522         .ctrl = &rk3288_ctrl_data,
 523         .win = rk3399_vop_lit_win_data,
 524         .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data),
 525 };
 526
 527 static const struct vop_data rk322x_vop = {
 528         .version = VOP_VERSION(3, 7),
 529         .feature = VOP_FEATURE_OUTPUT_10BIT,
 530         .intr = &rk3366_vop_intr,
 531         .ctrl = &rk3288_ctrl_data,
 532         .win = rk3368_vop_win_data,
 533         .win_size = ARRAY_SIZE(rk3368_vop_win_data),
 534 };
 535
 536 static const struct vop_scl_regs rk3066_win_scl = {
 537         .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
 538         .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
 539         .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
 540         .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
 541 };
 542
 543 static const struct vop_win_phy rk3036_win0_data = {
 544         .scl = &rk3066_win_scl,
 545         .data_formats = formats_win_full,
 546         .nformats = ARRAY_SIZE(formats_win_full),
 547         .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
 548         .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
 549         .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
 550         .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
 551         .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
 552         .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
 553         .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
 554         .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
 555         .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
 556         .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16),
 557         .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18),
 558         .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0)
 559 };
 560
 561 static const struct vop_win_phy rk3036_win1_data = {
 562         .data_formats = formats_win_lite,
 563         .nformats = ARRAY_SIZE(formats_win_lite),
 564         .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
 565         .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
 566         .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
 567         .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
 568         .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
 569         .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
 570         .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
 571         .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
 572         .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19),
 573         .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1)
 574 };
 575
 576 static const struct vop_win_data rk3036_vop_win_data[] = {
 577         { .base = 0x00, .phy = &rk3036_win0_data,
 578           .type = DRM_PLANE_TYPE_PRIMARY },
 579         { .base = 0x00, .phy = &rk3036_win1_data,
 580           .type = DRM_PLANE_TYPE_CURSOR },
 581 };
 582
 583 static const int rk3036_vop_intrs[] = {
 584         DSP_HOLD_VALID_INTR,
 585         FS_INTR,
 586         LINE_FLAG_INTR,
 587         BUS_ERROR_INTR,
 588 };
 589
 590 static const struct vop_intr rk3036_intr = {
 591         .intrs = rk3036_vop_intrs,
 592         .nintrs = ARRAY_SIZE(rk3036_vop_intrs),
 593         .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
 594         .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
 595         .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
 596         .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
 597 };
 598
 599 static const struct vop_ctrl rk3036_ctrl_data = {
 600         .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
 601         .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
 602         .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24),
 603         .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
 604         .dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8),
 605         .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 606         .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
 607         .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 608         .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
 609         .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
 610 };
 611
 612 static const struct vop_data rk3036_vop = {
 613         .version = VOP_VERSION(2, 2),
 614         .ctrl = &rk3036_ctrl_data,
 615         .intr = &rk3036_intr,
 616         .win = rk3036_vop_win_data,
 617         .win_size = ARRAY_SIZE(rk3036_vop_win_data),
 618 };
 619
 620 static const struct of_device_id vop_driver_dt_match[] = {
 621         { .compatible = "rockchip,rk3036-vop",
 622           .data = &rk3036_vop },
 623         { .compatible = "rockchip,rk3288-vop",
 624           .data = &rk3288_vop },
 625         { .compatible = "rockchip,rk3368-vop",
 626           .data = &rk3368_vop },
 627         { .compatible = "rockchip,rk3366-vop",
 628           .data = &rk3366_vop },
 629         { .compatible = "rockchip,rk3399-vop-big",
 630           .data = &rk3399_vop_big },
 631         { .compatible = "rockchip,rk3399-vop-lit",
 632           .data = &rk3399_vop_lit },
 633         { .compatible = "rockchip,rk322x-vop",
 634           .data = &rk322x_vop },
 635         {},
 636 };
 637 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
 638
 639 static int vop_probe(struct platform_device *pdev)
 640 {
 641         struct device *dev = &pdev->dev;
 642
 643         if (!dev->of_node) {
 644                 dev_err(dev, "can't find vop devices\n");
 645                 return -ENODEV;
 646         }
 647
 648         return component_add(dev, &vop_component_ops);
 649 }
 650
 651 static int vop_remove(struct platform_device *pdev)
 652 {
 653         component_del(&pdev->dev, &vop_component_ops);
 654
 655         return 0;
 656 }
 657
 658 struct platform_driver vop_platform_driver = {
 659         .probe = vop_probe,
 660         .remove = vop_remove,
 661         .driver = {
 662                 .name = "rockchip-vop",
 663                 .owner = THIS_MODULE,
 664                 .of_match_table = of_match_ptr(vop_driver_dt_match),
 665         },
 666 };
 667
 668 module_platform_driver(vop_platform_driver);
 669
 670 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
 671 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
 672 MODULE_LICENSE("GPL v2");