drivers/gpu/drm/rockchip/rockchip_vop_reg.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drmP.h>
  16
  17 #include <linux/kernel.h>
  18 #include <linux/component.h>
  19
  20 #include "rockchip_drm_vop.h"
  21 #include "rockchip_vop_reg.h"
  22
  23 #define VOP_REG_VER_MASK(off, _mask, s, _write_mask, _major, \
  24                          _begin_minor, _end_minor) \
  25                 {.offset = off, \
  26                  .mask = _mask, \
  27                  .shift = s, \
  28                  .write_mask = _write_mask, \
  29                  .major = _major, \
  30                  .begin_minor = _begin_minor, \
  31                  .end_minor = _end_minor,}
  32
  33 #define VOP_REG(off, _mask, s) \
  34                 VOP_REG_VER_MASK(off, _mask, s, false, 0, 0, -1)
  35
  36 #define VOP_REG_MASK(off, _mask, s) \
  37                 VOP_REG_VER_MASK(off, _mask, s, true, 0, 0, -1)
  38
  39 #define VOP_REG_VER(off, _mask, s, _major, _begin_minor, _end_minor) \
  40                 VOP_REG_VER_MASK(off, _mask, s, false, \
  41                                  _major, _begin_minor, _end_minor)
  42
  43
  44 static const uint32_t formats_win_full[] = {
  45         DRM_FORMAT_XRGB8888,
  46         DRM_FORMAT_ARGB8888,
  47         DRM_FORMAT_XBGR8888,
  48         DRM_FORMAT_ABGR8888,
  49         DRM_FORMAT_RGB888,
  50         DRM_FORMAT_BGR888,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_BGR565,
  53         DRM_FORMAT_NV12,
  54         DRM_FORMAT_NV16,
  55         DRM_FORMAT_NV24,
  56         DRM_FORMAT_NV12_10,
  57         DRM_FORMAT_NV16_10,
  58         DRM_FORMAT_NV24_10,
  59 };
  60
  61 static const uint32_t formats_win_lite[] = {
  62         DRM_FORMAT_XRGB8888,
  63         DRM_FORMAT_ARGB8888,
  64         DRM_FORMAT_XBGR8888,
  65         DRM_FORMAT_ABGR8888,
  66         DRM_FORMAT_RGB888,
  67         DRM_FORMAT_BGR888,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_BGR565,
  70 };
  71
  72 static const struct vop_scl_extension rk3288_win_full_scl_ext = {
  73         .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
  74         .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
  75         .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
  76         .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
  77         .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
  78         .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
  79         .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
  80         .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
  81         .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
  82         .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
  83         .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
  84         .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
  85         .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
  86         .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
  87         .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
  88         .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
  89         .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
  90         .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
  91         .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
  92         .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
  93         .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
  94 };
  95
  96 static const struct vop_scl_regs rk3288_win_full_scl = {
  97         .ext = &rk3288_win_full_scl_ext,
  98         .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
  99         .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
 100         .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
 101         .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
 102 };
 103
 104 static const struct vop_win_phy rk3288_win01_data = {
 105         .scl = &rk3288_win_full_scl,
 106         .data_formats = formats_win_full,
 107         .nformats = ARRAY_SIZE(formats_win_full),
 108         .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
 109         .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
 110         .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 4),
 111         .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
 112         .xmirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 21, 3, 2, -1),
 113         .ymirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 22, 3, 2, -1),
 114         .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
 115         .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
 116         .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
 117         .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
 118         .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
 119         .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
 120         .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
 121         .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffffffff, 0),
 122         .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xffffffff, 0),
 123         .channel = VOP_REG_VER(RK3288_WIN0_CTRL2, 0xff, 0, 3, 8, 8),
 124 };
 125
 126 static const struct vop_win_phy rk3288_win23_data = {
 127         .data_formats = formats_win_lite,
 128         .nformats = ARRAY_SIZE(formats_win_lite),
 129         .gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
 130         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4),
 131         .format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
 132         .rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
 133         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
 134         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
 135         .yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
 136         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
 137         .src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
 138         .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
 139 };
 140
 141 static const struct vop_win_phy rk3288_area1_data = {
 142         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 5),
 143         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO1, 0x0fff0fff, 0),
 144         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST1, 0x1fff1fff, 0),
 145         .yrgb_mst = VOP_REG(RK3288_WIN2_MST1, 0xffffffff, 0),
 146         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 16),
 147 };
 148
 149 static const struct vop_win_phy rk3288_area2_data = {
 150         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 6),
 151         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO2, 0x0fff0fff, 0),
 152         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST2, 0x1fff1fff, 0),
 153         .yrgb_mst = VOP_REG(RK3288_WIN2_MST2, 0xffffffff, 0),
 154         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 0),
 155 };
 156
 157 static const struct vop_win_phy rk3288_area3_data = {
 158         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 7),
 159         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO3, 0x0fff0fff, 0),
 160         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST3, 0x1fff1fff, 0),
 161         .yrgb_mst = VOP_REG(RK3288_WIN2_MST3, 0xffffffff, 0),
 162         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 16),
 163 };
 164
 165 static const struct vop_win_phy *rk3288_area_data[] = {
 166         &rk3288_area1_data,
 167         &rk3288_area2_data,
 168         &rk3288_area3_data
 169 };
 170
 171 static const struct vop_ctrl rk3288_ctrl_data = {
 172         .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
 173         .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 174         .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
 175         .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 176         .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
 177         .vact_st_end_f1 = VOP_REG(RK3288_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
 178         .vs_st_end_f1 = VOP_REG(RK3288_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
 179         .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
 180         .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
 181         .vpost_st_end_f1 = VOP_REG(RK3288_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
 182         .post_scl_factor = VOP_REG(RK3288_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
 183         .post_scl_ctrl = VOP_REG(RK3288_POST_SCL_CTRL, 0x3, 0),
 184
 185         .dsp_interlace = VOP_REG(RK3288_DSP_CTRL0, 0x1, 10),
 186         .auto_gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
 187         .dsp_layer_sel = VOP_REG(RK3288_DSP_CTRL1, 0xff, 8),
 188         .post_lb_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 18, 3, 2, -1),
 189         .global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1),
 190         .overlay_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 16, 3, 2, -1),
 191         .core_dclk_div = VOP_REG_VER(RK3366_DSP_CTRL0, 0x1, 4, 3, 4, -1),
 192         .p2i_en = VOP_REG_VER(RK3366_DSP_CTRL0, 0x1, 5, 3, 4, -1),
 193         .dclk_ddr = VOP_REG_VER(RK3366_DSP_CTRL0, 0x1, 8, 3, 4, -1),
 194         .dp_en = VOP_REG_VER(RK3399_SYS_CTRL, 0x1, 11, 3, 5, -1),
 195         .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
 196         .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
 197         .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
 198         .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
 199         .dclk_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0x1, 7, 3, 0, 1),
 200         .pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0x7, 4, 3, 0, 1),
 201         .dp_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL0, 0x1, 19, 3, 0, 1),
 202         .dp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 16, 3, 2, -1),
 203         .rgb_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL0, 0x1, 19, 3, 0, 1),
 204         .rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 16, 3, 2, -1),
 205         .hdmi_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL0, 0x1, 23, 3, 0, 1),
 206         .hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 20, 3, 2, -1),
 207         .edp_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 27, 3, 0, 1),
 208         .edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 24, 3, 2, -1),
 209         .mipi_dclk_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x1, 31, 3, 0, 1),
 210         .mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0x7, 28, 3, 2, -1),
 211
 212         .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
 213         .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
 214
 215         .dsp_out_yuv = VOP_REG_VER(RK3399_POST_SCL_CTRL, 0x1, 2, 3, 5, -1),
 216         .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12),
 217         .dsp_ccir656_avg = VOP_REG(RK3288_DSP_CTRL0, 0x1, 20),
 218         .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
 219         .update_gamma_lut = VOP_REG_VER(RK3288_DSP_CTRL1, 0x1, 7, 3, 5, -1),
 220         .lut_buffer_index = VOP_REG_VER(RK3399_DBG_POST_REG1, 0x1, 1, 3, 5, -1),
 221         .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0),
 222         .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
 223
 224         .afbdc_rstn = VOP_REG_VER(RK3399_AFBCD0_CTRL, 0x1, 3, 3, 5, -1),
 225         .afbdc_en = VOP_REG_VER(RK3399_AFBCD0_CTRL, 0x1, 0, 3, 5, -1),
 226         .afbdc_sel = VOP_REG_VER(RK3399_AFBCD0_CTRL, 0x3, 1, 3, 5, -1),
 227         .afbdc_format = VOP_REG_VER(RK3399_AFBCD0_CTRL, 0x1f, 16, 3, 5, -1),
 228         .afbdc_hreg_block_split = VOP_REG_VER(RK3399_AFBCD0_CTRL,
 229                                               0x1, 21, 3, 5, -1),
 230         .afbdc_hdr_ptr = VOP_REG_VER(RK3399_AFBCD0_HDR_PTR, 0xffffffff,
 231                                      0, 3, 5, -1),
 232         .afbdc_pic_size = VOP_REG_VER(RK3399_AFBCD0_PIC_SIZE, 0xffffffff,
 233                                       0, 3, 5, -1),
 234         .cabc_config_mode = VOP_REG_VER(RK3399_CABC_CTRL0, 0x3, 1, 3, 5, -1),
 235         .cabc_calc_pixel_num = VOP_REG_VER(RK3399_CABC_CTRL0, 0x7fffff, 4,
 236                                            3, 5, -1),
 237         .cabc_handle_en = VOP_REG_VER(RK3399_CABC_CTRL0, 0x1, 3, 3, 5, -1),
 238         .cabc_en = VOP_REG_VER(RK3399_CABC_CTRL0, 0x1, 0, 3, 5, -1),
 239         .cabc_total_num = VOP_REG_VER(RK3399_CABC_CTRL1, 0x7fffff, 4, 3, 5, -1),
 240         .cabc_lut_en = VOP_REG_VER(RK3399_CABC_CTRL1, 0x1, 0, 3, 5, -1),
 241         .cabc_stage_up_mode = VOP_REG_VER(RK3399_CABC_CTRL2, 0x1, 19, 3, 5, -1),
 242         .cabc_stage_up = VOP_REG_VER(RK3399_CABC_CTRL2, 0x1ff, 8, 3, 5, -1),
 243         .cabc_stage_down = VOP_REG_VER(RK3399_CABC_CTRL2, 0xff, 0, 3, 5, -1),
 244         .cabc_global_dn = VOP_REG_VER(RK3399_CABC_CTRL3, 0xff, 0, 3, 5, -1),
 245         .cabc_global_dn_limit_en = VOP_REG_VER(RK3399_CABC_CTRL3, 0x1, 8,
 246                                                3, 5, -1),
 247
 248         .xmirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 22),
 249         .ymirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 23),
 250
 251         .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0),
 252
 253         .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
 254 };
 255
 256 /*
 257  * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
 258  * special support to get alpha blending working.  For now, just use overlay
 259  * window 3 for the drm cursor.
 260  *
 261  */
 262 static const struct vop_win_data rk3288_vop_win_data[] = {
 263         { .base = 0x00, .phy = &rk3288_win01_data,
 264           .type = DRM_PLANE_TYPE_PRIMARY },
 265         { .base = 0x40, .phy = &rk3288_win01_data,
 266           .type = DRM_PLANE_TYPE_OVERLAY },
 267         { .base = 0x00, .phy = &rk3288_win23_data,
 268           .type = DRM_PLANE_TYPE_OVERLAY,
 269           .area = rk3288_area_data,
 270           .area_size = ARRAY_SIZE(rk3288_area_data), },
 271         { .base = 0x50, .phy = &rk3288_win23_data,
 272           .type = DRM_PLANE_TYPE_CURSOR,
 273           .area = rk3288_area_data,
 274           .area_size = ARRAY_SIZE(rk3288_area_data), },
 275 };
 276
 277 static const int rk3288_vop_intrs[] = {
 278         DSP_HOLD_VALID_INTR,
 279         FS_INTR,
 280         LINE_FLAG_INTR,
 281         BUS_ERROR_INTR,
 282 };
 283
 284 static const struct vop_intr rk3288_vop_intr = {
 285         .intrs = rk3288_vop_intrs,
 286         .nintrs = ARRAY_SIZE(rk3288_vop_intrs),
 287         .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
 288         .status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
 289         .enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
 290         .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
 291 };
 292
 293 static const struct vop_data rk3288_vop = {
 294         .version = VOP_VERSION(3, 1),
 295         .feature = VOP_FEATURE_OUTPUT_10BIT,
 296         .max_input = {4096, 8192},
 297         /*
 298          * TODO: rk3288 have two vop, big one support 3840x2160,
 299          * little one only support 2560x1600.
 300          * Now force use 3840x2160.
 301          */
 302         .max_output = {3840, 2160},
 303         .intr = &rk3288_vop_intr,
 304         .ctrl = &rk3288_ctrl_data,
 305         .win = rk3288_vop_win_data,
 306         .win_size = ARRAY_SIZE(rk3288_vop_win_data),
 307 };
 308
 309 static const int rk3368_vop_intrs[] = {
 310         FS_INTR,
 311         FS_NEW_INTR,
 312         ADDR_SAME_INTR,
 313         LINE_FLAG_INTR,
 314         LINE_FLAG1_INTR,
 315         BUS_ERROR_INTR,
 316         WIN0_EMPTY_INTR,
 317         WIN1_EMPTY_INTR,
 318         WIN2_EMPTY_INTR,
 319         WIN3_EMPTY_INTR,
 320         HWC_EMPTY_INTR,
 321         POST_BUF_EMPTY_INTR,
 322         PWM_GEN_INTR,
 323         DSP_HOLD_VALID_INTR,
 324 };
 325
 326 static const struct vop_intr rk3368_vop_intr = {
 327         .intrs = rk3368_vop_intrs,
 328         .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
 329         .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0),
 330         .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16),
 331         .status = VOP_REG_MASK(RK3368_INTR_STATUS, 0x3fff, 0),
 332         .enable = VOP_REG_MASK(RK3368_INTR_EN, 0x3fff, 0),
 333         .clear = VOP_REG_MASK(RK3368_INTR_CLEAR, 0x3fff, 0),
 334 };
 335
 336 static const struct vop_win_phy rk3368_win23_data = {
 337         .data_formats = formats_win_lite,
 338         .nformats = ARRAY_SIZE(formats_win_lite),
 339         .gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0),
 340         .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4),
 341         .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5),
 342         .ymirror = VOP_REG(RK3368_WIN2_CTRL1, 0x1, 15),
 343         .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20),
 344         .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0),
 345         .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0),
 346         .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0),
 347         .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0),
 348         .src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
 349         .dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xff, 0),
 350 };
 351
 352 static const struct vop_win_phy rk3368_area1_data = {
 353         .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 8),
 354         .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 9),
 355         .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 23),
 356         .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO1, 0x0fff0fff, 0),
 357         .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST1, 0x1fff1fff, 0),
 358         .yrgb_mst = VOP_REG(RK3368_WIN2_MST1, 0xffffffff, 0),
 359         .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 16),
 360 };
 361
 362 static const struct vop_win_phy rk3368_area2_data = {
 363         .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 12),
 364         .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 13),
 365         .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 26),
 366         .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO2, 0x0fff0fff, 0),
 367         .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST2, 0x1fff1fff, 0),
 368         .yrgb_mst = VOP_REG(RK3368_WIN2_MST2, 0xffffffff, 0),
 369         .yrgb_vir = VOP_REG(RK3368_WIN2_VIR2_3, 0x1fff, 0),
 370 };
 371
 372 static const struct vop_win_phy rk3368_area3_data = {
 373         .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 16),
 374         .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 17),
 375         .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 29),
 376         .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO3, 0x0fff0fff, 0),
 377         .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST3, 0x1fff1fff, 0),
 378         .yrgb_mst = VOP_REG(RK3368_WIN2_MST3, 0xffffffff, 0),
 379         .yrgb_vir = VOP_REG(RK3368_WIN2_VIR2_3, 0x1fff, 16),
 380 };
 381
 382 static const struct vop_win_phy *rk3368_area_data[] = {
 383         &rk3368_area1_data,
 384         &rk3368_area2_data,
 385         &rk3368_area3_data
 386 };
 387
 388 static const struct vop_win_data rk3368_vop_win_data[] = {
 389         { .base = 0x00, .phy = &rk3288_win01_data,
 390           .type = DRM_PLANE_TYPE_PRIMARY },
 391         { .base = 0x40, .phy = &rk3288_win01_data,
 392           .type = DRM_PLANE_TYPE_OVERLAY },
 393         { .base = 0x00, .phy = &rk3368_win23_data,
 394           .type = DRM_PLANE_TYPE_OVERLAY,
 395           .area = rk3368_area_data,
 396           .area_size = ARRAY_SIZE(rk3368_area_data), },
 397         { .base = 0x50, .phy = &rk3368_win23_data,
 398           .type = DRM_PLANE_TYPE_CURSOR,
 399           .area = rk3368_area_data,
 400           .area_size = ARRAY_SIZE(rk3368_area_data), },
 401 };
 402
 403 static const struct vop_data rk3368_vop = {
 404         .version = VOP_VERSION(3, 2),
 405         .max_input = {4096, 8192},
 406         .max_output = {4096, 2160},
 407         .intr = &rk3368_vop_intr,
 408         .ctrl = &rk3288_ctrl_data,
 409         .win = rk3368_vop_win_data,
 410         .win_size = ARRAY_SIZE(rk3368_vop_win_data),
 411 };
 412
 413 static const struct vop_intr rk3366_vop_intr = {
 414         .intrs = rk3368_vop_intrs,
 415         .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
 416         .line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0),
 417         .line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16),
 418         .status = VOP_REG_MASK(RK3366_INTR_STATUS0, 0xffff, 0),
 419         .enable = VOP_REG_MASK(RK3366_INTR_EN0, 0xffff, 0),
 420         .clear = VOP_REG_MASK(RK3366_INTR_CLEAR0, 0xffff, 0),
 421 };
 422
 423 static const struct vop_data rk3366_vop = {
 424         .version = VOP_VERSION(3, 4),
 425         .max_input = {4096, 8192},
 426         .max_output = {4096, 2160},
 427         .intr = &rk3366_vop_intr,
 428         .ctrl = &rk3288_ctrl_data,
 429         .win = rk3368_vop_win_data,
 430         .win_size = ARRAY_SIZE(rk3368_vop_win_data),
 431 };
 432
 433 static const uint32_t vop_csc_y2r_bt601[] = {
 434         0x00000400, 0x0400059c, 0xfd25fea0, 0x07170400,
 435         0x00000000, 0xfffecab4, 0x00087932, 0xfff1d4f2,
 436 };
 437
 438 static const uint32_t vop_csc_y2r_bt601_12_235[] = {
 439         0x000004a8, 0x04a80662, 0xfcbffe6f, 0x081204a8,
 440         0x00000000, 0xfff2134e, 0x00087b58, 0xffeeb4b0,
 441 };
 442
 443 static const uint32_t vop_csc_r2y_bt601[] = {
 444         0x02590132, 0xff530075, 0x0200fead, 0xfe530200,
 445         0x0000ffad, 0x00000200, 0x00080200, 0x00080200,
 446 };
 447
 448 static const uint32_t vop_csc_r2y_bt601_12_235[] = {
 449         0x02040107, 0xff680064, 0x01c2fed6, 0xffb7fe87,
 450         0x0000ffb7, 0x00010200, 0x00080200, 0x00080200,
 451 };
 452
 453 static const uint32_t vop_csc_y2r_bt709[] = {
 454         0x000004a8, 0x04a8072c, 0xfddeff26, 0x087304a8,
 455         0x00000000, 0xfff08077, 0x0004cfed, 0xffedf1b8,
 456 };
 457
 458 static const uint32_t vop_csc_r2y_bt709[] = {
 459         0x027500bb, 0xff99003f, 0x01c2fea5, 0xfe6801c2,
 460         0x0000ffd7, 0x00010200, 0x00080200, 0x00080200,
 461 };
 462
 463 static const uint32_t vop_csc_y2r_bt2020[] = {
 464         0x000004a8, 0x04a806b6, 0xfd66ff40, 0x089004a8,
 465         0x00000000, 0xfff16bfc, 0x00058ae9, 0xffedb828,
 466 };
 467
 468 static const uint32_t vop_csc_r2y_bt2020[] = {
 469         0x025300e6, 0xff830034, 0x01c1febd, 0xfe6401c1,
 470         0x0000ffdc, 0x00010200, 0x00080200, 0x00080200,
 471 };
 472
 473 static const uint32_t vop_csc_r2r_bt709_to_bt2020[] = {
 474         0xfda606a4, 0xff80ffb5, 0xfff80488, 0xff99ffed,
 475         0x0000047a, 0x00000200, 0x00000200, 0x00000200,
 476 };
 477
 478 static const uint32_t vop_csc_r2r_bt2020_to_bt709[] = {
 479         0x01510282, 0x0047002c, 0x000c03ae, 0x005a0011,
 480         0x00000394, 0x00000200, 0x00000200, 0x00000200,
 481 };
 482
 483 static const struct vop_csc_table rk3399_csc_table = {
 484         .y2r_bt601              = vop_csc_y2r_bt601,
 485         .y2r_bt601_12_235       = vop_csc_y2r_bt601_12_235,
 486         .r2y_bt601              = vop_csc_r2y_bt601,
 487         .r2y_bt601_12_235       = vop_csc_r2y_bt601_12_235,
 488
 489         .y2r_bt709              = vop_csc_y2r_bt709,
 490         .r2y_bt709              = vop_csc_r2y_bt709,
 491
 492         .y2r_bt2020             = vop_csc_y2r_bt2020,
 493         .r2y_bt2020             = vop_csc_r2y_bt2020,
 494
 495         .r2r_bt709_to_bt2020    = vop_csc_r2r_bt709_to_bt2020,
 496         .r2r_bt2020_to_bt709    = vop_csc_r2r_bt2020_to_bt709,
 497 };
 498
 499 static const struct vop_csc rk3399_win0_csc = {
 500         .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 0),
 501         .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1),
 502         .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 2),
 503         .y2r_offset = RK3399_WIN0_YUV2YUV_Y2R,
 504         .r2r_offset = RK3399_WIN0_YUV2YUV_3X3,
 505         .r2y_offset = RK3399_WIN0_YUV2YUV_R2Y,
 506 };
 507
 508 static const struct vop_csc rk3399_win1_csc = {
 509         .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 8),
 510         .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 9),
 511         .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 10),
 512         .y2r_offset = RK3399_WIN1_YUV2YUV_Y2R,
 513         .r2r_offset = RK3399_WIN1_YUV2YUV_3X3,
 514         .r2y_offset = RK3399_WIN1_YUV2YUV_R2Y,
 515 };
 516
 517 static const struct vop_win_data rk3399_vop_win_data[] = {
 518         { .base = 0x00, .phy = &rk3288_win01_data, .csc = &rk3399_win0_csc,
 519           .type = DRM_PLANE_TYPE_PRIMARY },
 520         { .base = 0x40, .phy = &rk3288_win01_data, .csc = &rk3399_win1_csc,
 521           .type = DRM_PLANE_TYPE_OVERLAY },
 522         { .base = 0x00, .phy = &rk3368_win23_data,
 523           .type = DRM_PLANE_TYPE_OVERLAY,
 524           .area = rk3368_area_data,
 525           .area_size = ARRAY_SIZE(rk3368_area_data), },
 526         { .base = 0x50, .phy = &rk3368_win23_data,
 527           .type = DRM_PLANE_TYPE_CURSOR,
 528           .area = rk3368_area_data,
 529           .area_size = ARRAY_SIZE(rk3368_area_data), },
 530 };
 531
 532 static const struct vop_data rk3399_vop_big = {
 533         .version = VOP_VERSION(3, 5),
 534         .csc_table = &rk3399_csc_table,
 535         .feature = VOP_FEATURE_OUTPUT_10BIT | VOP_FEATURE_AFBDC,
 536         .max_input = {4096, 8192},
 537         .max_output = {4096, 2160},
 538         .intr = &rk3366_vop_intr,
 539         .ctrl = &rk3288_ctrl_data,
 540         .win = rk3399_vop_win_data,
 541         .win_size = ARRAY_SIZE(rk3399_vop_win_data),
 542 };
 543
 544 static const struct vop_win_data rk3399_vop_lit_win_data[] = {
 545         { .base = 0x00, .phy = &rk3288_win01_data, .csc = &rk3399_win0_csc,
 546           .type = DRM_PLANE_TYPE_PRIMARY },
 547         { .phy = NULL },
 548         { .base = 0x00, .phy = &rk3368_win23_data,
 549           .type = DRM_PLANE_TYPE_CURSOR,
 550           .area = rk3368_area_data,
 551           .area_size = ARRAY_SIZE(rk3368_area_data), },
 552         { .phy = NULL },
 553 };
 554
 555
 556 static const struct vop_data rk3399_vop_lit = {
 557         .version = VOP_VERSION(3, 6),
 558         .csc_table = &rk3399_csc_table,
 559         .max_input = {4096, 8192},
 560         .max_output = {2560, 1600},
 561         .intr = &rk3366_vop_intr,
 562         .ctrl = &rk3288_ctrl_data,
 563         .win = rk3399_vop_lit_win_data,
 564         .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data),
 565 };
 566
 567 static const struct vop_win_data rk322x_vop_win_data[] = {
 568         { .base = 0x00, .phy = &rk3288_win01_data,
 569           .type = DRM_PLANE_TYPE_PRIMARY },
 570         { .base = 0x40, .phy = &rk3288_win01_data,
 571           .type = DRM_PLANE_TYPE_CURSOR },
 572 };
 573
 574 static const struct vop_data rk322x_vop = {
 575         .version = VOP_VERSION(3, 7),
 576         .feature = VOP_FEATURE_OUTPUT_10BIT,
 577         .max_input = {4096, 8192},
 578         .max_output = {4096, 2160},
 579         .intr = &rk3366_vop_intr,
 580         .ctrl = &rk3288_ctrl_data,
 581         .win = rk322x_vop_win_data,
 582         .win_size = ARRAY_SIZE(rk322x_vop_win_data),
 583 };
 584
 585 static const struct vop_ctrl rk3328_ctrl_data = {
 586         .standby = VOP_REG(RK3328_SYS_CTRL, 0x1, 22),
 587         .auto_gate_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 23),
 588         .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 589         .hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0),
 590         .vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 591         .vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0),
 592         .vact_st_end_f1 = VOP_REG(RK3328_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
 593         .vs_st_end_f1 = VOP_REG(RK3328_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
 594         .hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
 595         .vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
 596         .vpost_st_end_f1 = VOP_REG(RK3328_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
 597         .dsp_interlace = VOP_REG(RK3328_DSP_CTRL0, 0x1, 10),
 598         .dsp_layer_sel = VOP_REG(RK3328_DSP_CTRL1, 0xff, 8),
 599         .post_lb_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 18),
 600         .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11),
 601         .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16),
 602         .core_dclk_div = VOP_REG(RK3328_DSP_CTRL0, 0x1, 4),
 603         .p2i_en = VOP_REG(RK3328_DSP_CTRL0, 0x1, 5),
 604         .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12),
 605         .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13),
 606         .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14),
 607         .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15),
 608         .tve_dclk_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 24),
 609         .tve_dclk_pol = VOP_REG(RK3328_SYS_CTRL, 0x1, 25),
 610         .tve_sw_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 26),
 611         .sw_uv_offset_en  = VOP_REG(RK3328_SYS_CTRL, 0x1, 27),
 612         .sw_genlock   = VOP_REG(RK3328_SYS_CTRL, 0x1, 28),
 613         .sw_dac_sel = VOP_REG(RK3328_SYS_CTRL, 0x1, 29),
 614         .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 16),
 615         .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 20),
 616         .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 24),
 617         .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0x7, 28),
 618         .rgb_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 19),
 619         .hdmi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 23),
 620         .edp_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 27),
 621         .mipi_dclk_pol = VOP_REG(RK3328_DSP_CTRL1, 0x1, 31),
 622
 623         .dither_down = VOP_REG(RK3328_DSP_CTRL1, 0xf, 1),
 624         .dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6),
 625
 626         .dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12),
 627         .dsp_ccir656_avg = VOP_REG(RK3328_DSP_CTRL0, 0x1, 20),
 628         .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18),
 629         .dsp_lut_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 0),
 630         .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0),
 631
 632         .xmirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 22),
 633         .ymirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 23),
 634
 635         .dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0),
 636
 637         .cfg_done = VOP_REG(RK3328_REG_CFG_DONE, 0x1, 0),
 638 };
 639
 640 static const struct vop_intr rk3328_vop_intr = {
 641         .intrs = rk3368_vop_intrs,
 642         .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
 643         .line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0),
 644         .line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16),
 645         .status = VOP_REG_MASK(RK3328_INTR_STATUS0, 0xffff, 0),
 646         .enable = VOP_REG_MASK(RK3328_INTR_EN0, 0xffff, 0),
 647         .clear = VOP_REG_MASK(RK3328_INTR_CLEAR0, 0xffff, 0),
 648 };
 649
 650 static const struct vop_win_data rk3328_vop_win_data[] = {
 651         { .base = 0xd0, .phy = &rk3288_win01_data,
 652           .type = DRM_PLANE_TYPE_PRIMARY },
 653         { .base = 0x1d0, .phy = &rk3288_win01_data,
 654           .type = DRM_PLANE_TYPE_OVERLAY },
 655         { .base = 0x2d0, .phy = &rk3288_win01_data,
 656           .type = DRM_PLANE_TYPE_CURSOR },
 657 };
 658
 659 static const struct vop_data rk3328_vop = {
 660         .version = VOP_VERSION(3, 8),
 661         .feature = VOP_FEATURE_OUTPUT_10BIT,
 662         .max_input = {4096, 8192},
 663         .max_output = {4096, 2160},
 664         .intr = &rk3328_vop_intr,
 665         .ctrl = &rk3328_ctrl_data,
 666         .win = rk3328_vop_win_data,
 667         .win_size = ARRAY_SIZE(rk3328_vop_win_data),
 668 };
 669
 670 static const struct vop_scl_regs rk3066_win_scl = {
 671         .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
 672         .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
 673         .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
 674         .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
 675 };
 676
 677 static const struct vop_win_phy rk3036_win0_data = {
 678         .scl = &rk3066_win_scl,
 679         .data_formats = formats_win_full,
 680         .nformats = ARRAY_SIZE(formats_win_full),
 681         .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
 682         .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
 683         .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
 684         .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
 685         .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
 686         .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
 687         .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
 688         .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
 689         .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
 690         .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16),
 691         .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18),
 692         .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0)
 693 };
 694
 695 static const struct vop_win_phy rk3036_win1_data = {
 696         .data_formats = formats_win_lite,
 697         .nformats = ARRAY_SIZE(formats_win_lite),
 698         .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
 699         .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
 700         .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
 701         .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
 702         .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
 703         .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
 704         .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
 705         .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
 706         .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19),
 707         .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1)
 708 };
 709
 710 static const struct vop_win_data rk3036_vop_win_data[] = {
 711         { .base = 0x00, .phy = &rk3036_win0_data,
 712           .type = DRM_PLANE_TYPE_PRIMARY },
 713         { .base = 0x00, .phy = &rk3036_win1_data,
 714           .type = DRM_PLANE_TYPE_CURSOR },
 715 };
 716
 717 static const int rk3036_vop_intrs[] = {
 718         DSP_HOLD_VALID_INTR,
 719         FS_INTR,
 720         LINE_FLAG_INTR,
 721         BUS_ERROR_INTR,
 722 };
 723
 724 static const struct vop_intr rk3036_intr = {
 725         .intrs = rk3036_vop_intrs,
 726         .nintrs = ARRAY_SIZE(rk3036_vop_intrs),
 727         .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
 728         .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
 729         .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
 730         .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
 731 };
 732
 733 static const struct vop_ctrl rk3036_ctrl_data = {
 734         .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
 735         .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
 736         .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24),
 737         .dclk_pol = VOP_REG(RK3036_DSP_CTRL0, 0x1, 7),
 738         .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0x7, 4),
 739         .dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8),
 740         .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 741         .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
 742         .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 743         .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
 744         .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
 745 };
 746
 747 static const struct vop_data rk3036_vop = {
 748         .version = VOP_VERSION(2, 2),
 749         .max_input = {1920, 1080},
 750         .max_output = {1920, 1080},
 751         .ctrl = &rk3036_ctrl_data,
 752         .intr = &rk3036_intr,
 753         .win = rk3036_vop_win_data,
 754         .win_size = ARRAY_SIZE(rk3036_vop_win_data),
 755 };
 756
 757 static const int rk3366_vop_lit_intrs[] = {
 758         FS_INTR,
 759         FS_NEW_INTR,
 760         ADDR_SAME_INTR,
 761         LINE_FLAG_INTR,
 762         LINE_FLAG1_INTR,
 763         BUS_ERROR_INTR,
 764         WIN0_EMPTY_INTR,
 765         WIN1_EMPTY_INTR,
 766         DSP_HOLD_VALID_INTR,
 767 };
 768
 769 static const struct vop_scl_regs rk3366_lit_win_scl = {
 770         .scale_yrgb_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
 771         .scale_yrgb_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
 772         .scale_cbcr_x = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
 773         .scale_cbcr_y = VOP_REG(RK3366_LIT_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
 774 };
 775
 776 static const struct vop_win_phy rk3366_lit_win0_data = {
 777         .scl = &rk3366_lit_win_scl,
 778         .data_formats = formats_win_full,
 779         .nformats = ARRAY_SIZE(formats_win_full),
 780
 781         .enable = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 0),
 782         .format = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x7, 1),
 783         .rb_swap = VOP_REG(RK3366_LIT_WIN0_CTRL0, 0x1, 12),
 784         .act_info = VOP_REG(RK3366_LIT_WIN0_ACT_INFO, 0xffffffff, 0),
 785         .dsp_info = VOP_REG(RK3366_LIT_WIN0_DSP_INFO, 0xffffffff, 0),
 786         .dsp_st = VOP_REG(RK3366_LIT_WIN0_DSP_ST, 0xffffffff, 0),
 787         .yrgb_mst = VOP_REG(RK3366_LIT_WIN0_YRGB_MST0, 0xffffffff, 0),
 788         .uv_mst = VOP_REG(RK3366_LIT_WIN0_CBR_MST0, 0xffffffff, 0),
 789         .yrgb_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 0),
 790         .uv_vir = VOP_REG(RK3366_LIT_WIN0_VIR, 0x1fff, 16),
 791
 792         .alpha_mode = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 1),
 793         .alpha_en = VOP_REG(RK3366_LIT_WIN0_ALPHA_CTRL, 0x1, 0),
 794         .key_color = VOP_REG(RK3366_LIT_WIN0_COLOR_KEY, 0xffffff, 0),
 795         .key_en = VOP_REG(RK3366_LIT_WIN0_COLOR_KEY, 0x1, 24),
 796 };
 797
 798 static const struct vop_win_phy rk3366_lit_win1_data = {
 799         .data_formats = formats_win_lite,
 800         .nformats = ARRAY_SIZE(formats_win_lite),
 801
 802         .enable = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 0),
 803         .format = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x7, 4),
 804         .rb_swap = VOP_REG(RK3366_LIT_WIN1_CTRL0, 0x1, 12),
 805         .dsp_info = VOP_REG(RK3366_LIT_WIN1_DSP_INFO, 0xffffffff, 0),
 806         .dsp_st = VOP_REG(RK3366_LIT_WIN1_DSP_ST, 0xffffffff, 0),
 807         .yrgb_mst = VOP_REG(RK3366_LIT_WIN1_MST, 0xffffffff, 0),
 808         .yrgb_vir = VOP_REG(RK3366_LIT_WIN1_VIR, 0x1fff, 0),
 809
 810         .alpha_mode = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 1),
 811         .alpha_en = VOP_REG(RK3366_LIT_WIN1_ALPHA_CTRL, 0x1, 0),
 812         .key_color = VOP_REG(RK3366_LIT_WIN1_COLOR_KEY, 0xffffff, 0),
 813         .key_en = VOP_REG(RK3366_LIT_WIN1_COLOR_KEY, 0x1, 24),
 814 };
 815
 816 static const struct vop_win_data rk3366_vop_lit_win_data[] = {
 817         { .base = 0x00, .phy = &rk3366_lit_win0_data,
 818           .type = DRM_PLANE_TYPE_PRIMARY },
 819         { .base = 0x00, .phy = &rk3366_lit_win1_data,
 820           .type = DRM_PLANE_TYPE_CURSOR },
 821 };
 822
 823 static const struct vop_intr rk3366_lit_intr = {
 824         .intrs = rk3366_vop_lit_intrs,
 825         .nintrs = ARRAY_SIZE(rk3366_vop_lit_intrs),
 826         .line_flag_num[0] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 0),
 827         .line_flag_num[1] = VOP_REG(RK3366_LIT_LINE_FLAG, 0xfff, 16),
 828         .status = VOP_REG_MASK(RK3366_LIT_INTR_STATUS, 0xffff, 0),
 829         .enable = VOP_REG_MASK(RK3366_LIT_INTR_EN, 0xffff, 0),
 830         .clear = VOP_REG_MASK(RK3366_LIT_INTR_CLEAR, 0xffff, 0),
 831 };
 832
 833 static const struct vop_ctrl rk3366_lit_ctrl_data = {
 834         .standby = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 1),
 835         .htotal_pw = VOP_REG(RK3366_LIT_DSP_HTOTAL_HS_END, 0x0fff0fff, 0),
 836         .hact_st_end = VOP_REG(RK3366_LIT_DSP_HACT_ST_END, 0x0fff0fff, 0),
 837         .vtotal_pw = VOP_REG(RK3366_LIT_DSP_VTOTAL_VS_END, 0x0fff0fff, 0),
 838         .vact_st_end = VOP_REG(RK3366_LIT_DSP_VACT_ST_END, 0x0fff0fff, 0),
 839         .vact_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VACT_ST_END_F1, 0x0fff0fff, 0),
 840         .vs_st_end_f1 = VOP_REG(RK3366_LIT_DSP_VS_ST_END_F1, 0x0fff0fff, 0),
 841         .dsp_interlace = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 0),
 842         .global_regdone_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 13),
 843         .auto_gate_en = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 0),
 844         .dsp_layer_sel = VOP_REG(RK3366_LIT_SYS_CTRL0, 0x1, 1),
 845         .overlay_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 4),
 846         .core_dclk_div = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 13),
 847         .dclk_ddr = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 14),
 848         .rgb_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 0),
 849         .rgb_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 2),
 850         .hdmi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 8),
 851         .hdmi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 10),
 852         .lvds_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 16),
 853         .lvds_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 18),
 854         .mipi_en = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 24),
 855         .mipi_pin_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x7, 26),
 856         .mipi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 25),
 857         .lvds_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 17),
 858         .hdmi_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 9),
 859         .rgb_dclk_pol = VOP_REG(RK3366_LIT_DSP_CTRL0, 0x1, 1),
 860         .dither_up = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 2),
 861         .dither_down = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x7, 6),
 862         .dsp_data_swap = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1f, 9),
 863         .dsp_ccir656_avg = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 5),
 864         .dsp_black = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 15),
 865         .dsp_blank = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 14),
 866         .dsp_outzero = VOP_REG(RK3366_LIT_SYS_CTRL2, 0x1, 3),
 867         .dsp_lut_en = VOP_REG(RK3366_LIT_DSP_CTRL2, 0x1, 5),
 868         .out_mode = VOP_REG(RK3366_LIT_DSP_CTRL2, 0xf, 16),
 869         .dsp_background = VOP_REG(RK3366_LIT_DSP_BG, 0x00ffffff, 0),
 870         .cfg_done = VOP_REG(RK3366_LIT_REG_CFG_DONE, 0x1, 0),
 871 };
 872
 873 static const struct vop_data rk3366_vop_lit = {
 874         .max_input = {1920, 8192},
 875         .max_output = {1920, 1080},
 876         .ctrl = &rk3366_lit_ctrl_data,
 877         .intr = &rk3366_lit_intr,
 878         .win = rk3366_vop_lit_win_data,
 879         .win_size = ARRAY_SIZE(rk3366_vop_lit_win_data),
 880 };
 881
 882 static const struct of_device_id vop_driver_dt_match[] = {
 883         { .compatible = "rockchip,rk3036-vop",
 884           .data = &rk3036_vop },
 885         { .compatible = "rockchip,rk3288-vop",
 886           .data = &rk3288_vop },
 887         { .compatible = "rockchip,rk3368-vop",
 888           .data = &rk3368_vop },
 889         { .compatible = "rockchip,rk3366-vop",
 890           .data = &rk3366_vop },
 891         { .compatible = "rockchip,rk3366-vop-lit",
 892           .data = &rk3366_vop_lit },
 893         { .compatible = "rockchip,rk3399-vop-big",
 894           .data = &rk3399_vop_big },
 895         { .compatible = "rockchip,rk3399-vop-lit",
 896           .data = &rk3399_vop_lit },
 897         { .compatible = "rockchip,rk322x-vop",
 898           .data = &rk322x_vop },
 899         { .compatible = "rockchip,rk3328-vop",
 900           .data = &rk3328_vop },
 901         {},
 902 };
 903 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
 904
 905 static int vop_probe(struct platform_device *pdev)
 906 {
 907         struct device *dev = &pdev->dev;
 908
 909         if (!dev->of_node) {
 910                 dev_err(dev, "can't find vop devices\n");
 911                 return -ENODEV;
 912         }
 913
 914         return component_add(dev, &vop_component_ops);
 915 }
 916
 917 static int vop_remove(struct platform_device *pdev)
 918 {
 919         component_del(&pdev->dev, &vop_component_ops);
 920
 921         return 0;
 922 }
 923
 924 struct platform_driver vop_platform_driver = {
 925         .probe = vop_probe,
 926         .remove = vop_remove,
 927         .driver = {
 928                 .name = "rockchip-vop",
 929                 .owner = THIS_MODULE,
 930                 .of_match_table = of_match_ptr(vop_driver_dt_match),
 931         },
 932 };
 933
 934 module_platform_driver(vop_platform_driver);
 935
 936 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
 937 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
 938 MODULE_LICENSE("GPL v2");