drivers/gpu/drm/rockchip/rockchip_vop_reg.c

   1 /*
   2  * Copyright (C) Fuzhou Rockchip Electronics Co.Ltd
   3  * Author:Mark Yao <mark.yao@rock-chips.com>
   4  *
   5  * This software is licensed under the terms of the GNU General Public
   6  * License version 2, as published by the Free Software Foundation, and
   7  * may be copied, distributed, and modified under those terms.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <drm/drmP.h>
  16
  17 #include <linux/kernel.h>
  18 #include <linux/component.h>
  19
  20 #include "rockchip_drm_vop.h"
  21 #include "rockchip_vop_reg.h"
  22
  23 #define VOP_REG_VER_MASK(off, _mask, s, _write_mask, _major, \
  24                          _begin_minor, _end_minor) \
  25                 {.offset = off, \
  26                  .mask = _mask, \
  27                  .shift = s, \
  28                  .write_mask = _write_mask, \
  29                  .major = _major, \
  30                  .begin_minor = _begin_minor, \
  31                  .end_minor = _end_minor,}
  32
  33 #define VOP_REG(off, _mask, s) \
  34                 VOP_REG_VER_MASK(off, _mask, s, false, 0, 0, -1)
  35
  36 #define VOP_REG_MASK(off, _mask, s) \
  37                 VOP_REG_VER_MASK(off, _mask, s, true, 0, 0, -1)
  38
  39 #define VOP_REG_VER(off, _mask, s, _major, _begin_minor, _end_minor) \
  40                 VOP_REG_VER_MASK(off, _mask, s, false, \
  41                                  _major, _begin_minor, _end_minor)
  42
  43
  44 static const uint32_t formats_win_full[] = {
  45         DRM_FORMAT_XRGB8888,
  46         DRM_FORMAT_ARGB8888,
  47         DRM_FORMAT_XBGR8888,
  48         DRM_FORMAT_ABGR8888,
  49         DRM_FORMAT_RGB888,
  50         DRM_FORMAT_BGR888,
  51         DRM_FORMAT_RGB565,
  52         DRM_FORMAT_BGR565,
  53         DRM_FORMAT_NV12,
  54         DRM_FORMAT_NV16,
  55         DRM_FORMAT_NV24,
  56         DRM_FORMAT_NV12_10,
  57         DRM_FORMAT_NV16_10,
  58         DRM_FORMAT_NV24_10,
  59 };
  60
  61 static const uint32_t formats_win_lite[] = {
  62         DRM_FORMAT_XRGB8888,
  63         DRM_FORMAT_ARGB8888,
  64         DRM_FORMAT_XBGR8888,
  65         DRM_FORMAT_ABGR8888,
  66         DRM_FORMAT_RGB888,
  67         DRM_FORMAT_BGR888,
  68         DRM_FORMAT_RGB565,
  69         DRM_FORMAT_BGR565,
  70 };
  71
  72 static const struct vop_scl_extension rk3288_win_full_scl_ext = {
  73         .cbcr_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 31),
  74         .cbcr_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 30),
  75         .cbcr_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 28),
  76         .cbcr_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 26),
  77         .cbcr_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 24),
  78         .yrgb_vsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 23),
  79         .yrgb_vsu_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 22),
  80         .yrgb_hsd_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 20),
  81         .yrgb_ver_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 18),
  82         .yrgb_hor_scl_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 16),
  83         .line_load_mode = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 15),
  84         .cbcr_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0x7, 12),
  85         .yrgb_axi_gather_num = VOP_REG(RK3288_WIN0_CTRL1, 0xf, 8),
  86         .vsd_cbcr_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 7),
  87         .vsd_cbcr_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 6),
  88         .vsd_yrgb_gt2 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 5),
  89         .vsd_yrgb_gt4 = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 4),
  90         .bic_coe_sel = VOP_REG(RK3288_WIN0_CTRL1, 0x3, 2),
  91         .cbcr_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 1),
  92         .yrgb_axi_gather_en = VOP_REG(RK3288_WIN0_CTRL1, 0x1, 0),
  93         .lb_mode = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 5),
  94 };
  95
  96 static const struct vop_scl_regs rk3288_win_full_scl = {
  97         .ext = &rk3288_win_full_scl_ext,
  98         .scale_yrgb_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
  99         .scale_yrgb_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
 100         .scale_cbcr_x = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
 101         .scale_cbcr_y = VOP_REG(RK3288_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
 102 };
 103
 104 static const struct vop_win_phy rk3288_win01_data = {
 105         .scl = &rk3288_win_full_scl,
 106         .data_formats = formats_win_full,
 107         .nformats = ARRAY_SIZE(formats_win_full),
 108         .enable = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 0),
 109         .format = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 1),
 110         .fmt_10 = VOP_REG(RK3288_WIN0_CTRL0, 0x7, 4),
 111         .rb_swap = VOP_REG(RK3288_WIN0_CTRL0, 0x1, 12),
 112         .xmirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 21, 3, 2, -1),
 113         .ymirror = VOP_REG_VER(RK3368_WIN0_CTRL0, 0x1, 22, 3, 2, -1),
 114         .act_info = VOP_REG(RK3288_WIN0_ACT_INFO, 0x1fff1fff, 0),
 115         .dsp_info = VOP_REG(RK3288_WIN0_DSP_INFO, 0x0fff0fff, 0),
 116         .dsp_st = VOP_REG(RK3288_WIN0_DSP_ST, 0x1fff1fff, 0),
 117         .yrgb_mst = VOP_REG(RK3288_WIN0_YRGB_MST, 0xffffffff, 0),
 118         .uv_mst = VOP_REG(RK3288_WIN0_CBR_MST, 0xffffffff, 0),
 119         .yrgb_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 0),
 120         .uv_vir = VOP_REG(RK3288_WIN0_VIR, 0x3fff, 16),
 121         .src_alpha_ctl = VOP_REG(RK3288_WIN0_SRC_ALPHA_CTRL, 0xffffffff, 0),
 122         .dst_alpha_ctl = VOP_REG(RK3288_WIN0_DST_ALPHA_CTRL, 0xffffffff, 0),
 123 };
 124
 125 static const struct vop_win_phy rk3288_win23_data = {
 126         .data_formats = formats_win_lite,
 127         .nformats = ARRAY_SIZE(formats_win_lite),
 128         .gate = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 0),
 129         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 4),
 130         .format = VOP_REG(RK3288_WIN2_CTRL0, 0x7, 1),
 131         .rb_swap = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 12),
 132         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO0, 0x0fff0fff, 0),
 133         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST0, 0x1fff1fff, 0),
 134         .yrgb_mst = VOP_REG(RK3288_WIN2_MST0, 0xffffffff, 0),
 135         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 0),
 136         .src_alpha_ctl = VOP_REG(RK3288_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
 137         .dst_alpha_ctl = VOP_REG(RK3288_WIN2_DST_ALPHA_CTRL, 0xff, 0),
 138 };
 139
 140 static const struct vop_win_phy rk3288_area1_data = {
 141         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 5),
 142         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO1, 0x0fff0fff, 0),
 143         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST1, 0x1fff1fff, 0),
 144         .yrgb_mst = VOP_REG(RK3288_WIN2_MST1, 0xffffffff, 0),
 145         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR0_1, 0x1fff, 16),
 146 };
 147
 148 static const struct vop_win_phy rk3288_area2_data = {
 149         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 6),
 150         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO2, 0x0fff0fff, 0),
 151         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST2, 0x1fff1fff, 0),
 152         .yrgb_mst = VOP_REG(RK3288_WIN2_MST2, 0xffffffff, 0),
 153         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 0),
 154 };
 155
 156 static const struct vop_win_phy rk3288_area3_data = {
 157         .enable = VOP_REG(RK3288_WIN2_CTRL0, 0x1, 7),
 158         .dsp_info = VOP_REG(RK3288_WIN2_DSP_INFO3, 0x0fff0fff, 0),
 159         .dsp_st = VOP_REG(RK3288_WIN2_DSP_ST3, 0x1fff1fff, 0),
 160         .yrgb_mst = VOP_REG(RK3288_WIN2_MST3, 0xffffffff, 0),
 161         .yrgb_vir = VOP_REG(RK3288_WIN2_VIR2_3, 0x1fff, 16),
 162 };
 163
 164 static const struct vop_win_phy *rk3288_area_data[] = {
 165         &rk3288_area1_data,
 166         &rk3288_area2_data,
 167         &rk3288_area3_data
 168 };
 169
 170 static const struct vop_ctrl rk3288_ctrl_data = {
 171         .standby = VOP_REG(RK3288_SYS_CTRL, 0x1, 22),
 172         .htotal_pw = VOP_REG(RK3288_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 173         .hact_st_end = VOP_REG(RK3288_DSP_HACT_ST_END, 0x1fff1fff, 0),
 174         .vtotal_pw = VOP_REG(RK3288_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 175         .vact_st_end = VOP_REG(RK3288_DSP_VACT_ST_END, 0x1fff1fff, 0),
 176         .vact_st_end_f1 = VOP_REG(RK3288_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
 177         .vs_st_end_f1 = VOP_REG(RK3288_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
 178         .hpost_st_end = VOP_REG(RK3288_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
 179         .vpost_st_end = VOP_REG(RK3288_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
 180         .vpost_st_end_f1 = VOP_REG(RK3288_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
 181         .post_scl_factor = VOP_REG(RK3288_POST_SCL_FACTOR_YRGB, 0xffffffff, 0),
 182         .post_scl_ctrl = VOP_REG(RK3288_POST_SCL_CTRL, 0x3, 0),
 183
 184         .dsp_interlace = VOP_REG(RK3288_DSP_CTRL0, 0x1, 10),
 185         .auto_gate_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 23),
 186         .dsp_layer_sel = VOP_REG(RK3288_DSP_CTRL1, 0xff, 8),
 187         .post_lb_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 18, 3, 2, -1),
 188         .global_regdone_en = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 11, 3, 2, -1),
 189         .overlay_mode = VOP_REG_VER(RK3288_SYS_CTRL, 0x1, 16, 3, 2, -1),
 190         .core_dclk_div = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 4, 3, 4, -1),
 191         .p2i_en = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 5, 3, 4, -1),
 192         .dclk_ddr = VOP_REG_VER(RK3399_DSP_CTRL0, 0x1, 8, 3, 4, -1),
 193         .dp_en = VOP_REG(RK3399_SYS_CTRL, 0x1, 11),
 194         .rgb_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 12),
 195         .hdmi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 13),
 196         .edp_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 14),
 197         .mipi_en = VOP_REG(RK3288_SYS_CTRL, 0x1, 15),
 198         .pin_pol = VOP_REG_VER(RK3288_DSP_CTRL0, 0xf, 4, 3, 0, 1),
 199         .dp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 16, 3, 2, -1),
 200         .rgb_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 16, 3, 2, -1),
 201         .hdmi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 20, 3, 2, -1),
 202         .edp_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 24, 3, 2, -1),
 203         .mipi_pin_pol = VOP_REG_VER(RK3368_DSP_CTRL1, 0xf, 28, 3, 2, -1),
 204
 205         .dither_down = VOP_REG(RK3288_DSP_CTRL1, 0xf, 1),
 206         .dither_up = VOP_REG(RK3288_DSP_CTRL1, 0x1, 6),
 207
 208         .dsp_out_yuv = VOP_REG_VER(RK3399_POST_SCL_CTRL, 0x1, 2, 3, 5, -1),
 209         .dsp_data_swap = VOP_REG(RK3288_DSP_CTRL0, 0x1f, 12),
 210         .dsp_ccir656_avg = VOP_REG(RK3288_DSP_CTRL0, 0x1, 20),
 211         .dsp_blank = VOP_REG(RK3288_DSP_CTRL0, 0x3, 18),
 212         .dsp_lut_en = VOP_REG(RK3288_DSP_CTRL1, 0x1, 0),
 213         .out_mode = VOP_REG(RK3288_DSP_CTRL0, 0xf, 0),
 214
 215         .afbdc_rstn = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 3),
 216         .afbdc_en = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 0),
 217         .afbdc_sel = VOP_REG(RK3399_AFBCD0_CTRL, 0x3, 1),
 218         .afbdc_format = VOP_REG(RK3399_AFBCD0_CTRL, 0x1f, 16),
 219         .afbdc_hreg_block_split = VOP_REG(RK3399_AFBCD0_CTRL, 0x1, 21),
 220         .afbdc_hdr_ptr = VOP_REG(RK3399_AFBCD0_HDR_PTR, 0xffffffff, 0),
 221         .afbdc_pic_size = VOP_REG(RK3399_AFBCD0_PIC_SIZE, 0xffffffff, 0),
 222
 223         .xmirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 22),
 224         .ymirror = VOP_REG(RK3288_DSP_CTRL0, 0x1, 23),
 225
 226         .dsp_background = VOP_REG(RK3288_DSP_BG, 0xffffffff, 0),
 227
 228         .cfg_done = VOP_REG(RK3288_REG_CFG_DONE, 0x1, 0),
 229 };
 230
 231 /*
 232  * Note: rk3288 has a dedicated 'cursor' window, however, that window requires
 233  * special support to get alpha blending working.  For now, just use overlay
 234  * window 3 for the drm cursor.
 235  *
 236  */
 237 static const struct vop_win_data rk3288_vop_win_data[] = {
 238         { .base = 0x00, .phy = &rk3288_win01_data,
 239           .type = DRM_PLANE_TYPE_PRIMARY },
 240         { .base = 0x40, .phy = &rk3288_win01_data,
 241           .type = DRM_PLANE_TYPE_OVERLAY },
 242         { .base = 0x00, .phy = &rk3288_win23_data,
 243           .type = DRM_PLANE_TYPE_OVERLAY,
 244           .area = rk3288_area_data,
 245           .area_size = ARRAY_SIZE(rk3288_area_data), },
 246         { .base = 0x50, .phy = &rk3288_win23_data,
 247           .type = DRM_PLANE_TYPE_CURSOR,
 248           .area = rk3288_area_data,
 249           .area_size = ARRAY_SIZE(rk3288_area_data), },
 250 };
 251
 252 static const int rk3288_vop_intrs[] = {
 253         DSP_HOLD_VALID_INTR,
 254         FS_INTR,
 255         LINE_FLAG_INTR,
 256         BUS_ERROR_INTR,
 257 };
 258
 259 static const struct vop_intr rk3288_vop_intr = {
 260         .intrs = rk3288_vop_intrs,
 261         .nintrs = ARRAY_SIZE(rk3288_vop_intrs),
 262         .line_flag_num[0] = VOP_REG(RK3288_INTR_CTRL0, 0x1fff, 12),
 263         .status = VOP_REG(RK3288_INTR_CTRL0, 0xf, 0),
 264         .enable = VOP_REG(RK3288_INTR_CTRL0, 0xf, 4),
 265         .clear = VOP_REG(RK3288_INTR_CTRL0, 0xf, 8),
 266 };
 267
 268 static const struct vop_data rk3288_vop = {
 269         .version = VOP_VERSION(3, 1),
 270         .feature = VOP_FEATURE_OUTPUT_10BIT,
 271         .max_input = {4096, 8192},
 272         /*
 273          * TODO: rk3288 have two vop, big one support 3840x2160,
 274          * little one only support 2560x1600.
 275          * Now force use 3840x2160.
 276          */
 277         .max_output = {3840, 2160},
 278         .intr = &rk3288_vop_intr,
 279         .ctrl = &rk3288_ctrl_data,
 280         .win = rk3288_vop_win_data,
 281         .win_size = ARRAY_SIZE(rk3288_vop_win_data),
 282 };
 283
 284 static const int rk3368_vop_intrs[] = {
 285         FS_INTR,
 286         FS_NEW_INTR,
 287         ADDR_SAME_INTR,
 288         LINE_FLAG_INTR,
 289         LINE_FLAG1_INTR,
 290         BUS_ERROR_INTR,
 291         WIN0_EMPTY_INTR,
 292         WIN1_EMPTY_INTR,
 293         WIN2_EMPTY_INTR,
 294         WIN3_EMPTY_INTR,
 295         HWC_EMPTY_INTR,
 296         POST_BUF_EMPTY_INTR,
 297         PWM_GEN_INTR,
 298         DSP_HOLD_VALID_INTR,
 299 };
 300
 301 static const struct vop_intr rk3368_vop_intr = {
 302         .intrs = rk3368_vop_intrs,
 303         .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
 304         .line_flag_num[0] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 0),
 305         .line_flag_num[1] = VOP_REG(RK3368_LINE_FLAG, 0xffff, 16),
 306         .status = VOP_REG_MASK(RK3368_INTR_STATUS, 0x3fff, 0),
 307         .enable = VOP_REG_MASK(RK3368_INTR_EN, 0x3fff, 0),
 308         .clear = VOP_REG_MASK(RK3368_INTR_CLEAR, 0x3fff, 0),
 309 };
 310
 311 static const struct vop_win_phy rk3368_win23_data = {
 312         .data_formats = formats_win_lite,
 313         .nformats = ARRAY_SIZE(formats_win_lite),
 314         .gate = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 0),
 315         .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 4),
 316         .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 5),
 317         .ymirror = VOP_REG(RK3368_WIN2_CTRL1, 0x1, 15),
 318         .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 20),
 319         .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO0, 0x0fff0fff, 0),
 320         .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST0, 0x1fff1fff, 0),
 321         .yrgb_mst = VOP_REG(RK3368_WIN2_MST0, 0xffffffff, 0),
 322         .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 0),
 323         .src_alpha_ctl = VOP_REG(RK3368_WIN2_SRC_ALPHA_CTRL, 0xff, 0),
 324         .dst_alpha_ctl = VOP_REG(RK3368_WIN2_DST_ALPHA_CTRL, 0xff, 0),
 325 };
 326
 327 static const struct vop_win_phy rk3368_area1_data = {
 328         .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 8),
 329         .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 9),
 330         .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 23),
 331         .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO1, 0x0fff0fff, 0),
 332         .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST1, 0x1fff1fff, 0),
 333         .yrgb_mst = VOP_REG(RK3368_WIN2_MST1, 0xffffffff, 0),
 334         .yrgb_vir = VOP_REG(RK3368_WIN2_VIR0_1, 0x1fff, 16),
 335 };
 336
 337 static const struct vop_win_phy rk3368_area2_data = {
 338         .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 12),
 339         .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 13),
 340         .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 26),
 341         .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO2, 0x0fff0fff, 0),
 342         .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST2, 0x1fff1fff, 0),
 343         .yrgb_mst = VOP_REG(RK3368_WIN2_MST2, 0xffffffff, 0),
 344         .yrgb_vir = VOP_REG(RK3368_WIN2_VIR2_3, 0x1fff, 0),
 345 };
 346
 347 static const struct vop_win_phy rk3368_area3_data = {
 348         .enable = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 16),
 349         .format = VOP_REG(RK3368_WIN2_CTRL0, 0x3, 17),
 350         .rb_swap = VOP_REG(RK3368_WIN2_CTRL0, 0x1, 29),
 351         .dsp_info = VOP_REG(RK3368_WIN2_DSP_INFO3, 0x0fff0fff, 0),
 352         .dsp_st = VOP_REG(RK3368_WIN2_DSP_ST3, 0x1fff1fff, 0),
 353         .yrgb_mst = VOP_REG(RK3368_WIN2_MST3, 0xffffffff, 0),
 354         .yrgb_vir = VOP_REG(RK3368_WIN2_VIR2_3, 0x1fff, 16),
 355 };
 356
 357 static const struct vop_win_phy *rk3368_area_data[] = {
 358         &rk3368_area1_data,
 359         &rk3368_area2_data,
 360         &rk3368_area3_data
 361 };
 362
 363 static const struct vop_win_data rk3368_vop_win_data[] = {
 364         { .base = 0x00, .phy = &rk3288_win01_data,
 365           .type = DRM_PLANE_TYPE_PRIMARY },
 366         { .base = 0x40, .phy = &rk3288_win01_data,
 367           .type = DRM_PLANE_TYPE_OVERLAY },
 368         { .base = 0x00, .phy = &rk3368_win23_data,
 369           .type = DRM_PLANE_TYPE_OVERLAY,
 370           .area = rk3368_area_data,
 371           .area_size = ARRAY_SIZE(rk3368_area_data), },
 372         { .base = 0x50, .phy = &rk3368_win23_data,
 373           .type = DRM_PLANE_TYPE_CURSOR,
 374           .area = rk3368_area_data,
 375           .area_size = ARRAY_SIZE(rk3368_area_data), },
 376 };
 377
 378 static const struct vop_data rk3368_vop = {
 379         .version = VOP_VERSION(3, 2),
 380         .feature = VOP_FEATURE_OUTPUT_10BIT,
 381         .max_input = {4096, 8192},
 382         .max_output = {4096, 2160},
 383         .intr = &rk3368_vop_intr,
 384         .ctrl = &rk3288_ctrl_data,
 385         .win = rk3368_vop_win_data,
 386         .win_size = ARRAY_SIZE(rk3368_vop_win_data),
 387 };
 388
 389 static const struct vop_intr rk3366_vop_intr = {
 390         .intrs = rk3368_vop_intrs,
 391         .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
 392         .line_flag_num[0] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 0),
 393         .line_flag_num[1] = VOP_REG(RK3366_LINE_FLAG, 0xffff, 16),
 394         .status = VOP_REG_MASK(RK3366_INTR_STATUS0, 0xffff, 0),
 395         .enable = VOP_REG_MASK(RK3366_INTR_EN0, 0xffff, 0),
 396         .clear = VOP_REG_MASK(RK3366_INTR_CLEAR0, 0xffff, 0),
 397 };
 398
 399 static const struct vop_data rk3366_vop = {
 400         .version = VOP_VERSION(3, 4),
 401         .feature = VOP_FEATURE_OUTPUT_10BIT,
 402         .max_input = {4096, 8192},
 403         .max_output = {4096, 2160},
 404         .intr = &rk3366_vop_intr,
 405         .ctrl = &rk3288_ctrl_data,
 406         .win = rk3368_vop_win_data,
 407         .win_size = ARRAY_SIZE(rk3368_vop_win_data),
 408 };
 409
 410 static const uint32_t vop_csc_y2r_bt601[] = {
 411         0x00000400, 0x0400059c, 0xfd25fea0, 0x07170400,
 412         0x00000000, 0xfffecab4, 0x00087932, 0xfff1d4f2,
 413 };
 414
 415 static const uint32_t vop_csc_y2r_bt601_12_235[] = {
 416         0x000004a8, 0x04a80662, 0xfcbffe6f, 0x081204a8,
 417         0x00000000, 0xfff2134e, 0x00087b58, 0xffeeb4b0,
 418 };
 419
 420 static const uint32_t vop_csc_r2y_bt601[] = {
 421         0x02590132, 0xff530075, 0x0200fead, 0xfe530200,
 422         0x0000ffad, 0x00000200, 0x00080200, 0x00080200,
 423 };
 424
 425 static const uint32_t vop_csc_r2y_bt601_12_235[] = {
 426         0x02040107, 0xff680064, 0x01c2fed6, 0xffb7fe87,
 427         0x0000ffb7, 0x00010200, 0x00080200, 0x00080200,
 428 };
 429
 430 static const uint32_t vop_csc_y2r_bt709[] = {
 431         0x000004a8, 0x04a8072c, 0xfddeff26, 0x087304a8,
 432         0x00000000, 0xfff08077, 0x0004cfed, 0xffedf1b8,
 433 };
 434
 435 static const uint32_t vop_csc_r2y_bt709[] = {
 436         0x027500bb, 0xff99003f, 0x01c2fea5, 0xfe6801c2,
 437         0x0000ffd7, 0x00010200, 0x00080200, 0x00080200,
 438 };
 439
 440 static const uint32_t vop_csc_y2r_bt2020[] = {
 441         0x000004a8, 0x04a806b6, 0xfd66ff40, 0x089004a8,
 442         0x00000000, 0xfff16bfc, 0x00058ae9, 0xffedb828,
 443 };
 444
 445 static const uint32_t vop_csc_r2y_bt2020[] = {
 446         0x025300e6, 0xff830034, 0x01c1febd, 0xfe6401c1,
 447         0x0000ffdc, 0x00010200, 0x00080200, 0x00080200,
 448 };
 449
 450 static const uint32_t vop_csc_r2r_bt709_to_bt2020[] = {
 451         0xfda606a4, 0xff80ffb5, 0xfff80488, 0xff99ffed,
 452         0x0000047a, 0x00000200, 0x00000200, 0x00000200,
 453 };
 454
 455 static const uint32_t vop_csc_r2r_bt2020_to_bt709[] = {
 456         0x01510282, 0x0047002c, 0x000c03ae, 0x005a0011,
 457         0x00000394, 0x00000200, 0x00000200, 0x00000200,
 458 };
 459
 460 static const struct vop_csc_table rk3399_csc_table = {
 461         .y2r_bt601              = vop_csc_y2r_bt601,
 462         .y2r_bt601_12_235       = vop_csc_y2r_bt601_12_235,
 463         .r2y_bt601              = vop_csc_r2y_bt601,
 464         .r2y_bt601_12_235       = vop_csc_r2y_bt601_12_235,
 465
 466         .y2r_bt709              = vop_csc_y2r_bt709,
 467         .r2y_bt709              = vop_csc_r2y_bt709,
 468
 469         .y2r_bt2020             = vop_csc_y2r_bt2020,
 470         .r2y_bt2020             = vop_csc_r2y_bt2020,
 471
 472         .r2r_bt709_to_bt2020    = vop_csc_r2r_bt709_to_bt2020,
 473         .r2r_bt2020_to_bt709    = vop_csc_r2r_bt2020_to_bt709,
 474 };
 475
 476 static const struct vop_csc rk3399_win0_csc = {
 477         .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 0),
 478         .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 1),
 479         .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 2),
 480         .y2r_offset = RK3399_WIN0_YUV2YUV_Y2R,
 481         .r2r_offset = RK3399_WIN0_YUV2YUV_3X3,
 482         .r2y_offset = RK3399_WIN0_YUV2YUV_R2Y,
 483 };
 484
 485 static const struct vop_csc rk3399_win1_csc = {
 486         .r2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 8),
 487         .y2r_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 9),
 488         .r2y_en = VOP_REG(RK3399_YUV2YUV_WIN, 0x1, 10),
 489         .y2r_offset = RK3399_WIN1_YUV2YUV_Y2R,
 490         .r2r_offset = RK3399_WIN1_YUV2YUV_3X3,
 491         .r2y_offset = RK3399_WIN1_YUV2YUV_R2Y,
 492 };
 493
 494 static const struct vop_win_data rk3399_vop_win_data[] = {
 495         { .base = 0x00, .phy = &rk3288_win01_data, .csc = &rk3399_win0_csc,
 496           .type = DRM_PLANE_TYPE_PRIMARY },
 497         { .base = 0x40, .phy = &rk3288_win01_data, .csc = &rk3399_win1_csc,
 498           .type = DRM_PLANE_TYPE_OVERLAY },
 499         { .base = 0x00, .phy = &rk3368_win23_data,
 500           .type = DRM_PLANE_TYPE_OVERLAY,
 501           .area = rk3368_area_data,
 502           .area_size = ARRAY_SIZE(rk3368_area_data), },
 503         { .base = 0x50, .phy = &rk3368_win23_data,
 504           .type = DRM_PLANE_TYPE_CURSOR,
 505           .area = rk3368_area_data,
 506           .area_size = ARRAY_SIZE(rk3368_area_data), },
 507 };
 508
 509 static const struct vop_data rk3399_vop_big = {
 510         .version = VOP_VERSION(3, 5),
 511         .csc_table = &rk3399_csc_table,
 512         .feature = VOP_FEATURE_OUTPUT_10BIT | VOP_FEATURE_AFBDC,
 513         .max_input = {4096, 8192},
 514         .max_output = {4096, 2160},
 515         .intr = &rk3366_vop_intr,
 516         .ctrl = &rk3288_ctrl_data,
 517         .win = rk3399_vop_win_data,
 518         .win_size = ARRAY_SIZE(rk3399_vop_win_data),
 519 };
 520
 521 static const struct vop_win_data rk3399_vop_lit_win_data[] = {
 522         { .base = 0x00, .phy = &rk3288_win01_data, .csc = &rk3399_win0_csc,
 523           .type = DRM_PLANE_TYPE_PRIMARY },
 524         { .phy = NULL },
 525         { .base = 0x00, .phy = &rk3368_win23_data,
 526           .type = DRM_PLANE_TYPE_CURSOR,
 527           .area = rk3368_area_data,
 528           .area_size = ARRAY_SIZE(rk3368_area_data), },
 529         { .phy = NULL },
 530 };
 531
 532
 533 static const struct vop_data rk3399_vop_lit = {
 534         .version = VOP_VERSION(3, 6),
 535         .csc_table = &rk3399_csc_table,
 536         .max_input = {4096, 8192},
 537         .max_output = {2560, 1600},
 538         .intr = &rk3366_vop_intr,
 539         .ctrl = &rk3288_ctrl_data,
 540         .win = rk3399_vop_lit_win_data,
 541         .win_size = ARRAY_SIZE(rk3399_vop_lit_win_data),
 542 };
 543
 544 static const struct vop_data rk322x_vop = {
 545         .version = VOP_VERSION(3, 7),
 546         .feature = VOP_FEATURE_OUTPUT_10BIT,
 547         .max_input = {4096, 8192},
 548         .max_output = {4096, 2160},
 549         .intr = &rk3366_vop_intr,
 550         .ctrl = &rk3288_ctrl_data,
 551         .win = rk3368_vop_win_data,
 552         .win_size = ARRAY_SIZE(rk3368_vop_win_data),
 553 };
 554
 555 static const struct vop_ctrl rk3328_ctrl_data = {
 556         .standby = VOP_REG(RK3328_SYS_CTRL, 0x1, 22),
 557         .auto_gate_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 23),
 558         .htotal_pw = VOP_REG(RK3328_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 559         .hact_st_end = VOP_REG(RK3328_DSP_HACT_ST_END, 0x1fff1fff, 0),
 560         .vtotal_pw = VOP_REG(RK3328_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 561         .vact_st_end = VOP_REG(RK3328_DSP_VACT_ST_END, 0x1fff1fff, 0),
 562         .vact_st_end_f1 = VOP_REG(RK3328_DSP_VACT_ST_END_F1, 0x1fff1fff, 0),
 563         .vs_st_end_f1 = VOP_REG(RK3328_DSP_VS_ST_END_F1, 0x1fff1fff, 0),
 564         .hpost_st_end = VOP_REG(RK3328_POST_DSP_HACT_INFO, 0x1fff1fff, 0),
 565         .vpost_st_end = VOP_REG(RK3328_POST_DSP_VACT_INFO, 0x1fff1fff, 0),
 566         .vpost_st_end_f1 = VOP_REG(RK3328_POST_DSP_VACT_INFO_F1, 0x1fff1fff, 0),
 567         .dsp_interlace = VOP_REG(RK3328_DSP_CTRL0, 0x1, 10),
 568         .dsp_layer_sel = VOP_REG(RK3328_DSP_CTRL1, 0xff, 8),
 569         .post_lb_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 18),
 570         .global_regdone_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 11),
 571         .overlay_mode = VOP_REG(RK3328_SYS_CTRL, 0x1, 16),
 572         .core_dclk_div = VOP_REG(RK3328_DSP_CTRL0, 0x1, 4),
 573         .p2i_en = VOP_REG(RK3328_DSP_CTRL0, 0x1, 5),
 574         .rgb_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 12),
 575         .hdmi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 13),
 576         .edp_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 14),
 577         .mipi_en = VOP_REG(RK3328_SYS_CTRL, 0x1, 15),
 578         .rgb_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 16),
 579         .hdmi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 20),
 580         .edp_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 24),
 581         .mipi_pin_pol = VOP_REG(RK3328_DSP_CTRL1, 0xf, 28),
 582
 583         .dither_down = VOP_REG(RK3328_DSP_CTRL1, 0xf, 1),
 584         .dither_up = VOP_REG(RK3328_DSP_CTRL1, 0x1, 6),
 585
 586         .dsp_data_swap = VOP_REG(RK3328_DSP_CTRL0, 0x1f, 12),
 587         .dsp_ccir656_avg = VOP_REG(RK3328_DSP_CTRL0, 0x1, 20),
 588         .dsp_blank = VOP_REG(RK3328_DSP_CTRL0, 0x3, 18),
 589         .dsp_lut_en = VOP_REG(RK3328_DSP_CTRL1, 0x1, 0),
 590         .out_mode = VOP_REG(RK3328_DSP_CTRL0, 0xf, 0),
 591
 592         .xmirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 22),
 593         .ymirror = VOP_REG(RK3328_DSP_CTRL0, 0x1, 23),
 594
 595         .dsp_background = VOP_REG(RK3328_DSP_BG, 0xffffffff, 0),
 596
 597         .cfg_done = VOP_REG(RK3328_REG_CFG_DONE, 0x1, 0),
 598 };
 599
 600 static const struct vop_intr rk3328_vop_intr = {
 601         .intrs = rk3368_vop_intrs,
 602         .nintrs = ARRAY_SIZE(rk3368_vop_intrs),
 603         .line_flag_num[0] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 0),
 604         .line_flag_num[1] = VOP_REG(RK3328_LINE_FLAG, 0xffff, 16),
 605         .status = VOP_REG_MASK(RK3328_INTR_STATUS0, 0xffff, 0),
 606         .enable = VOP_REG_MASK(RK3328_INTR_EN0, 0xffff, 0),
 607         .clear = VOP_REG_MASK(RK3328_INTR_CLEAR0, 0xffff, 0),
 608 };
 609
 610 static const struct vop_win_data rk3328_vop_win_data[] = {
 611         { .base = 0xd0, .phy = &rk3288_win01_data,
 612           .type = DRM_PLANE_TYPE_PRIMARY },
 613         { .base = 0x1d0, .phy = &rk3288_win01_data,
 614           .type = DRM_PLANE_TYPE_OVERLAY },
 615         { .base = 0x2d0, .phy = &rk3288_win01_data,
 616           .type = DRM_PLANE_TYPE_OVERLAY },
 617         { .base = 0x3d0, .phy = &rk3288_win01_data,
 618           .type = DRM_PLANE_TYPE_CURSOR },
 619 };
 620
 621 static const struct vop_data rk3328_vop = {
 622         .version = VOP_VERSION(3, 8),
 623         .feature = VOP_FEATURE_OUTPUT_10BIT,
 624         .max_input = {4096, 8192},
 625         .max_output = {4096, 2160},
 626         .intr = &rk3328_vop_intr,
 627         .ctrl = &rk3328_ctrl_data,
 628         .win = rk3328_vop_win_data,
 629         .win_size = ARRAY_SIZE(rk3328_vop_win_data),
 630 };
 631
 632 static const struct vop_scl_regs rk3066_win_scl = {
 633         .scale_yrgb_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 0x0),
 634         .scale_yrgb_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_YRGB, 0xffff, 16),
 635         .scale_cbcr_x = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 0x0),
 636         .scale_cbcr_y = VOP_REG(RK3036_WIN0_SCL_FACTOR_CBR, 0xffff, 16),
 637 };
 638
 639 static const struct vop_win_phy rk3036_win0_data = {
 640         .scl = &rk3066_win_scl,
 641         .data_formats = formats_win_full,
 642         .nformats = ARRAY_SIZE(formats_win_full),
 643         .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 0),
 644         .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 3),
 645         .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 15),
 646         .act_info = VOP_REG(RK3036_WIN0_ACT_INFO, 0x1fff1fff, 0),
 647         .dsp_info = VOP_REG(RK3036_WIN0_DSP_INFO, 0x0fff0fff, 0),
 648         .dsp_st = VOP_REG(RK3036_WIN0_DSP_ST, 0x1fff1fff, 0),
 649         .yrgb_mst = VOP_REG(RK3036_WIN0_YRGB_MST, 0xffffffff, 0),
 650         .uv_mst = VOP_REG(RK3036_WIN0_CBR_MST, 0xffffffff, 0),
 651         .yrgb_vir = VOP_REG(RK3036_WIN0_VIR, 0xffff, 0),
 652         .uv_vir = VOP_REG(RK3036_WIN0_VIR, 0x1fff, 16),
 653         .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 18),
 654         .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 0)
 655 };
 656
 657 static const struct vop_win_phy rk3036_win1_data = {
 658         .data_formats = formats_win_lite,
 659         .nformats = ARRAY_SIZE(formats_win_lite),
 660         .enable = VOP_REG(RK3036_SYS_CTRL, 0x1, 1),
 661         .format = VOP_REG(RK3036_SYS_CTRL, 0x7, 6),
 662         .rb_swap = VOP_REG(RK3036_SYS_CTRL, 0x1, 19),
 663         .act_info = VOP_REG(RK3036_WIN1_ACT_INFO, 0x1fff1fff, 0),
 664         .dsp_info = VOP_REG(RK3036_WIN1_DSP_INFO, 0x0fff0fff, 0),
 665         .dsp_st = VOP_REG(RK3036_WIN1_DSP_ST, 0x1fff1fff, 0),
 666         .yrgb_mst = VOP_REG(RK3036_WIN1_MST, 0xffffffff, 0),
 667         .yrgb_vir = VOP_REG(RK3036_WIN1_VIR, 0xffff, 0),
 668         .alpha_mode = VOP_REG(RK3036_DSP_CTRL0, 0x1, 19),
 669         .alpha_en = VOP_REG(RK3036_ALPHA_CTRL, 0x1, 1)
 670 };
 671
 672 static const struct vop_win_data rk3036_vop_win_data[] = {
 673         { .base = 0x00, .phy = &rk3036_win0_data,
 674           .type = DRM_PLANE_TYPE_PRIMARY },
 675         { .base = 0x00, .phy = &rk3036_win1_data,
 676           .type = DRM_PLANE_TYPE_CURSOR },
 677 };
 678
 679 static const int rk3036_vop_intrs[] = {
 680         DSP_HOLD_VALID_INTR,
 681         FS_INTR,
 682         LINE_FLAG_INTR,
 683         BUS_ERROR_INTR,
 684 };
 685
 686 static const struct vop_intr rk3036_intr = {
 687         .intrs = rk3036_vop_intrs,
 688         .nintrs = ARRAY_SIZE(rk3036_vop_intrs),
 689         .line_flag_num[0] = VOP_REG(RK3036_INT_STATUS, 0xfff, 12),
 690         .status = VOP_REG(RK3036_INT_STATUS, 0xf, 0),
 691         .enable = VOP_REG(RK3036_INT_STATUS, 0xf, 4),
 692         .clear = VOP_REG(RK3036_INT_STATUS, 0xf, 8),
 693 };
 694
 695 static const struct vop_ctrl rk3036_ctrl_data = {
 696         .standby = VOP_REG(RK3036_SYS_CTRL, 0x1, 30),
 697         .out_mode = VOP_REG(RK3036_DSP_CTRL0, 0xf, 0),
 698         .dsp_blank = VOP_REG(RK3036_DSP_CTRL1, 0x1, 24),
 699         .pin_pol = VOP_REG(RK3036_DSP_CTRL0, 0xf, 4),
 700         .dsp_layer_sel = VOP_REG(RK3036_DSP_CTRL0, 0x1, 8),
 701         .htotal_pw = VOP_REG(RK3036_DSP_HTOTAL_HS_END, 0x1fff1fff, 0),
 702         .hact_st_end = VOP_REG(RK3036_DSP_HACT_ST_END, 0x1fff1fff, 0),
 703         .vtotal_pw = VOP_REG(RK3036_DSP_VTOTAL_VS_END, 0x1fff1fff, 0),
 704         .vact_st_end = VOP_REG(RK3036_DSP_VACT_ST_END, 0x1fff1fff, 0),
 705         .cfg_done = VOP_REG(RK3036_REG_CFG_DONE, 0x1, 0),
 706 };
 707
 708 static const struct vop_data rk3036_vop = {
 709         .version = VOP_VERSION(2, 2),
 710         .max_input = {1920, 1080},
 711         .max_output = {1920, 1080},
 712         .ctrl = &rk3036_ctrl_data,
 713         .intr = &rk3036_intr,
 714         .win = rk3036_vop_win_data,
 715         .win_size = ARRAY_SIZE(rk3036_vop_win_data),
 716 };
 717
 718 static const struct of_device_id vop_driver_dt_match[] = {
 719         { .compatible = "rockchip,rk3036-vop",
 720           .data = &rk3036_vop },
 721         { .compatible = "rockchip,rk3288-vop",
 722           .data = &rk3288_vop },
 723         { .compatible = "rockchip,rk3368-vop",
 724           .data = &rk3368_vop },
 725         { .compatible = "rockchip,rk3366-vop",
 726           .data = &rk3366_vop },
 727         { .compatible = "rockchip,rk3399-vop-big",
 728           .data = &rk3399_vop_big },
 729         { .compatible = "rockchip,rk3399-vop-lit",
 730           .data = &rk3399_vop_lit },
 731         { .compatible = "rockchip,rk322x-vop",
 732           .data = &rk322x_vop },
 733         { .compatible = "rockchip,rk3328-vop",
 734           .data = &rk3328_vop },
 735         {},
 736 };
 737 MODULE_DEVICE_TABLE(of, vop_driver_dt_match);
 738
 739 static int vop_probe(struct platform_device *pdev)
 740 {
 741         struct device *dev = &pdev->dev;
 742
 743         if (!dev->of_node) {
 744                 dev_err(dev, "can't find vop devices\n");
 745                 return -ENODEV;
 746         }
 747
 748         return component_add(dev, &vop_component_ops);
 749 }
 750
 751 static int vop_remove(struct platform_device *pdev)
 752 {
 753         component_del(&pdev->dev, &vop_component_ops);
 754
 755         return 0;
 756 }
 757
 758 struct platform_driver vop_platform_driver = {
 759         .probe = vop_probe,
 760         .remove = vop_remove,
 761         .driver = {
 762                 .name = "rockchip-vop",
 763                 .owner = THIS_MODULE,
 764                 .of_match_table = of_match_ptr(vop_driver_dt_match),
 765         },
 766 };
 767
 768 module_platform_driver(vop_platform_driver);
 769
 770 MODULE_AUTHOR("Mark Yao <mark.yao@rock-chips.com>");
 771 MODULE_DESCRIPTION("ROCKCHIP VOP Driver");
 772 MODULE_LICENSE("GPL v2");