2 * Copyright (C) STMicroelectronics SA 2014
3 * Authors: Benjamin Gaignard <benjamin.gaignard@st.com>
4 * Fabien Dessenne <fabien.dessenne@st.com>
5 * for STMicroelectronics.
6 * License terms: GNU General Public License (GPL), version 2
9 #include "sti_compositor.h"
10 #include "sti_mixer.h"
13 /* Identity: G=Y , B=Cb , R=Cr */
14 static const u32 mixerColorSpaceMatIdentity[] = {
15 0x10000000, 0x00000000, 0x10000000, 0x00001000,
16 0x00000000, 0x00000000, 0x00000000, 0x00000000
20 #define GAM_MIXER_CTL 0x00
21 #define GAM_MIXER_BKC 0x04
22 #define GAM_MIXER_BCO 0x0C
23 #define GAM_MIXER_BCS 0x10
24 #define GAM_MIXER_AVO 0x28
25 #define GAM_MIXER_AVS 0x2C
26 #define GAM_MIXER_CRB 0x34
27 #define GAM_MIXER_ACT 0x38
28 #define GAM_MIXER_MBP 0x3C
29 #define GAM_MIXER_MX0 0x80
31 /* id for depth of CRB reg */
32 #define GAM_DEPTH_VID0_ID 1
33 #define GAM_DEPTH_VID1_ID 2
34 #define GAM_DEPTH_GDP0_ID 3
35 #define GAM_DEPTH_GDP1_ID 4
36 #define GAM_DEPTH_GDP2_ID 5
37 #define GAM_DEPTH_GDP3_ID 6
38 #define GAM_DEPTH_MASK_ID 7
41 #define GAM_CTL_BACK_MASK BIT(0)
42 #define GAM_CTL_VID0_MASK BIT(1)
43 #define GAM_CTL_VID1_MASK BIT(2)
44 #define GAM_CTL_GDP0_MASK BIT(3)
45 #define GAM_CTL_GDP1_MASK BIT(4)
46 #define GAM_CTL_GDP2_MASK BIT(5)
47 #define GAM_CTL_GDP3_MASK BIT(6)
49 const char *sti_mixer_to_str(struct sti_mixer *mixer)
57 return "<UNKNOWN MIXER>";
61 static inline u32 sti_mixer_reg_read(struct sti_mixer *mixer, u32 reg_id)
63 return readl(mixer->regs + reg_id);
66 static inline void sti_mixer_reg_write(struct sti_mixer *mixer,
69 writel(val, mixer->regs + reg_id);
72 void sti_mixer_set_background_status(struct sti_mixer *mixer, bool enable)
74 u32 val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL);
76 val &= ~GAM_CTL_BACK_MASK;
78 sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
81 static void sti_mixer_set_background_color(struct sti_mixer *mixer,
82 u8 red, u8 green, u8 blue)
84 u32 val = (red << 16) | (green << 8) | blue;
86 sti_mixer_reg_write(mixer, GAM_MIXER_BKC, val);
89 static void sti_mixer_set_background_area(struct sti_mixer *mixer,
90 struct drm_display_mode *mode)
92 u32 ydo, xdo, yds, xds;
94 ydo = sti_vtg_get_line_number(*mode, 0);
95 yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
96 xdo = sti_vtg_get_pixel_number(*mode, 0);
97 xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
99 sti_mixer_reg_write(mixer, GAM_MIXER_BCO, ydo << 16 | xdo);
100 sti_mixer_reg_write(mixer, GAM_MIXER_BCS, yds << 16 | xds);
103 int sti_mixer_set_layer_depth(struct sti_mixer *mixer, struct sti_layer *layer)
105 int layer_id = 0, depth = layer->zorder;
108 if (depth >= GAM_MIXER_NB_DEPTH_LEVEL)
111 switch (layer->desc) {
113 layer_id = GAM_DEPTH_GDP0_ID;
116 layer_id = GAM_DEPTH_GDP1_ID;
119 layer_id = GAM_DEPTH_GDP2_ID;
122 layer_id = GAM_DEPTH_GDP3_ID;
125 layer_id = GAM_DEPTH_VID0_ID;
128 layer_id = GAM_DEPTH_VID1_ID;
131 DRM_ERROR("Unknown layer %d\n", layer->desc);
134 mask = GAM_DEPTH_MASK_ID << (3 * depth);
135 layer_id = layer_id << (3 * depth);
137 DRM_DEBUG_DRIVER("%s %s depth=%d\n", sti_mixer_to_str(mixer),
138 sti_layer_to_str(layer), depth);
139 dev_dbg(mixer->dev, "GAM_MIXER_CRB val 0x%x mask 0x%x\n",
142 val = sti_mixer_reg_read(mixer, GAM_MIXER_CRB);
145 sti_mixer_reg_write(mixer, GAM_MIXER_CRB, val);
147 dev_dbg(mixer->dev, "Read GAM_MIXER_CRB 0x%x\n",
148 sti_mixer_reg_read(mixer, GAM_MIXER_CRB));
152 int sti_mixer_active_video_area(struct sti_mixer *mixer,
153 struct drm_display_mode *mode)
155 u32 ydo, xdo, yds, xds;
157 ydo = sti_vtg_get_line_number(*mode, 0);
158 yds = sti_vtg_get_line_number(*mode, mode->vdisplay - 1);
159 xdo = sti_vtg_get_pixel_number(*mode, 0);
160 xds = sti_vtg_get_pixel_number(*mode, mode->hdisplay - 1);
162 DRM_DEBUG_DRIVER("%s active video area xdo:%d ydo:%d xds:%d yds:%d\n",
163 sti_mixer_to_str(mixer), xdo, ydo, xds, yds);
164 sti_mixer_reg_write(mixer, GAM_MIXER_AVO, ydo << 16 | xdo);
165 sti_mixer_reg_write(mixer, GAM_MIXER_AVS, yds << 16 | xds);
167 sti_mixer_set_background_color(mixer, 0xFF, 0, 0);
169 sti_mixer_set_background_area(mixer, mode);
170 sti_mixer_set_background_status(mixer, true);
174 static u32 sti_mixer_get_layer_mask(struct sti_layer *layer)
176 switch (layer->desc) {
178 return GAM_CTL_BACK_MASK;
180 return GAM_CTL_GDP0_MASK;
182 return GAM_CTL_GDP1_MASK;
184 return GAM_CTL_GDP2_MASK;
186 return GAM_CTL_GDP3_MASK;
188 return GAM_CTL_VID0_MASK;
190 return GAM_CTL_VID1_MASK;
196 int sti_mixer_set_layer_status(struct sti_mixer *mixer,
197 struct sti_layer *layer, bool status)
201 DRM_DEBUG_DRIVER("%s %s %s\n", status ? "enable" : "disable",
202 sti_mixer_to_str(mixer), sti_layer_to_str(layer));
204 mask = sti_mixer_get_layer_mask(layer);
206 DRM_ERROR("Can not find layer mask\n");
210 val = sti_mixer_reg_read(mixer, GAM_MIXER_CTL);
212 val |= status ? mask : 0;
213 sti_mixer_reg_write(mixer, GAM_MIXER_CTL, val);
218 void sti_mixer_set_matrix(struct sti_mixer *mixer)
222 for (i = 0; i < ARRAY_SIZE(mixerColorSpaceMatIdentity); i++)
223 sti_mixer_reg_write(mixer, GAM_MIXER_MX0 + (i * 4),
224 mixerColorSpaceMatIdentity[i]);
227 struct sti_mixer *sti_mixer_create(struct device *dev, int id,
228 void __iomem *baseaddr)
230 struct sti_mixer *mixer = devm_kzalloc(dev, sizeof(*mixer), GFP_KERNEL);
231 struct device_node *np = dev->of_node;
233 dev_dbg(dev, "%s\n", __func__);
235 DRM_ERROR("Failed to allocated memory for mixer\n");
238 mixer->regs = baseaddr;
242 if (of_device_is_compatible(np, "st,stih416-compositor"))
243 sti_mixer_set_matrix(mixer);
245 DRM_DEBUG_DRIVER("%s created. Regs=%p\n",
246 sti_mixer_to_str(mixer), mixer->regs);