drivers/gpu/drm/tegra/dc.c

   1 /*
   2  * Copyright (C) 2012 Avionic Design GmbH
   3  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/debugfs.h>
  12 #include <linux/reset.h>
  13
  14 #include "dc.h"
  15 #include "drm.h"
  16 #include "gem.h"
  17
  18 #include <drm/drm_plane_helper.h>
  19
  20 struct tegra_dc_soc_info {
  21         bool supports_interlacing;
  22         bool supports_cursor;
  23         bool supports_block_linear;
  24         unsigned int pitch_align;
  25 };
  26
  27 struct tegra_plane {
  28         struct drm_plane base;
  29         unsigned int index;
  30 };
  31
  32 static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
  33 {
  34         return container_of(plane, struct tegra_plane, base);
  35 }
  36
  37 static unsigned int tegra_dc_format(uint32_t format, uint32_t *swap)
  38 {
  39         /* assume no swapping of fetched data */
  40         if (swap)
  41                 *swap = BYTE_SWAP_NOSWAP;
  42
  43         switch (format) {
  44         case DRM_FORMAT_XBGR8888:
  45                 return WIN_COLOR_DEPTH_R8G8B8A8;
  46
  47         case DRM_FORMAT_XRGB8888:
  48                 return WIN_COLOR_DEPTH_B8G8R8A8;
  49
  50         case DRM_FORMAT_RGB565:
  51                 return WIN_COLOR_DEPTH_B5G6R5;
  52
  53         case DRM_FORMAT_UYVY:
  54                 return WIN_COLOR_DEPTH_YCbCr422;
  55
  56         case DRM_FORMAT_YUYV:
  57                 if (swap)
  58                         *swap = BYTE_SWAP_SWAP2;
  59
  60                 return WIN_COLOR_DEPTH_YCbCr422;
  61
  62         case DRM_FORMAT_YUV420:
  63                 return WIN_COLOR_DEPTH_YCbCr420P;
  64
  65         case DRM_FORMAT_YUV422:
  66                 return WIN_COLOR_DEPTH_YCbCr422P;
  67
  68         default:
  69                 break;
  70         }
  71
  72         WARN(1, "unsupported pixel format %u, using default\n", format);
  73         return WIN_COLOR_DEPTH_B8G8R8A8;
  74 }
  75
  76 static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
  77 {
  78         switch (format) {
  79         case WIN_COLOR_DEPTH_YCbCr422:
  80         case WIN_COLOR_DEPTH_YUV422:
  81                 if (planar)
  82                         *planar = false;
  83
  84                 return true;
  85
  86         case WIN_COLOR_DEPTH_YCbCr420P:
  87         case WIN_COLOR_DEPTH_YUV420P:
  88         case WIN_COLOR_DEPTH_YCbCr422P:
  89         case WIN_COLOR_DEPTH_YUV422P:
  90         case WIN_COLOR_DEPTH_YCbCr422R:
  91         case WIN_COLOR_DEPTH_YUV422R:
  92         case WIN_COLOR_DEPTH_YCbCr422RA:
  93         case WIN_COLOR_DEPTH_YUV422RA:
  94                 if (planar)
  95                         *planar = true;
  96
  97                 return true;
  98         }
  99
 100         return false;
 101 }
 102
 103 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
 104                                   unsigned int bpp)
 105 {
 106         fixed20_12 outf = dfixed_init(out);
 107         fixed20_12 inf = dfixed_init(in);
 108         u32 dda_inc;
 109         int max;
 110
 111         if (v)
 112                 max = 15;
 113         else {
 114                 switch (bpp) {
 115                 case 2:
 116                         max = 8;
 117                         break;
 118
 119                 default:
 120                         WARN_ON_ONCE(1);
 121                         /* fallthrough */
 122                 case 4:
 123                         max = 4;
 124                         break;
 125                 }
 126         }
 127
 128         outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
 129         inf.full -= dfixed_const(1);
 130
 131         dda_inc = dfixed_div(inf, outf);
 132         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
 133
 134         return dda_inc;
 135 }
 136
 137 static inline u32 compute_initial_dda(unsigned int in)
 138 {
 139         fixed20_12 inf = dfixed_init(in);
 140         return dfixed_frac(inf);
 141 }
 142
 143 static int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
 144                                  const struct tegra_dc_window *window)
 145 {
 146         unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
 147         unsigned long value;
 148         bool yuv, planar;
 149
 150         /*
 151          * For YUV planar modes, the number of bytes per pixel takes into
 152          * account only the luma component and therefore is 1.
 153          */
 154         yuv = tegra_dc_format_is_yuv(window->format, &planar);
 155         if (!yuv)
 156                 bpp = window->bits_per_pixel / 8;
 157         else
 158                 bpp = planar ? 1 : 2;
 159
 160         value = WINDOW_A_SELECT << index;
 161         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
 162
 163         tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
 164         tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
 165
 166         value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
 167         tegra_dc_writel(dc, value, DC_WIN_POSITION);
 168
 169         value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
 170         tegra_dc_writel(dc, value, DC_WIN_SIZE);
 171
 172         h_offset = window->src.x * bpp;
 173         v_offset = window->src.y;
 174         h_size = window->src.w * bpp;
 175         v_size = window->src.h;
 176
 177         value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
 178         tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
 179
 180         /*
 181          * For DDA computations the number of bytes per pixel for YUV planar
 182          * modes needs to take into account all Y, U and V components.
 183          */
 184         if (yuv && planar)
 185                 bpp = 2;
 186
 187         h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
 188         v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
 189
 190         value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
 191         tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
 192
 193         h_dda = compute_initial_dda(window->src.x);
 194         v_dda = compute_initial_dda(window->src.y);
 195
 196         tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
 197         tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
 198
 199         tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
 200         tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
 201
 202         tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
 203
 204         if (yuv && planar) {
 205                 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
 206                 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
 207                 value = window->stride[1] << 16 | window->stride[0];
 208                 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
 209         } else {
 210                 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
 211         }
 212
 213         if (window->bottom_up)
 214                 v_offset += window->src.h - 1;
 215
 216         tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
 217         tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
 218
 219         if (dc->soc->supports_block_linear) {
 220                 unsigned long height = window->tiling.value;
 221
 222                 switch (window->tiling.mode) {
 223                 case TEGRA_BO_TILING_MODE_PITCH:
 224                         value = DC_WINBUF_SURFACE_KIND_PITCH;
 225                         break;
 226
 227                 case TEGRA_BO_TILING_MODE_TILED:
 228                         value = DC_WINBUF_SURFACE_KIND_TILED;
 229                         break;
 230
 231                 case TEGRA_BO_TILING_MODE_BLOCK:
 232                         value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
 233                                 DC_WINBUF_SURFACE_KIND_BLOCK;
 234                         break;
 235                 }
 236
 237                 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
 238         } else {
 239                 switch (window->tiling.mode) {
 240                 case TEGRA_BO_TILING_MODE_PITCH:
 241                         value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
 242                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
 243                         break;
 244
 245                 case TEGRA_BO_TILING_MODE_TILED:
 246                         value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
 247                                 DC_WIN_BUFFER_ADDR_MODE_TILE;
 248                         break;
 249
 250                 case TEGRA_BO_TILING_MODE_BLOCK:
 251                         DRM_ERROR("hardware doesn't support block linear mode\n");
 252                         return -EINVAL;
 253                 }
 254
 255                 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
 256         }
 257
 258         value = WIN_ENABLE;
 259
 260         if (yuv) {
 261                 /* setup default colorspace conversion coefficients */
 262                 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
 263                 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
 264                 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
 265                 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
 266                 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
 267                 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
 268                 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
 269                 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
 270
 271                 value |= CSC_ENABLE;
 272         } else if (window->bits_per_pixel < 24) {
 273                 value |= COLOR_EXPAND;
 274         }
 275
 276         if (window->bottom_up)
 277                 value |= V_DIRECTION;
 278
 279         tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
 280
 281         /*
 282          * Disable blending and assume Window A is the bottom-most window,
 283          * Window C is the top-most window and Window B is in the middle.
 284          */
 285         tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
 286         tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
 287
 288         switch (index) {
 289         case 0:
 290                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
 291                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
 292                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
 293                 break;
 294
 295         case 1:
 296                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
 297                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
 298                 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
 299                 break;
 300
 301         case 2:
 302                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
 303                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
 304                 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
 305                 break;
 306         }
 307
 308         tegra_dc_writel(dc, WIN_A_UPDATE << index, DC_CMD_STATE_CONTROL);
 309         tegra_dc_writel(dc, WIN_A_ACT_REQ << index, DC_CMD_STATE_CONTROL);
 310
 311         return 0;
 312 }
 313
 314 static int tegra_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
 315                               struct drm_framebuffer *fb, int crtc_x,
 316                               int crtc_y, unsigned int crtc_w,
 317                               unsigned int crtc_h, uint32_t src_x,
 318                               uint32_t src_y, uint32_t src_w, uint32_t src_h)
 319 {
 320         struct tegra_plane *p = to_tegra_plane(plane);
 321         struct tegra_dc *dc = to_tegra_dc(crtc);
 322         struct tegra_dc_window window;
 323         unsigned int i;
 324         int err;
 325
 326         memset(&window, 0, sizeof(window));
 327         window.src.x = src_x >> 16;
 328         window.src.y = src_y >> 16;
 329         window.src.w = src_w >> 16;
 330         window.src.h = src_h >> 16;
 331         window.dst.x = crtc_x;
 332         window.dst.y = crtc_y;
 333         window.dst.w = crtc_w;
 334         window.dst.h = crtc_h;
 335         window.format = tegra_dc_format(fb->pixel_format, &window.swap);
 336         window.bits_per_pixel = fb->bits_per_pixel;
 337         window.bottom_up = tegra_fb_is_bottom_up(fb);
 338
 339         err = tegra_fb_get_tiling(fb, &window.tiling);
 340         if (err < 0)
 341                 return err;
 342
 343         for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
 344                 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
 345
 346                 window.base[i] = bo->paddr + fb->offsets[i];
 347
 348                 /*
 349                  * Tegra doesn't support different strides for U and V planes
 350                  * so we display a warning if the user tries to display a
 351                  * framebuffer with such a configuration.
 352                  */
 353                 if (i >= 2) {
 354                         if (fb->pitches[i] != window.stride[1])
 355                                 DRM_ERROR("unsupported UV-plane configuration\n");
 356                 } else {
 357                         window.stride[i] = fb->pitches[i];
 358                 }
 359         }
 360
 361         return tegra_dc_setup_window(dc, p->index, &window);
 362 }
 363
 364 static int tegra_plane_disable(struct drm_plane *plane)
 365 {
 366         struct tegra_dc *dc = to_tegra_dc(plane->crtc);
 367         struct tegra_plane *p = to_tegra_plane(plane);
 368         unsigned long value;
 369
 370         if (!plane->crtc)
 371                 return 0;
 372
 373         value = WINDOW_A_SELECT << p->index;
 374         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
 375
 376         value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
 377         value &= ~WIN_ENABLE;
 378         tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
 379
 380         tegra_dc_writel(dc, WIN_A_UPDATE << p->index, DC_CMD_STATE_CONTROL);
 381         tegra_dc_writel(dc, WIN_A_ACT_REQ << p->index, DC_CMD_STATE_CONTROL);
 382
 383         return 0;
 384 }
 385
 386 static void tegra_plane_destroy(struct drm_plane *plane)
 387 {
 388         struct tegra_plane *p = to_tegra_plane(plane);
 389
 390         tegra_plane_disable(plane);
 391         drm_plane_cleanup(plane);
 392         kfree(p);
 393 }
 394
 395 static const struct drm_plane_funcs tegra_plane_funcs = {
 396         .update_plane = tegra_plane_update,
 397         .disable_plane = tegra_plane_disable,
 398         .destroy = tegra_plane_destroy,
 399 };
 400
 401 static const uint32_t plane_formats[] = {
 402         DRM_FORMAT_XBGR8888,
 403         DRM_FORMAT_XRGB8888,
 404         DRM_FORMAT_RGB565,
 405         DRM_FORMAT_UYVY,
 406         DRM_FORMAT_YUYV,
 407         DRM_FORMAT_YUV420,
 408         DRM_FORMAT_YUV422,
 409 };
 410
 411 static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
 412 {
 413         unsigned int i;
 414         int err = 0;
 415
 416         for (i = 0; i < 2; i++) {
 417                 struct tegra_plane *plane;
 418
 419                 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
 420                 if (!plane)
 421                         return -ENOMEM;
 422
 423                 plane->index = 1 + i;
 424
 425                 err = drm_plane_init(drm, &plane->base, 1 << dc->pipe,
 426                                      &tegra_plane_funcs, plane_formats,
 427                                      ARRAY_SIZE(plane_formats), false);
 428                 if (err < 0) {
 429                         kfree(plane);
 430                         return err;
 431                 }
 432         }
 433
 434         return 0;
 435 }
 436
 437 static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
 438                              struct drm_framebuffer *fb)
 439 {
 440         struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
 441         unsigned int h_offset = 0, v_offset = 0;
 442         struct tegra_bo_tiling tiling;
 443         unsigned int format, swap;
 444         unsigned long value;
 445         int err;
 446
 447         err = tegra_fb_get_tiling(fb, &tiling);
 448         if (err < 0)
 449                 return err;
 450
 451         tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
 452
 453         value = fb->offsets[0] + y * fb->pitches[0] +
 454                 x * fb->bits_per_pixel / 8;
 455
 456         tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR);
 457         tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE);
 458
 459         format = tegra_dc_format(fb->pixel_format, &swap);
 460         tegra_dc_writel(dc, format, DC_WIN_COLOR_DEPTH);
 461         tegra_dc_writel(dc, swap, DC_WIN_BYTE_SWAP);
 462
 463         if (dc->soc->supports_block_linear) {
 464                 unsigned long height = tiling.value;
 465
 466                 switch (tiling.mode) {
 467                 case TEGRA_BO_TILING_MODE_PITCH:
 468                         value = DC_WINBUF_SURFACE_KIND_PITCH;
 469                         break;
 470
 471                 case TEGRA_BO_TILING_MODE_TILED:
 472                         value = DC_WINBUF_SURFACE_KIND_TILED;
 473                         break;
 474
 475                 case TEGRA_BO_TILING_MODE_BLOCK:
 476                         value = DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(height) |
 477                                 DC_WINBUF_SURFACE_KIND_BLOCK;
 478                         break;
 479                 }
 480
 481                 tegra_dc_writel(dc, value, DC_WINBUF_SURFACE_KIND);
 482         } else {
 483                 switch (tiling.mode) {
 484                 case TEGRA_BO_TILING_MODE_PITCH:
 485                         value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
 486                                 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
 487                         break;
 488
 489                 case TEGRA_BO_TILING_MODE_TILED:
 490                         value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
 491                                 DC_WIN_BUFFER_ADDR_MODE_TILE;
 492                         break;
 493
 494                 case TEGRA_BO_TILING_MODE_BLOCK:
 495                         DRM_ERROR("hardware doesn't support block linear mode\n");
 496                         return -EINVAL;
 497                 }
 498
 499                 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
 500         }
 501
 502         /* make sure bottom-up buffers are properly displayed */
 503         if (tegra_fb_is_bottom_up(fb)) {
 504                 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
 505                 value |= V_DIRECTION;
 506                 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
 507
 508                 v_offset += fb->height - 1;
 509         } else {
 510                 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
 511                 value &= ~V_DIRECTION;
 512                 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
 513         }
 514
 515         tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
 516         tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
 517
 518         value = GENERAL_UPDATE | WIN_A_UPDATE;
 519         tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
 520
 521         value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
 522         tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
 523
 524         return 0;
 525 }
 526
 527 void tegra_dc_enable_vblank(struct tegra_dc *dc)
 528 {
 529         unsigned long value, flags;
 530
 531         spin_lock_irqsave(&dc->lock, flags);
 532
 533         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
 534         value |= VBLANK_INT;
 535         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
 536
 537         spin_unlock_irqrestore(&dc->lock, flags);
 538 }
 539
 540 void tegra_dc_disable_vblank(struct tegra_dc *dc)
 541 {
 542         unsigned long value, flags;
 543
 544         spin_lock_irqsave(&dc->lock, flags);
 545
 546         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
 547         value &= ~VBLANK_INT;
 548         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
 549
 550         spin_unlock_irqrestore(&dc->lock, flags);
 551 }
 552
 553 static int tegra_dc_cursor_set2(struct drm_crtc *crtc, struct drm_file *file,
 554                                 uint32_t handle, uint32_t width,
 555                                 uint32_t height, int32_t hot_x, int32_t hot_y)
 556 {
 557         unsigned long value = CURSOR_CLIP_DISPLAY;
 558         struct tegra_dc *dc = to_tegra_dc(crtc);
 559         struct drm_gem_object *gem;
 560         struct tegra_bo *bo = NULL;
 561
 562         if (!dc->soc->supports_cursor)
 563                 return -ENXIO;
 564
 565         if (width != height)
 566                 return -EINVAL;
 567
 568         switch (width) {
 569         case 32:
 570                 value |= CURSOR_SIZE_32x32;
 571                 break;
 572
 573         case 64:
 574                 value |= CURSOR_SIZE_64x64;
 575                 break;
 576
 577         case 128:
 578                 value |= CURSOR_SIZE_128x128;
 579
 580         case 256:
 581                 value |= CURSOR_SIZE_256x256;
 582                 break;
 583
 584         default:
 585                 return -EINVAL;
 586         }
 587
 588         if (handle) {
 589                 gem = drm_gem_object_lookup(crtc->dev, file, handle);
 590                 if (!gem)
 591                         return -ENOENT;
 592
 593                 bo = to_tegra_bo(gem);
 594         }
 595
 596         if (bo) {
 597                 unsigned long addr = (bo->paddr & 0xfffffc00) >> 10;
 598 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
 599                 unsigned long high = (bo->paddr & 0xfffffffc) >> 32;
 600 #endif
 601
 602                 tegra_dc_writel(dc, value | addr, DC_DISP_CURSOR_START_ADDR);
 603
 604 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
 605                 tegra_dc_writel(dc, high, DC_DISP_CURSOR_START_ADDR_HI);
 606 #endif
 607
 608                 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
 609                 value |= CURSOR_ENABLE;
 610                 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 611
 612                 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
 613                 value &= ~CURSOR_DST_BLEND_MASK;
 614                 value &= ~CURSOR_SRC_BLEND_MASK;
 615                 value |= CURSOR_MODE_NORMAL;
 616                 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
 617                 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
 618                 value |= CURSOR_ALPHA;
 619                 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
 620         } else {
 621                 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
 622                 value &= ~CURSOR_ENABLE;
 623                 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 624         }
 625
 626         tegra_dc_writel(dc, CURSOR_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
 627         tegra_dc_writel(dc, CURSOR_ACT_REQ, DC_CMD_STATE_CONTROL);
 628
 629         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
 630         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
 631
 632         return 0;
 633 }
 634
 635 static int tegra_dc_cursor_move(struct drm_crtc *crtc, int x, int y)
 636 {
 637         struct tegra_dc *dc = to_tegra_dc(crtc);
 638         unsigned long value;
 639
 640         if (!dc->soc->supports_cursor)
 641                 return -ENXIO;
 642
 643         value = ((y & 0x3fff) << 16) | (x & 0x3fff);
 644         tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
 645
 646         tegra_dc_writel(dc, CURSOR_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
 647         tegra_dc_writel(dc, CURSOR_ACT_REQ, DC_CMD_STATE_CONTROL);
 648
 649         /* XXX: only required on generations earlier than Tegra124? */
 650         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
 651         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
 652
 653         return 0;
 654 }
 655
 656 static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
 657 {
 658         struct drm_device *drm = dc->base.dev;
 659         struct drm_crtc *crtc = &dc->base;
 660         unsigned long flags, base;
 661         struct tegra_bo *bo;
 662
 663         if (!dc->event)
 664                 return;
 665
 666         bo = tegra_fb_get_plane(crtc->primary->fb, 0);
 667
 668         /* check if new start address has been latched */
 669         tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
 670         base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
 671         tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
 672
 673         if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
 674                 spin_lock_irqsave(&drm->event_lock, flags);
 675                 drm_send_vblank_event(drm, dc->pipe, dc->event);
 676                 drm_vblank_put(drm, dc->pipe);
 677                 dc->event = NULL;
 678                 spin_unlock_irqrestore(&drm->event_lock, flags);
 679         }
 680 }
 681
 682 void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
 683 {
 684         struct tegra_dc *dc = to_tegra_dc(crtc);
 685         struct drm_device *drm = crtc->dev;
 686         unsigned long flags;
 687
 688         spin_lock_irqsave(&drm->event_lock, flags);
 689
 690         if (dc->event && dc->event->base.file_priv == file) {
 691                 dc->event->base.destroy(&dc->event->base);
 692                 drm_vblank_put(drm, dc->pipe);
 693                 dc->event = NULL;
 694         }
 695
 696         spin_unlock_irqrestore(&drm->event_lock, flags);
 697 }
 698
 699 static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
 700                               struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
 701 {
 702         struct tegra_dc *dc = to_tegra_dc(crtc);
 703         struct drm_device *drm = crtc->dev;
 704
 705         if (dc->event)
 706                 return -EBUSY;
 707
 708         if (event) {
 709                 event->pipe = dc->pipe;
 710                 dc->event = event;
 711                 drm_vblank_get(drm, dc->pipe);
 712         }
 713
 714         tegra_dc_set_base(dc, 0, 0, fb);
 715         crtc->primary->fb = fb;
 716
 717         return 0;
 718 }
 719
 720 static void drm_crtc_clear(struct drm_crtc *crtc)
 721 {
 722         memset(crtc, 0, sizeof(*crtc));
 723 }
 724
 725 static void tegra_dc_destroy(struct drm_crtc *crtc)
 726 {
 727         drm_crtc_cleanup(crtc);
 728         drm_crtc_clear(crtc);
 729 }
 730
 731 static const struct drm_crtc_funcs tegra_crtc_funcs = {
 732         .cursor_set2 = tegra_dc_cursor_set2,
 733         .cursor_move = tegra_dc_cursor_move,
 734         .page_flip = tegra_dc_page_flip,
 735         .set_config = drm_crtc_helper_set_config,
 736         .destroy = tegra_dc_destroy,
 737 };
 738
 739 static void tegra_crtc_disable(struct drm_crtc *crtc)
 740 {
 741         struct drm_device *drm = crtc->dev;
 742         struct drm_plane *plane;
 743
 744         drm_for_each_legacy_plane(plane, &drm->mode_config.plane_list) {
 745                 if (plane->crtc == crtc) {
 746                         tegra_plane_disable(plane);
 747                         plane->crtc = NULL;
 748
 749                         if (plane->fb) {
 750                                 drm_framebuffer_unreference(plane->fb);
 751                                 plane->fb = NULL;
 752                         }
 753                 }
 754         }
 755
 756         drm_crtc_vblank_off(crtc);
 757 }
 758
 759 static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
 760                                   const struct drm_display_mode *mode,
 761                                   struct drm_display_mode *adjusted)
 762 {
 763         return true;
 764 }
 765
 766 static int tegra_dc_set_timings(struct tegra_dc *dc,
 767                                 struct drm_display_mode *mode)
 768 {
 769         unsigned int h_ref_to_sync = 1;
 770         unsigned int v_ref_to_sync = 1;
 771         unsigned long value;
 772
 773         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
 774
 775         value = (v_ref_to_sync << 16) | h_ref_to_sync;
 776         tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
 777
 778         value = ((mode->vsync_end - mode->vsync_start) << 16) |
 779                 ((mode->hsync_end - mode->hsync_start) <<  0);
 780         tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
 781
 782         value = ((mode->vtotal - mode->vsync_end) << 16) |
 783                 ((mode->htotal - mode->hsync_end) <<  0);
 784         tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
 785
 786         value = ((mode->vsync_start - mode->vdisplay) << 16) |
 787                 ((mode->hsync_start - mode->hdisplay) <<  0);
 788         tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
 789
 790         value = (mode->vdisplay << 16) | mode->hdisplay;
 791         tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
 792
 793         return 0;
 794 }
 795
 796 static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
 797                                 struct drm_display_mode *mode)
 798 {
 799         unsigned long pclk = mode->clock * 1000;
 800         struct tegra_dc *dc = to_tegra_dc(crtc);
 801         struct tegra_output *output = NULL;
 802         struct drm_encoder *encoder;
 803         unsigned int div;
 804         u32 value;
 805         long err;
 806
 807         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head)
 808                 if (encoder->crtc == crtc) {
 809                         output = encoder_to_output(encoder);
 810                         break;
 811                 }
 812
 813         if (!output)
 814                 return -ENODEV;
 815
 816         /*
 817          * This assumes that the parent clock is pll_d_out0 or pll_d2_out
 818          * respectively, each of which divides the base pll_d by 2.
 819          */
 820         err = tegra_output_setup_clock(output, dc->clk, pclk, &div);
 821         if (err < 0) {
 822                 dev_err(dc->dev, "failed to setup clock: %ld\n", err);
 823                 return err;
 824         }
 825
 826         DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), div);
 827
 828         value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
 829         tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
 830
 831         return 0;
 832 }
 833
 834 static int tegra_crtc_mode_set(struct drm_crtc *crtc,
 835                                struct drm_display_mode *mode,
 836                                struct drm_display_mode *adjusted,
 837                                int x, int y, struct drm_framebuffer *old_fb)
 838 {
 839         struct tegra_bo *bo = tegra_fb_get_plane(crtc->primary->fb, 0);
 840         struct tegra_dc *dc = to_tegra_dc(crtc);
 841         struct tegra_dc_window window;
 842         u32 value;
 843         int err;
 844
 845         err = tegra_crtc_setup_clk(crtc, mode);
 846         if (err) {
 847                 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err);
 848                 return err;
 849         }
 850
 851         /* program display mode */
 852         tegra_dc_set_timings(dc, mode);
 853
 854         /* interlacing isn't supported yet, so disable it */
 855         if (dc->soc->supports_interlacing) {
 856                 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
 857                 value &= ~INTERLACE_ENABLE;
 858                 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
 859         }
 860
 861         /* setup window parameters */
 862         memset(&window, 0, sizeof(window));
 863         window.src.x = 0;
 864         window.src.y = 0;
 865         window.src.w = mode->hdisplay;
 866         window.src.h = mode->vdisplay;
 867         window.dst.x = 0;
 868         window.dst.y = 0;
 869         window.dst.w = mode->hdisplay;
 870         window.dst.h = mode->vdisplay;
 871         window.format = tegra_dc_format(crtc->primary->fb->pixel_format,
 872                                         &window.swap);
 873         window.bits_per_pixel = crtc->primary->fb->bits_per_pixel;
 874         window.stride[0] = crtc->primary->fb->pitches[0];
 875         window.base[0] = bo->paddr;
 876
 877         err = tegra_dc_setup_window(dc, 0, &window);
 878         if (err < 0)
 879                 dev_err(dc->dev, "failed to enable root plane\n");
 880
 881         return 0;
 882 }
 883
 884 static int tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 885                                     struct drm_framebuffer *old_fb)
 886 {
 887         struct tegra_dc *dc = to_tegra_dc(crtc);
 888
 889         return tegra_dc_set_base(dc, x, y, crtc->primary->fb);
 890 }
 891
 892 static void tegra_crtc_prepare(struct drm_crtc *crtc)
 893 {
 894         struct tegra_dc *dc = to_tegra_dc(crtc);
 895         unsigned int syncpt;
 896         unsigned long value;
 897
 898         drm_crtc_vblank_off(crtc);
 899
 900         /* hardware initialization */
 901         reset_control_deassert(dc->rst);
 902         usleep_range(10000, 20000);
 903
 904         if (dc->pipe)
 905                 syncpt = SYNCPT_VBLANK1;
 906         else
 907                 syncpt = SYNCPT_VBLANK0;
 908
 909         /* initialize display controller */
 910         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
 911         tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
 912
 913         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
 914         tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
 915
 916         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
 917                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
 918         tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
 919
 920         /* initialize timer */
 921         value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
 922                 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
 923         tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
 924
 925         value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
 926                 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
 927         tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
 928
 929         value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
 930         tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
 931
 932         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
 933         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
 934 }
 935
 936 static void tegra_crtc_commit(struct drm_crtc *crtc)
 937 {
 938         struct tegra_dc *dc = to_tegra_dc(crtc);
 939         unsigned long value;
 940
 941         value = GENERAL_UPDATE | WIN_A_UPDATE;
 942         tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
 943
 944         value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
 945         tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
 946
 947         drm_crtc_vblank_on(crtc);
 948 }
 949
 950 static void tegra_crtc_load_lut(struct drm_crtc *crtc)
 951 {
 952 }
 953
 954 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
 955         .disable = tegra_crtc_disable,
 956         .mode_fixup = tegra_crtc_mode_fixup,
 957         .mode_set = tegra_crtc_mode_set,
 958         .mode_set_base = tegra_crtc_mode_set_base,
 959         .prepare = tegra_crtc_prepare,
 960         .commit = tegra_crtc_commit,
 961         .load_lut = tegra_crtc_load_lut,
 962 };
 963
 964 static irqreturn_t tegra_dc_irq(int irq, void *data)
 965 {
 966         struct tegra_dc *dc = data;
 967         unsigned long status;
 968
 969         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
 970         tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
 971
 972         if (status & FRAME_END_INT) {
 973                 /*
 974                 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
 975                 */
 976         }
 977
 978         if (status & VBLANK_INT) {
 979                 /*
 980                 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
 981                 */
 982                 drm_handle_vblank(dc->base.dev, dc->pipe);
 983                 tegra_dc_finish_page_flip(dc);
 984         }
 985
 986         if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
 987                 /*
 988                 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
 989                 */
 990         }
 991
 992         return IRQ_HANDLED;
 993 }
 994
 995 static int tegra_dc_show_regs(struct seq_file *s, void *data)
 996 {
 997         struct drm_info_node *node = s->private;
 998         struct tegra_dc *dc = node->info_ent->data;
 999
1000 #define DUMP_REG(name)                                          \
1001         seq_printf(s, "%-40s %#05x %08lx\n", #name, name,       \
1002                    tegra_dc_readl(dc, name))
1003
1004         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
1005         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
1006         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
1007         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
1008         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
1009         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
1010         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
1011         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
1012         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
1013         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
1014         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
1015         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
1016         DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
1017         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
1018         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
1019         DUMP_REG(DC_CMD_SIGNAL_RAISE);
1020         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
1021         DUMP_REG(DC_CMD_INT_STATUS);
1022         DUMP_REG(DC_CMD_INT_MASK);
1023         DUMP_REG(DC_CMD_INT_ENABLE);
1024         DUMP_REG(DC_CMD_INT_TYPE);
1025         DUMP_REG(DC_CMD_INT_POLARITY);
1026         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
1027         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
1028         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
1029         DUMP_REG(DC_CMD_STATE_ACCESS);
1030         DUMP_REG(DC_CMD_STATE_CONTROL);
1031         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
1032         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
1033         DUMP_REG(DC_COM_CRC_CONTROL);
1034         DUMP_REG(DC_COM_CRC_CHECKSUM);
1035         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
1036         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
1037         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
1038         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
1039         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
1040         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
1041         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
1042         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
1043         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
1044         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
1045         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
1046         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
1047         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
1048         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
1049         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
1050         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
1051         DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
1052         DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
1053         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
1054         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
1055         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
1056         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
1057         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
1058         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
1059         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
1060         DUMP_REG(DC_COM_PIN_MISC_CONTROL);
1061         DUMP_REG(DC_COM_PIN_PM0_CONTROL);
1062         DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
1063         DUMP_REG(DC_COM_PIN_PM1_CONTROL);
1064         DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
1065         DUMP_REG(DC_COM_SPI_CONTROL);
1066         DUMP_REG(DC_COM_SPI_START_BYTE);
1067         DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
1068         DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
1069         DUMP_REG(DC_COM_HSPI_CS_DC);
1070         DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
1071         DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
1072         DUMP_REG(DC_COM_GPIO_CTRL);
1073         DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
1074         DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
1075         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
1076         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
1077         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
1078         DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
1079         DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1080         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
1081         DUMP_REG(DC_DISP_REF_TO_SYNC);
1082         DUMP_REG(DC_DISP_SYNC_WIDTH);
1083         DUMP_REG(DC_DISP_BACK_PORCH);
1084         DUMP_REG(DC_DISP_ACTIVE);
1085         DUMP_REG(DC_DISP_FRONT_PORCH);
1086         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
1087         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
1088         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
1089         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
1090         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
1091         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
1092         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
1093         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
1094         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
1095         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
1096         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
1097         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
1098         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
1099         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
1100         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
1101         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
1102         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
1103         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
1104         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
1105         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
1106         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
1107         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
1108         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
1109         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
1110         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
1111         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
1112         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
1113         DUMP_REG(DC_DISP_M0_CONTROL);
1114         DUMP_REG(DC_DISP_M1_CONTROL);
1115         DUMP_REG(DC_DISP_DI_CONTROL);
1116         DUMP_REG(DC_DISP_PP_CONTROL);
1117         DUMP_REG(DC_DISP_PP_SELECT_A);
1118         DUMP_REG(DC_DISP_PP_SELECT_B);
1119         DUMP_REG(DC_DISP_PP_SELECT_C);
1120         DUMP_REG(DC_DISP_PP_SELECT_D);
1121         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
1122         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
1123         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
1124         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
1125         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
1126         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
1127         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
1128         DUMP_REG(DC_DISP_BORDER_COLOR);
1129         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
1130         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
1131         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
1132         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
1133         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
1134         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
1135         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
1136         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
1137         DUMP_REG(DC_DISP_CURSOR_POSITION);
1138         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
1139         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
1140         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
1141         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
1142         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
1143         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
1144         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
1145         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
1146         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
1147         DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
1148         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
1149         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
1150         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
1151         DUMP_REG(DC_DISP_SD_CONTROL);
1152         DUMP_REG(DC_DISP_SD_CSC_COEFF);
1153         DUMP_REG(DC_DISP_SD_LUT(0));
1154         DUMP_REG(DC_DISP_SD_LUT(1));
1155         DUMP_REG(DC_DISP_SD_LUT(2));
1156         DUMP_REG(DC_DISP_SD_LUT(3));
1157         DUMP_REG(DC_DISP_SD_LUT(4));
1158         DUMP_REG(DC_DISP_SD_LUT(5));
1159         DUMP_REG(DC_DISP_SD_LUT(6));
1160         DUMP_REG(DC_DISP_SD_LUT(7));
1161         DUMP_REG(DC_DISP_SD_LUT(8));
1162         DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
1163         DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
1164         DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1165         DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1166         DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1167         DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1168         DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1169         DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1170         DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1171         DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1172         DUMP_REG(DC_DISP_SD_BL_TF(0));
1173         DUMP_REG(DC_DISP_SD_BL_TF(1));
1174         DUMP_REG(DC_DISP_SD_BL_TF(2));
1175         DUMP_REG(DC_DISP_SD_BL_TF(3));
1176         DUMP_REG(DC_DISP_SD_BL_CONTROL);
1177         DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1178         DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
1179         DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
1180         DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);
1181         DUMP_REG(DC_WIN_WIN_OPTIONS);
1182         DUMP_REG(DC_WIN_BYTE_SWAP);
1183         DUMP_REG(DC_WIN_BUFFER_CONTROL);
1184         DUMP_REG(DC_WIN_COLOR_DEPTH);
1185         DUMP_REG(DC_WIN_POSITION);
1186         DUMP_REG(DC_WIN_SIZE);
1187         DUMP_REG(DC_WIN_PRESCALED_SIZE);
1188         DUMP_REG(DC_WIN_H_INITIAL_DDA);
1189         DUMP_REG(DC_WIN_V_INITIAL_DDA);
1190         DUMP_REG(DC_WIN_DDA_INC);
1191         DUMP_REG(DC_WIN_LINE_STRIDE);
1192         DUMP_REG(DC_WIN_BUF_STRIDE);
1193         DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1194         DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1195         DUMP_REG(DC_WIN_DV_CONTROL);
1196         DUMP_REG(DC_WIN_BLEND_NOKEY);
1197         DUMP_REG(DC_WIN_BLEND_1WIN);
1198         DUMP_REG(DC_WIN_BLEND_2WIN_X);
1199         DUMP_REG(DC_WIN_BLEND_2WIN_Y);
1200         DUMP_REG(DC_WIN_BLEND_3WIN_XY);
1201         DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1202         DUMP_REG(DC_WINBUF_START_ADDR);
1203         DUMP_REG(DC_WINBUF_START_ADDR_NS);
1204         DUMP_REG(DC_WINBUF_START_ADDR_U);
1205         DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1206         DUMP_REG(DC_WINBUF_START_ADDR_V);
1207         DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1208         DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1209         DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1210         DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1211         DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1212         DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1213         DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1214         DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1215         DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1216
1217 #undef DUMP_REG
1218
1219         return 0;
1220 }
1221
1222 static struct drm_info_list debugfs_files[] = {
1223         { "regs", tegra_dc_show_regs, 0, NULL },
1224 };
1225
1226 static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1227 {
1228         unsigned int i;
1229         char *name;
1230         int err;
1231
1232         name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1233         dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1234         kfree(name);
1235
1236         if (!dc->debugfs)
1237                 return -ENOMEM;
1238
1239         dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1240                                     GFP_KERNEL);
1241         if (!dc->debugfs_files) {
1242                 err = -ENOMEM;
1243                 goto remove;
1244         }
1245
1246         for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1247                 dc->debugfs_files[i].data = dc;
1248
1249         err = drm_debugfs_create_files(dc->debugfs_files,
1250                                        ARRAY_SIZE(debugfs_files),
1251                                        dc->debugfs, minor);
1252         if (err < 0)
1253                 goto free;
1254
1255         dc->minor = minor;
1256
1257         return 0;
1258
1259 free:
1260         kfree(dc->debugfs_files);
1261         dc->debugfs_files = NULL;
1262 remove:
1263         debugfs_remove(dc->debugfs);
1264         dc->debugfs = NULL;
1265
1266         return err;
1267 }
1268
1269 static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1270 {
1271         drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1272                                  dc->minor);
1273         dc->minor = NULL;
1274
1275         kfree(dc->debugfs_files);
1276         dc->debugfs_files = NULL;
1277
1278         debugfs_remove(dc->debugfs);
1279         dc->debugfs = NULL;
1280
1281         return 0;
1282 }
1283
1284 static int tegra_dc_init(struct host1x_client *client)
1285 {
1286         struct drm_device *drm = dev_get_drvdata(client->parent);
1287         struct tegra_dc *dc = host1x_client_to_dc(client);
1288         struct tegra_drm *tegra = drm->dev_private;
1289         int err;
1290
1291         drm_crtc_init(drm, &dc->base, &tegra_crtc_funcs);
1292         drm_mode_crtc_set_gamma_size(&dc->base, 256);
1293         drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1294
1295         /*
1296          * Keep track of the minimum pitch alignment across all display
1297          * controllers.
1298          */
1299         if (dc->soc->pitch_align > tegra->pitch_align)
1300                 tegra->pitch_align = dc->soc->pitch_align;
1301
1302         err = tegra_dc_rgb_init(drm, dc);
1303         if (err < 0 && err != -ENODEV) {
1304                 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1305                 return err;
1306         }
1307
1308         err = tegra_dc_add_planes(drm, dc);
1309         if (err < 0)
1310                 return err;
1311
1312         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1313                 err = tegra_dc_debugfs_init(dc, drm->primary);
1314                 if (err < 0)
1315                         dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1316         }
1317
1318         err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
1319                                dev_name(dc->dev), dc);
1320         if (err < 0) {
1321                 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1322                         err);
1323                 return err;
1324         }
1325
1326         return 0;
1327 }
1328
1329 static int tegra_dc_exit(struct host1x_client *client)
1330 {
1331         struct tegra_dc *dc = host1x_client_to_dc(client);
1332         int err;
1333
1334         devm_free_irq(dc->dev, dc->irq, dc);
1335
1336         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1337                 err = tegra_dc_debugfs_exit(dc);
1338                 if (err < 0)
1339                         dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1340         }
1341
1342         err = tegra_dc_rgb_exit(dc);
1343         if (err) {
1344                 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1345                 return err;
1346         }
1347
1348         return 0;
1349 }
1350
1351 static const struct host1x_client_ops dc_client_ops = {
1352         .init = tegra_dc_init,
1353         .exit = tegra_dc_exit,
1354 };
1355
1356 static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
1357         .supports_interlacing = false,
1358         .supports_cursor = false,
1359         .supports_block_linear = false,
1360         .pitch_align = 8,
1361 };
1362
1363 static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
1364         .supports_interlacing = false,
1365         .supports_cursor = false,
1366         .supports_block_linear = false,
1367         .pitch_align = 8,
1368 };
1369
1370 static const struct tegra_dc_soc_info tegra114_dc_soc_info = {
1371         .supports_interlacing = false,
1372         .supports_cursor = false,
1373         .supports_block_linear = false,
1374         .pitch_align = 64,
1375 };
1376
1377 static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
1378         .supports_interlacing = true,
1379         .supports_cursor = true,
1380         .supports_block_linear = true,
1381         .pitch_align = 64,
1382 };
1383
1384 static const struct of_device_id tegra_dc_of_match[] = {
1385         {
1386                 .compatible = "nvidia,tegra124-dc",
1387                 .data = &tegra124_dc_soc_info,
1388         }, {
1389                 .compatible = "nvidia,tegra30-dc",
1390                 .data = &tegra30_dc_soc_info,
1391         }, {
1392                 .compatible = "nvidia,tegra20-dc",
1393                 .data = &tegra20_dc_soc_info,
1394         }, {
1395                 /* sentinel */
1396         }
1397 };
1398 MODULE_DEVICE_TABLE(of, tegra_dc_of_match);
1399
1400 static int tegra_dc_parse_dt(struct tegra_dc *dc)
1401 {
1402         struct device_node *np;
1403         u32 value = 0;
1404         int err;
1405
1406         err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1407         if (err < 0) {
1408                 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1409
1410                 /*
1411                  * If the nvidia,head property isn't present, try to find the
1412                  * correct head number by looking up the position of this
1413                  * display controller's node within the device tree. Assuming
1414                  * that the nodes are ordered properly in the DTS file and
1415                  * that the translation into a flattened device tree blob
1416                  * preserves that ordering this will actually yield the right
1417                  * head number.
1418                  *
1419                  * If those assumptions don't hold, this will still work for
1420                  * cases where only a single display controller is used.
1421                  */
1422                 for_each_matching_node(np, tegra_dc_of_match) {
1423                         if (np == dc->dev->of_node)
1424                                 break;
1425
1426                         value++;
1427                 }
1428         }
1429
1430         dc->pipe = value;
1431
1432         return 0;
1433 }
1434
1435 static int tegra_dc_probe(struct platform_device *pdev)
1436 {
1437         const struct of_device_id *id;
1438         struct resource *regs;
1439         struct tegra_dc *dc;
1440         int err;
1441
1442         dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1443         if (!dc)
1444                 return -ENOMEM;
1445
1446         id = of_match_node(tegra_dc_of_match, pdev->dev.of_node);
1447         if (!id)
1448                 return -ENODEV;
1449
1450         spin_lock_init(&dc->lock);
1451         INIT_LIST_HEAD(&dc->list);
1452         dc->dev = &pdev->dev;
1453         dc->soc = id->data;
1454
1455         err = tegra_dc_parse_dt(dc);
1456         if (err < 0)
1457                 return err;
1458
1459         dc->clk = devm_clk_get(&pdev->dev, NULL);
1460         if (IS_ERR(dc->clk)) {
1461                 dev_err(&pdev->dev, "failed to get clock\n");
1462                 return PTR_ERR(dc->clk);
1463         }
1464
1465         dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1466         if (IS_ERR(dc->rst)) {
1467                 dev_err(&pdev->dev, "failed to get reset\n");
1468                 return PTR_ERR(dc->rst);
1469         }
1470
1471         err = clk_prepare_enable(dc->clk);
1472         if (err < 0)
1473                 return err;
1474
1475         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1476         dc->regs = devm_ioremap_resource(&pdev->dev, regs);
1477         if (IS_ERR(dc->regs))
1478                 return PTR_ERR(dc->regs);
1479
1480         dc->irq = platform_get_irq(pdev, 0);
1481         if (dc->irq < 0) {
1482                 dev_err(&pdev->dev, "failed to get IRQ\n");
1483                 return -ENXIO;
1484         }
1485
1486         INIT_LIST_HEAD(&dc->client.list);
1487         dc->client.ops = &dc_client_ops;
1488         dc->client.dev = &pdev->dev;
1489
1490         err = tegra_dc_rgb_probe(dc);
1491         if (err < 0 && err != -ENODEV) {
1492                 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
1493                 return err;
1494         }
1495
1496         err = host1x_client_register(&dc->client);
1497         if (err < 0) {
1498                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1499                         err);
1500                 return err;
1501         }
1502
1503         platform_set_drvdata(pdev, dc);
1504
1505         return 0;
1506 }
1507
1508 static int tegra_dc_remove(struct platform_device *pdev)
1509 {
1510         struct tegra_dc *dc = platform_get_drvdata(pdev);
1511         int err;
1512
1513         err = host1x_client_unregister(&dc->client);
1514         if (err < 0) {
1515                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1516                         err);
1517                 return err;
1518         }
1519
1520         err = tegra_dc_rgb_remove(dc);
1521         if (err < 0) {
1522                 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
1523                 return err;
1524         }
1525
1526         reset_control_assert(dc->rst);
1527         clk_disable_unprepare(dc->clk);
1528
1529         return 0;
1530 }
1531
1532 struct platform_driver tegra_dc_driver = {
1533         .driver = {
1534                 .name = "tegra-dc",
1535                 .owner = THIS_MODULE,
1536                 .of_match_table = tegra_dc_of_match,
1537         },
1538         .probe = tegra_dc_probe,
1539         .remove = tegra_dc_remove,
1540 };