2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <linux/clk.h>
11 #include <linux/debugfs.h>
12 #include <linux/reset.h>
18 struct tegra_dc_soc_info {
19 bool supports_interlacing;
24 struct drm_plane base;
28 static inline struct tegra_plane *to_tegra_plane(struct drm_plane *plane)
30 return container_of(plane, struct tegra_plane, base);
33 static unsigned int tegra_dc_format(uint32_t format, uint32_t *swap)
35 /* assume no swapping of fetched data */
37 *swap = BYTE_SWAP_NOSWAP;
40 case DRM_FORMAT_XBGR8888:
41 return WIN_COLOR_DEPTH_R8G8B8A8;
43 case DRM_FORMAT_XRGB8888:
44 return WIN_COLOR_DEPTH_B8G8R8A8;
46 case DRM_FORMAT_RGB565:
47 return WIN_COLOR_DEPTH_B5G6R5;
50 return WIN_COLOR_DEPTH_YCbCr422;
54 *swap = BYTE_SWAP_SWAP2;
56 return WIN_COLOR_DEPTH_YCbCr422;
58 case DRM_FORMAT_YUV420:
59 return WIN_COLOR_DEPTH_YCbCr420P;
61 case DRM_FORMAT_YUV422:
62 return WIN_COLOR_DEPTH_YCbCr422P;
68 WARN(1, "unsupported pixel format %u, using default\n", format);
69 return WIN_COLOR_DEPTH_B8G8R8A8;
72 static bool tegra_dc_format_is_yuv(unsigned int format, bool *planar)
75 case WIN_COLOR_DEPTH_YCbCr422:
76 case WIN_COLOR_DEPTH_YUV422:
82 case WIN_COLOR_DEPTH_YCbCr420P:
83 case WIN_COLOR_DEPTH_YUV420P:
84 case WIN_COLOR_DEPTH_YCbCr422P:
85 case WIN_COLOR_DEPTH_YUV422P:
86 case WIN_COLOR_DEPTH_YCbCr422R:
87 case WIN_COLOR_DEPTH_YUV422R:
88 case WIN_COLOR_DEPTH_YCbCr422RA:
89 case WIN_COLOR_DEPTH_YUV422RA:
99 static inline u32 compute_dda_inc(unsigned int in, unsigned int out, bool v,
102 fixed20_12 outf = dfixed_init(out);
103 fixed20_12 inf = dfixed_init(in);
124 outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
125 inf.full -= dfixed_const(1);
127 dda_inc = dfixed_div(inf, outf);
128 dda_inc = min_t(u32, dda_inc, dfixed_const(max));
133 static inline u32 compute_initial_dda(unsigned int in)
135 fixed20_12 inf = dfixed_init(in);
136 return dfixed_frac(inf);
139 static int tegra_dc_setup_window(struct tegra_dc *dc, unsigned int index,
140 const struct tegra_dc_window *window)
142 unsigned h_offset, v_offset, h_size, v_size, h_dda, v_dda, bpp;
147 * For YUV planar modes, the number of bytes per pixel takes into
148 * account only the luma component and therefore is 1.
150 yuv = tegra_dc_format_is_yuv(window->format, &planar);
152 bpp = window->bits_per_pixel / 8;
154 bpp = planar ? 1 : 2;
156 value = WINDOW_A_SELECT << index;
157 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
159 tegra_dc_writel(dc, window->format, DC_WIN_COLOR_DEPTH);
160 tegra_dc_writel(dc, window->swap, DC_WIN_BYTE_SWAP);
162 value = V_POSITION(window->dst.y) | H_POSITION(window->dst.x);
163 tegra_dc_writel(dc, value, DC_WIN_POSITION);
165 value = V_SIZE(window->dst.h) | H_SIZE(window->dst.w);
166 tegra_dc_writel(dc, value, DC_WIN_SIZE);
168 h_offset = window->src.x * bpp;
169 v_offset = window->src.y;
170 h_size = window->src.w * bpp;
171 v_size = window->src.h;
173 value = V_PRESCALED_SIZE(v_size) | H_PRESCALED_SIZE(h_size);
174 tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
177 * For DDA computations the number of bytes per pixel for YUV planar
178 * modes needs to take into account all Y, U and V components.
183 h_dda = compute_dda_inc(window->src.w, window->dst.w, false, bpp);
184 v_dda = compute_dda_inc(window->src.h, window->dst.h, true, bpp);
186 value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
187 tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
189 h_dda = compute_initial_dda(window->src.x);
190 v_dda = compute_initial_dda(window->src.y);
192 tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
193 tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
195 tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
196 tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
198 tegra_dc_writel(dc, window->base[0], DC_WINBUF_START_ADDR);
201 tegra_dc_writel(dc, window->base[1], DC_WINBUF_START_ADDR_U);
202 tegra_dc_writel(dc, window->base[2], DC_WINBUF_START_ADDR_V);
203 value = window->stride[1] << 16 | window->stride[0];
204 tegra_dc_writel(dc, value, DC_WIN_LINE_STRIDE);
206 tegra_dc_writel(dc, window->stride[0], DC_WIN_LINE_STRIDE);
209 if (window->bottom_up)
210 v_offset += window->src.h - 1;
212 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
213 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
216 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
217 DC_WIN_BUFFER_ADDR_MODE_TILE;
219 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
220 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
223 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
228 /* setup default colorspace conversion coefficients */
229 tegra_dc_writel(dc, 0x00f0, DC_WIN_CSC_YOF);
230 tegra_dc_writel(dc, 0x012a, DC_WIN_CSC_KYRGB);
231 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KUR);
232 tegra_dc_writel(dc, 0x0198, DC_WIN_CSC_KVR);
233 tegra_dc_writel(dc, 0x039b, DC_WIN_CSC_KUG);
234 tegra_dc_writel(dc, 0x032f, DC_WIN_CSC_KVG);
235 tegra_dc_writel(dc, 0x0204, DC_WIN_CSC_KUB);
236 tegra_dc_writel(dc, 0x0000, DC_WIN_CSC_KVB);
239 } else if (window->bits_per_pixel < 24) {
240 value |= COLOR_EXPAND;
243 if (window->bottom_up)
244 value |= V_DIRECTION;
246 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
249 * Disable blending and assume Window A is the bottom-most window,
250 * Window C is the top-most window and Window B is in the middle.
252 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_NOKEY);
253 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_1WIN);
257 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_X);
258 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
259 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
263 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
264 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_2WIN_Y);
265 tegra_dc_writel(dc, 0x000000, DC_WIN_BLEND_3WIN_XY);
269 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_X);
270 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_2WIN_Y);
271 tegra_dc_writel(dc, 0xffff00, DC_WIN_BLEND_3WIN_XY);
275 tegra_dc_writel(dc, WIN_A_UPDATE << index, DC_CMD_STATE_CONTROL);
276 tegra_dc_writel(dc, WIN_A_ACT_REQ << index, DC_CMD_STATE_CONTROL);
281 static int tegra_plane_update(struct drm_plane *plane, struct drm_crtc *crtc,
282 struct drm_framebuffer *fb, int crtc_x,
283 int crtc_y, unsigned int crtc_w,
284 unsigned int crtc_h, uint32_t src_x,
285 uint32_t src_y, uint32_t src_w, uint32_t src_h)
287 struct tegra_plane *p = to_tegra_plane(plane);
288 struct tegra_dc *dc = to_tegra_dc(crtc);
289 struct tegra_dc_window window;
292 memset(&window, 0, sizeof(window));
293 window.src.x = src_x >> 16;
294 window.src.y = src_y >> 16;
295 window.src.w = src_w >> 16;
296 window.src.h = src_h >> 16;
297 window.dst.x = crtc_x;
298 window.dst.y = crtc_y;
299 window.dst.w = crtc_w;
300 window.dst.h = crtc_h;
301 window.format = tegra_dc_format(fb->pixel_format, &window.swap);
302 window.bits_per_pixel = fb->bits_per_pixel;
303 window.bottom_up = tegra_fb_is_bottom_up(fb);
304 window.tiled = tegra_fb_is_tiled(fb);
306 for (i = 0; i < drm_format_num_planes(fb->pixel_format); i++) {
307 struct tegra_bo *bo = tegra_fb_get_plane(fb, i);
309 window.base[i] = bo->paddr + fb->offsets[i];
312 * Tegra doesn't support different strides for U and V planes
313 * so we display a warning if the user tries to display a
314 * framebuffer with such a configuration.
317 if (fb->pitches[i] != window.stride[1])
318 DRM_ERROR("unsupported UV-plane configuration\n");
320 window.stride[i] = fb->pitches[i];
324 return tegra_dc_setup_window(dc, p->index, &window);
327 static int tegra_plane_disable(struct drm_plane *plane)
329 struct tegra_dc *dc = to_tegra_dc(plane->crtc);
330 struct tegra_plane *p = to_tegra_plane(plane);
336 value = WINDOW_A_SELECT << p->index;
337 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
339 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
340 value &= ~WIN_ENABLE;
341 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
343 tegra_dc_writel(dc, WIN_A_UPDATE << p->index, DC_CMD_STATE_CONTROL);
344 tegra_dc_writel(dc, WIN_A_ACT_REQ << p->index, DC_CMD_STATE_CONTROL);
349 static void tegra_plane_destroy(struct drm_plane *plane)
351 struct tegra_plane *p = to_tegra_plane(plane);
353 tegra_plane_disable(plane);
354 drm_plane_cleanup(plane);
358 static const struct drm_plane_funcs tegra_plane_funcs = {
359 .update_plane = tegra_plane_update,
360 .disable_plane = tegra_plane_disable,
361 .destroy = tegra_plane_destroy,
364 static const uint32_t plane_formats[] = {
374 static int tegra_dc_add_planes(struct drm_device *drm, struct tegra_dc *dc)
379 for (i = 0; i < 2; i++) {
380 struct tegra_plane *plane;
382 plane = kzalloc(sizeof(*plane), GFP_KERNEL);
386 plane->index = 1 + i;
388 err = drm_plane_init(drm, &plane->base, 1 << dc->pipe,
389 &tegra_plane_funcs, plane_formats,
390 ARRAY_SIZE(plane_formats), false);
400 static int tegra_dc_set_base(struct tegra_dc *dc, int x, int y,
401 struct drm_framebuffer *fb)
403 struct tegra_bo *bo = tegra_fb_get_plane(fb, 0);
404 unsigned int h_offset = 0, v_offset = 0;
405 unsigned int format, swap;
408 tegra_dc_writel(dc, WINDOW_A_SELECT, DC_CMD_DISPLAY_WINDOW_HEADER);
410 value = fb->offsets[0] + y * fb->pitches[0] +
411 x * fb->bits_per_pixel / 8;
413 tegra_dc_writel(dc, bo->paddr + value, DC_WINBUF_START_ADDR);
414 tegra_dc_writel(dc, fb->pitches[0], DC_WIN_LINE_STRIDE);
416 format = tegra_dc_format(fb->pixel_format, &swap);
417 tegra_dc_writel(dc, format, DC_WIN_COLOR_DEPTH);
418 tegra_dc_writel(dc, swap, DC_WIN_BYTE_SWAP);
420 if (tegra_fb_is_tiled(fb)) {
421 value = DC_WIN_BUFFER_ADDR_MODE_TILE_UV |
422 DC_WIN_BUFFER_ADDR_MODE_TILE;
424 value = DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV |
425 DC_WIN_BUFFER_ADDR_MODE_LINEAR;
428 tegra_dc_writel(dc, value, DC_WIN_BUFFER_ADDR_MODE);
430 /* make sure bottom-up buffers are properly displayed */
431 if (tegra_fb_is_bottom_up(fb)) {
432 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
433 value |= V_DIRECTION;
434 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
436 v_offset += fb->height - 1;
438 value = tegra_dc_readl(dc, DC_WIN_WIN_OPTIONS);
439 value &= ~V_DIRECTION;
440 tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
443 tegra_dc_writel(dc, h_offset, DC_WINBUF_ADDR_H_OFFSET);
444 tegra_dc_writel(dc, v_offset, DC_WINBUF_ADDR_V_OFFSET);
446 value = GENERAL_UPDATE | WIN_A_UPDATE;
447 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
449 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
450 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
455 void tegra_dc_enable_vblank(struct tegra_dc *dc)
457 unsigned long value, flags;
459 spin_lock_irqsave(&dc->lock, flags);
461 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
463 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
465 spin_unlock_irqrestore(&dc->lock, flags);
468 void tegra_dc_disable_vblank(struct tegra_dc *dc)
470 unsigned long value, flags;
472 spin_lock_irqsave(&dc->lock, flags);
474 value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
475 value &= ~VBLANK_INT;
476 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
478 spin_unlock_irqrestore(&dc->lock, flags);
481 static int tegra_dc_cursor_set2(struct drm_crtc *crtc, struct drm_file *file,
482 uint32_t handle, uint32_t width,
483 uint32_t height, int32_t hot_x, int32_t hot_y)
485 unsigned long value = CURSOR_CLIP_DISPLAY;
486 struct tegra_dc *dc = to_tegra_dc(crtc);
487 struct drm_gem_object *gem;
488 struct tegra_bo *bo = NULL;
490 if (!dc->soc->supports_cursor)
498 value |= CURSOR_SIZE_32x32;
502 value |= CURSOR_SIZE_64x64;
506 value |= CURSOR_SIZE_128x128;
509 value |= CURSOR_SIZE_256x256;
517 gem = drm_gem_object_lookup(crtc->dev, file, handle);
521 bo = to_tegra_bo(gem);
525 unsigned long addr = (bo->paddr & 0xfffffc00) >> 10;
526 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
527 unsigned long high = (bo->paddr & 0xfffffffc) >> 32;
530 tegra_dc_writel(dc, value | addr, DC_DISP_CURSOR_START_ADDR);
532 #ifdef CONFIG_ARCH_DMA_ADDR_T_64BIT
533 tegra_dc_writel(dc, high, DC_DISP_CURSOR_START_ADDR_HI);
536 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
537 value |= CURSOR_ENABLE;
538 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
540 value = tegra_dc_readl(dc, DC_DISP_BLEND_CURSOR_CONTROL);
541 value &= ~CURSOR_DST_BLEND_MASK;
542 value &= ~CURSOR_SRC_BLEND_MASK;
543 value |= CURSOR_MODE_NORMAL;
544 value |= CURSOR_DST_BLEND_NEG_K1_TIMES_SRC;
545 value |= CURSOR_SRC_BLEND_K1_TIMES_SRC;
546 value |= CURSOR_ALPHA;
547 tegra_dc_writel(dc, value, DC_DISP_BLEND_CURSOR_CONTROL);
549 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
550 value &= ~CURSOR_ENABLE;
551 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
554 tegra_dc_writel(dc, CURSOR_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
555 tegra_dc_writel(dc, CURSOR_ACT_REQ, DC_CMD_STATE_CONTROL);
557 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
558 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
563 static int tegra_dc_cursor_move(struct drm_crtc *crtc, int x, int y)
565 struct tegra_dc *dc = to_tegra_dc(crtc);
568 if (!dc->soc->supports_cursor)
571 value = ((y & 0x3fff) << 16) | (x & 0x3fff);
572 tegra_dc_writel(dc, value, DC_DISP_CURSOR_POSITION);
574 tegra_dc_writel(dc, CURSOR_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
575 tegra_dc_writel(dc, CURSOR_ACT_REQ, DC_CMD_STATE_CONTROL);
577 /* XXX: only required on generations earlier than Tegra124? */
578 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
579 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
584 static void tegra_dc_finish_page_flip(struct tegra_dc *dc)
586 struct drm_device *drm = dc->base.dev;
587 struct drm_crtc *crtc = &dc->base;
588 unsigned long flags, base;
594 bo = tegra_fb_get_plane(crtc->primary->fb, 0);
596 /* check if new start address has been latched */
597 tegra_dc_writel(dc, READ_MUX, DC_CMD_STATE_ACCESS);
598 base = tegra_dc_readl(dc, DC_WINBUF_START_ADDR);
599 tegra_dc_writel(dc, 0, DC_CMD_STATE_ACCESS);
601 if (base == bo->paddr + crtc->primary->fb->offsets[0]) {
602 spin_lock_irqsave(&drm->event_lock, flags);
603 drm_send_vblank_event(drm, dc->pipe, dc->event);
604 drm_vblank_put(drm, dc->pipe);
606 spin_unlock_irqrestore(&drm->event_lock, flags);
610 void tegra_dc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
612 struct tegra_dc *dc = to_tegra_dc(crtc);
613 struct drm_device *drm = crtc->dev;
616 spin_lock_irqsave(&drm->event_lock, flags);
618 if (dc->event && dc->event->base.file_priv == file) {
619 dc->event->base.destroy(&dc->event->base);
620 drm_vblank_put(drm, dc->pipe);
624 spin_unlock_irqrestore(&drm->event_lock, flags);
627 static int tegra_dc_page_flip(struct drm_crtc *crtc, struct drm_framebuffer *fb,
628 struct drm_pending_vblank_event *event, uint32_t page_flip_flags)
630 struct tegra_dc *dc = to_tegra_dc(crtc);
631 struct drm_device *drm = crtc->dev;
637 event->pipe = dc->pipe;
639 drm_vblank_get(drm, dc->pipe);
642 tegra_dc_set_base(dc, 0, 0, fb);
643 crtc->primary->fb = fb;
648 static void drm_crtc_clear(struct drm_crtc *crtc)
650 memset(crtc, 0, sizeof(*crtc));
653 static void tegra_dc_destroy(struct drm_crtc *crtc)
655 drm_crtc_cleanup(crtc);
656 drm_crtc_clear(crtc);
659 static const struct drm_crtc_funcs tegra_crtc_funcs = {
660 .cursor_set2 = tegra_dc_cursor_set2,
661 .cursor_move = tegra_dc_cursor_move,
662 .page_flip = tegra_dc_page_flip,
663 .set_config = drm_crtc_helper_set_config,
664 .destroy = tegra_dc_destroy,
667 static void tegra_crtc_disable(struct drm_crtc *crtc)
669 struct tegra_dc *dc = to_tegra_dc(crtc);
670 struct drm_device *drm = crtc->dev;
671 struct drm_plane *plane;
673 drm_for_each_legacy_plane(plane, &drm->mode_config.plane_list) {
674 if (plane->crtc == crtc) {
675 tegra_plane_disable(plane);
679 drm_framebuffer_unreference(plane->fb);
685 drm_vblank_off(drm, dc->pipe);
688 static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
689 const struct drm_display_mode *mode,
690 struct drm_display_mode *adjusted)
695 static int tegra_dc_set_timings(struct tegra_dc *dc,
696 struct drm_display_mode *mode)
698 unsigned int h_ref_to_sync = 1;
699 unsigned int v_ref_to_sync = 1;
702 tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
704 value = (v_ref_to_sync << 16) | h_ref_to_sync;
705 tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
707 value = ((mode->vsync_end - mode->vsync_start) << 16) |
708 ((mode->hsync_end - mode->hsync_start) << 0);
709 tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
711 value = ((mode->vtotal - mode->vsync_end) << 16) |
712 ((mode->htotal - mode->hsync_end) << 0);
713 tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
715 value = ((mode->vsync_start - mode->vdisplay) << 16) |
716 ((mode->hsync_start - mode->hdisplay) << 0);
717 tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
719 value = (mode->vdisplay << 16) | mode->hdisplay;
720 tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
725 static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
726 struct drm_display_mode *mode)
728 unsigned long pclk = mode->clock * 1000;
729 struct tegra_dc *dc = to_tegra_dc(crtc);
730 struct tegra_output *output = NULL;
731 struct drm_encoder *encoder;
736 list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head)
737 if (encoder->crtc == crtc) {
738 output = encoder_to_output(encoder);
746 * This assumes that the parent clock is pll_d_out0 or pll_d2_out
747 * respectively, each of which divides the base pll_d by 2.
749 err = tegra_output_setup_clock(output, dc->clk, pclk, &div);
751 dev_err(dc->dev, "failed to setup clock: %ld\n", err);
755 DRM_DEBUG_KMS("rate: %lu, div: %u\n", clk_get_rate(dc->clk), div);
757 value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
758 tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
763 static int tegra_crtc_mode_set(struct drm_crtc *crtc,
764 struct drm_display_mode *mode,
765 struct drm_display_mode *adjusted,
766 int x, int y, struct drm_framebuffer *old_fb)
768 struct tegra_bo *bo = tegra_fb_get_plane(crtc->primary->fb, 0);
769 struct tegra_dc *dc = to_tegra_dc(crtc);
770 struct tegra_dc_window window;
774 drm_vblank_pre_modeset(crtc->dev, dc->pipe);
776 err = tegra_crtc_setup_clk(crtc, mode);
778 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err);
782 /* program display mode */
783 tegra_dc_set_timings(dc, mode);
785 /* interlacing isn't supported yet, so disable it */
786 if (dc->soc->supports_interlacing) {
787 value = tegra_dc_readl(dc, DC_DISP_INTERLACE_CONTROL);
788 value &= ~INTERLACE_ENABLE;
789 tegra_dc_writel(dc, value, DC_DISP_INTERLACE_CONTROL);
792 /* setup window parameters */
793 memset(&window, 0, sizeof(window));
796 window.src.w = mode->hdisplay;
797 window.src.h = mode->vdisplay;
800 window.dst.w = mode->hdisplay;
801 window.dst.h = mode->vdisplay;
802 window.format = tegra_dc_format(crtc->primary->fb->pixel_format,
804 window.bits_per_pixel = crtc->primary->fb->bits_per_pixel;
805 window.stride[0] = crtc->primary->fb->pitches[0];
806 window.base[0] = bo->paddr;
808 err = tegra_dc_setup_window(dc, 0, &window);
810 dev_err(dc->dev, "failed to enable root plane\n");
815 static int tegra_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
816 struct drm_framebuffer *old_fb)
818 struct tegra_dc *dc = to_tegra_dc(crtc);
820 return tegra_dc_set_base(dc, x, y, crtc->primary->fb);
823 static void tegra_crtc_prepare(struct drm_crtc *crtc)
825 struct tegra_dc *dc = to_tegra_dc(crtc);
829 /* hardware initialization */
830 reset_control_deassert(dc->rst);
831 usleep_range(10000, 20000);
834 syncpt = SYNCPT_VBLANK1;
836 syncpt = SYNCPT_VBLANK0;
838 /* initialize display controller */
839 tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
840 tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
842 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
843 tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
845 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
846 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
847 tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
849 /* initialize timer */
850 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
851 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
852 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
854 value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
855 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
856 tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
858 value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
859 tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
861 value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
862 tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
865 static void tegra_crtc_commit(struct drm_crtc *crtc)
867 struct tegra_dc *dc = to_tegra_dc(crtc);
870 value = GENERAL_UPDATE | WIN_A_UPDATE;
871 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
873 value = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
874 tegra_dc_writel(dc, value, DC_CMD_STATE_CONTROL);
876 drm_vblank_post_modeset(crtc->dev, dc->pipe);
879 static void tegra_crtc_load_lut(struct drm_crtc *crtc)
883 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
884 .disable = tegra_crtc_disable,
885 .mode_fixup = tegra_crtc_mode_fixup,
886 .mode_set = tegra_crtc_mode_set,
887 .mode_set_base = tegra_crtc_mode_set_base,
888 .prepare = tegra_crtc_prepare,
889 .commit = tegra_crtc_commit,
890 .load_lut = tegra_crtc_load_lut,
893 static irqreturn_t tegra_dc_irq(int irq, void *data)
895 struct tegra_dc *dc = data;
896 unsigned long status;
898 status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
899 tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
901 if (status & FRAME_END_INT) {
903 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
907 if (status & VBLANK_INT) {
909 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
911 drm_handle_vblank(dc->base.dev, dc->pipe);
912 tegra_dc_finish_page_flip(dc);
915 if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
917 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
924 static int tegra_dc_show_regs(struct seq_file *s, void *data)
926 struct drm_info_node *node = s->private;
927 struct tegra_dc *dc = node->info_ent->data;
929 #define DUMP_REG(name) \
930 seq_printf(s, "%-40s %#05x %08lx\n", #name, name, \
931 tegra_dc_readl(dc, name))
933 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
934 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
935 DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
936 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
937 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
938 DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
939 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
940 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
941 DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
942 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
943 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
944 DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
945 DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
946 DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
947 DUMP_REG(DC_CMD_DISPLAY_COMMAND);
948 DUMP_REG(DC_CMD_SIGNAL_RAISE);
949 DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
950 DUMP_REG(DC_CMD_INT_STATUS);
951 DUMP_REG(DC_CMD_INT_MASK);
952 DUMP_REG(DC_CMD_INT_ENABLE);
953 DUMP_REG(DC_CMD_INT_TYPE);
954 DUMP_REG(DC_CMD_INT_POLARITY);
955 DUMP_REG(DC_CMD_SIGNAL_RAISE1);
956 DUMP_REG(DC_CMD_SIGNAL_RAISE2);
957 DUMP_REG(DC_CMD_SIGNAL_RAISE3);
958 DUMP_REG(DC_CMD_STATE_ACCESS);
959 DUMP_REG(DC_CMD_STATE_CONTROL);
960 DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
961 DUMP_REG(DC_CMD_REG_ACT_CONTROL);
962 DUMP_REG(DC_COM_CRC_CONTROL);
963 DUMP_REG(DC_COM_CRC_CHECKSUM);
964 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
965 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
966 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
967 DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
968 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
969 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
970 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
971 DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
972 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
973 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
974 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
975 DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
976 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
977 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
978 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
979 DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
980 DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
981 DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
982 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
983 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
984 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
985 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
986 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
987 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
988 DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
989 DUMP_REG(DC_COM_PIN_MISC_CONTROL);
990 DUMP_REG(DC_COM_PIN_PM0_CONTROL);
991 DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
992 DUMP_REG(DC_COM_PIN_PM1_CONTROL);
993 DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
994 DUMP_REG(DC_COM_SPI_CONTROL);
995 DUMP_REG(DC_COM_SPI_START_BYTE);
996 DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
997 DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
998 DUMP_REG(DC_COM_HSPI_CS_DC);
999 DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
1000 DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
1001 DUMP_REG(DC_COM_GPIO_CTRL);
1002 DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
1003 DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
1004 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
1005 DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
1006 DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
1007 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
1008 DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
1009 DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
1010 DUMP_REG(DC_DISP_REF_TO_SYNC);
1011 DUMP_REG(DC_DISP_SYNC_WIDTH);
1012 DUMP_REG(DC_DISP_BACK_PORCH);
1013 DUMP_REG(DC_DISP_ACTIVE);
1014 DUMP_REG(DC_DISP_FRONT_PORCH);
1015 DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
1016 DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
1017 DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
1018 DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
1019 DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
1020 DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
1021 DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
1022 DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
1023 DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
1024 DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
1025 DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
1026 DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
1027 DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
1028 DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
1029 DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
1030 DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
1031 DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
1032 DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
1033 DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
1034 DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
1035 DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
1036 DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
1037 DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
1038 DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
1039 DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
1040 DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
1041 DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
1042 DUMP_REG(DC_DISP_M0_CONTROL);
1043 DUMP_REG(DC_DISP_M1_CONTROL);
1044 DUMP_REG(DC_DISP_DI_CONTROL);
1045 DUMP_REG(DC_DISP_PP_CONTROL);
1046 DUMP_REG(DC_DISP_PP_SELECT_A);
1047 DUMP_REG(DC_DISP_PP_SELECT_B);
1048 DUMP_REG(DC_DISP_PP_SELECT_C);
1049 DUMP_REG(DC_DISP_PP_SELECT_D);
1050 DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
1051 DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
1052 DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
1053 DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
1054 DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
1055 DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
1056 DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
1057 DUMP_REG(DC_DISP_BORDER_COLOR);
1058 DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
1059 DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
1060 DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
1061 DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
1062 DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
1063 DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
1064 DUMP_REG(DC_DISP_CURSOR_START_ADDR);
1065 DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
1066 DUMP_REG(DC_DISP_CURSOR_POSITION);
1067 DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
1068 DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
1069 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
1070 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
1071 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
1072 DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
1073 DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
1074 DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
1075 DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
1076 DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
1077 DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
1078 DUMP_REG(DC_DISP_DAC_CRT_CTRL);
1079 DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
1080 DUMP_REG(DC_DISP_SD_CONTROL);
1081 DUMP_REG(DC_DISP_SD_CSC_COEFF);
1082 DUMP_REG(DC_DISP_SD_LUT(0));
1083 DUMP_REG(DC_DISP_SD_LUT(1));
1084 DUMP_REG(DC_DISP_SD_LUT(2));
1085 DUMP_REG(DC_DISP_SD_LUT(3));
1086 DUMP_REG(DC_DISP_SD_LUT(4));
1087 DUMP_REG(DC_DISP_SD_LUT(5));
1088 DUMP_REG(DC_DISP_SD_LUT(6));
1089 DUMP_REG(DC_DISP_SD_LUT(7));
1090 DUMP_REG(DC_DISP_SD_LUT(8));
1091 DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
1092 DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
1093 DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
1094 DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
1095 DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
1096 DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
1097 DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
1098 DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
1099 DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
1100 DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
1101 DUMP_REG(DC_DISP_SD_BL_TF(0));
1102 DUMP_REG(DC_DISP_SD_BL_TF(1));
1103 DUMP_REG(DC_DISP_SD_BL_TF(2));
1104 DUMP_REG(DC_DISP_SD_BL_TF(3));
1105 DUMP_REG(DC_DISP_SD_BL_CONTROL);
1106 DUMP_REG(DC_DISP_SD_HW_K_VALUES);
1107 DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
1108 DUMP_REG(DC_DISP_CURSOR_START_ADDR_HI);
1109 DUMP_REG(DC_DISP_BLEND_CURSOR_CONTROL);
1110 DUMP_REG(DC_WIN_WIN_OPTIONS);
1111 DUMP_REG(DC_WIN_BYTE_SWAP);
1112 DUMP_REG(DC_WIN_BUFFER_CONTROL);
1113 DUMP_REG(DC_WIN_COLOR_DEPTH);
1114 DUMP_REG(DC_WIN_POSITION);
1115 DUMP_REG(DC_WIN_SIZE);
1116 DUMP_REG(DC_WIN_PRESCALED_SIZE);
1117 DUMP_REG(DC_WIN_H_INITIAL_DDA);
1118 DUMP_REG(DC_WIN_V_INITIAL_DDA);
1119 DUMP_REG(DC_WIN_DDA_INC);
1120 DUMP_REG(DC_WIN_LINE_STRIDE);
1121 DUMP_REG(DC_WIN_BUF_STRIDE);
1122 DUMP_REG(DC_WIN_UV_BUF_STRIDE);
1123 DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
1124 DUMP_REG(DC_WIN_DV_CONTROL);
1125 DUMP_REG(DC_WIN_BLEND_NOKEY);
1126 DUMP_REG(DC_WIN_BLEND_1WIN);
1127 DUMP_REG(DC_WIN_BLEND_2WIN_X);
1128 DUMP_REG(DC_WIN_BLEND_2WIN_Y);
1129 DUMP_REG(DC_WIN_BLEND_3WIN_XY);
1130 DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
1131 DUMP_REG(DC_WINBUF_START_ADDR);
1132 DUMP_REG(DC_WINBUF_START_ADDR_NS);
1133 DUMP_REG(DC_WINBUF_START_ADDR_U);
1134 DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
1135 DUMP_REG(DC_WINBUF_START_ADDR_V);
1136 DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
1137 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
1138 DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
1139 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
1140 DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
1141 DUMP_REG(DC_WINBUF_UFLOW_STATUS);
1142 DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
1143 DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
1144 DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
1151 static struct drm_info_list debugfs_files[] = {
1152 { "regs", tegra_dc_show_regs, 0, NULL },
1155 static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
1161 name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
1162 dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
1168 dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1170 if (!dc->debugfs_files) {
1175 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1176 dc->debugfs_files[i].data = dc;
1178 err = drm_debugfs_create_files(dc->debugfs_files,
1179 ARRAY_SIZE(debugfs_files),
1180 dc->debugfs, minor);
1189 kfree(dc->debugfs_files);
1190 dc->debugfs_files = NULL;
1192 debugfs_remove(dc->debugfs);
1198 static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
1200 drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
1204 kfree(dc->debugfs_files);
1205 dc->debugfs_files = NULL;
1207 debugfs_remove(dc->debugfs);
1213 static int tegra_dc_init(struct host1x_client *client)
1215 struct drm_device *drm = dev_get_drvdata(client->parent);
1216 struct tegra_dc *dc = host1x_client_to_dc(client);
1219 drm_crtc_init(drm, &dc->base, &tegra_crtc_funcs);
1220 drm_mode_crtc_set_gamma_size(&dc->base, 256);
1221 drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
1223 err = tegra_dc_rgb_init(drm, dc);
1224 if (err < 0 && err != -ENODEV) {
1225 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
1229 err = tegra_dc_add_planes(drm, dc);
1233 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1234 err = tegra_dc_debugfs_init(dc, drm->primary);
1236 dev_err(dc->dev, "debugfs setup failed: %d\n", err);
1239 err = devm_request_irq(dc->dev, dc->irq, tegra_dc_irq, 0,
1240 dev_name(dc->dev), dc);
1242 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
1250 static int tegra_dc_exit(struct host1x_client *client)
1252 struct tegra_dc *dc = host1x_client_to_dc(client);
1255 devm_free_irq(dc->dev, dc->irq, dc);
1257 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1258 err = tegra_dc_debugfs_exit(dc);
1260 dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
1263 err = tegra_dc_rgb_exit(dc);
1265 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
1272 static const struct host1x_client_ops dc_client_ops = {
1273 .init = tegra_dc_init,
1274 .exit = tegra_dc_exit,
1277 static const struct tegra_dc_soc_info tegra20_dc_soc_info = {
1278 .supports_interlacing = false,
1279 .supports_cursor = false,
1282 static const struct tegra_dc_soc_info tegra30_dc_soc_info = {
1283 .supports_interlacing = false,
1284 .supports_cursor = false,
1287 static const struct tegra_dc_soc_info tegra124_dc_soc_info = {
1288 .supports_interlacing = true,
1289 .supports_cursor = true,
1292 static const struct of_device_id tegra_dc_of_match[] = {
1294 .compatible = "nvidia,tegra124-dc",
1295 .data = &tegra124_dc_soc_info,
1297 .compatible = "nvidia,tegra30-dc",
1298 .data = &tegra30_dc_soc_info,
1300 .compatible = "nvidia,tegra20-dc",
1301 .data = &tegra20_dc_soc_info,
1307 static int tegra_dc_parse_dt(struct tegra_dc *dc)
1309 struct device_node *np;
1313 err = of_property_read_u32(dc->dev->of_node, "nvidia,head", &value);
1315 dev_err(dc->dev, "missing \"nvidia,head\" property\n");
1318 * If the nvidia,head property isn't present, try to find the
1319 * correct head number by looking up the position of this
1320 * display controller's node within the device tree. Assuming
1321 * that the nodes are ordered properly in the DTS file and
1322 * that the translation into a flattened device tree blob
1323 * preserves that ordering this will actually yield the right
1326 * If those assumptions don't hold, this will still work for
1327 * cases where only a single display controller is used.
1329 for_each_matching_node(np, tegra_dc_of_match) {
1330 if (np == dc->dev->of_node)
1342 static int tegra_dc_probe(struct platform_device *pdev)
1344 const struct of_device_id *id;
1345 struct resource *regs;
1346 struct tegra_dc *dc;
1349 dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
1353 id = of_match_node(tegra_dc_of_match, pdev->dev.of_node);
1357 spin_lock_init(&dc->lock);
1358 INIT_LIST_HEAD(&dc->list);
1359 dc->dev = &pdev->dev;
1362 err = tegra_dc_parse_dt(dc);
1366 dc->clk = devm_clk_get(&pdev->dev, NULL);
1367 if (IS_ERR(dc->clk)) {
1368 dev_err(&pdev->dev, "failed to get clock\n");
1369 return PTR_ERR(dc->clk);
1372 dc->rst = devm_reset_control_get(&pdev->dev, "dc");
1373 if (IS_ERR(dc->rst)) {
1374 dev_err(&pdev->dev, "failed to get reset\n");
1375 return PTR_ERR(dc->rst);
1378 err = clk_prepare_enable(dc->clk);
1382 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1383 dc->regs = devm_ioremap_resource(&pdev->dev, regs);
1384 if (IS_ERR(dc->regs))
1385 return PTR_ERR(dc->regs);
1387 dc->irq = platform_get_irq(pdev, 0);
1389 dev_err(&pdev->dev, "failed to get IRQ\n");
1393 INIT_LIST_HEAD(&dc->client.list);
1394 dc->client.ops = &dc_client_ops;
1395 dc->client.dev = &pdev->dev;
1397 err = tegra_dc_rgb_probe(dc);
1398 if (err < 0 && err != -ENODEV) {
1399 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
1403 err = host1x_client_register(&dc->client);
1405 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1410 platform_set_drvdata(pdev, dc);
1415 static int tegra_dc_remove(struct platform_device *pdev)
1417 struct tegra_dc *dc = platform_get_drvdata(pdev);
1420 err = host1x_client_unregister(&dc->client);
1422 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1427 err = tegra_dc_rgb_remove(dc);
1429 dev_err(&pdev->dev, "failed to remove RGB output: %d\n", err);
1433 clk_disable_unprepare(dc->clk);
1438 struct platform_driver tegra_dc_driver = {
1441 .owner = THIS_MODULE,
1442 .of_match_table = tegra_dc_of_match,
1444 .probe = tegra_dc_probe,
1445 .remove = tegra_dc_remove,