drivers/gpu/drm/tegra/dc.c

   1 /*
   2  * Copyright (C) 2012 Avionic Design GmbH
   3  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 as
   7  * published by the Free Software Foundation.
   8  */
   9
  10 #include <linux/clk.h>
  11 #include <linux/debugfs.h>
  12 #include <linux/module.h>
  13 #include <linux/of.h>
  14 #include <linux/platform_device.h>
  15
  16 #include <mach/clk.h>
  17
  18 #include "drm.h"
  19 #include "dc.h"
  20
  21 struct tegra_dc_window {
  22         fixed20_12 x;
  23         fixed20_12 y;
  24         fixed20_12 w;
  25         fixed20_12 h;
  26         unsigned int outx;
  27         unsigned int outy;
  28         unsigned int outw;
  29         unsigned int outh;
  30         unsigned int stride;
  31         unsigned int fmt;
  32 };
  33
  34 static const struct drm_crtc_funcs tegra_crtc_funcs = {
  35         .set_config = drm_crtc_helper_set_config,
  36         .destroy = drm_crtc_cleanup,
  37 };
  38
  39 static void tegra_crtc_dpms(struct drm_crtc *crtc, int mode)
  40 {
  41 }
  42
  43 static bool tegra_crtc_mode_fixup(struct drm_crtc *crtc,
  44                                   const struct drm_display_mode *mode,
  45                                   struct drm_display_mode *adjusted)
  46 {
  47         return true;
  48 }
  49
  50 static inline u32 compute_dda_inc(fixed20_12 inf, unsigned int out, bool v,
  51                                   unsigned int bpp)
  52 {
  53         fixed20_12 outf = dfixed_init(out);
  54         u32 dda_inc;
  55         int max;
  56
  57         if (v)
  58                 max = 15;
  59         else {
  60                 switch (bpp) {
  61                 case 2:
  62                         max = 8;
  63                         break;
  64
  65                 default:
  66                         WARN_ON_ONCE(1);
  67                         /* fallthrough */
  68                 case 4:
  69                         max = 4;
  70                         break;
  71                 }
  72         }
  73
  74         outf.full = max_t(u32, outf.full - dfixed_const(1), dfixed_const(1));
  75         inf.full -= dfixed_const(1);
  76
  77         dda_inc = dfixed_div(inf, outf);
  78         dda_inc = min_t(u32, dda_inc, dfixed_const(max));
  79
  80         return dda_inc;
  81 }
  82
  83 static inline u32 compute_initial_dda(fixed20_12 in)
  84 {
  85         return dfixed_frac(in);
  86 }
  87
  88 static int tegra_dc_set_timings(struct tegra_dc *dc,
  89                                 struct drm_display_mode *mode)
  90 {
  91         /* TODO: For HDMI compliance, h & v ref_to_sync should be set to 1 */
  92         unsigned int h_ref_to_sync = 0;
  93         unsigned int v_ref_to_sync = 0;
  94         unsigned long value;
  95
  96         tegra_dc_writel(dc, 0x0, DC_DISP_DISP_TIMING_OPTIONS);
  97
  98         value = (v_ref_to_sync << 16) | h_ref_to_sync;
  99         tegra_dc_writel(dc, value, DC_DISP_REF_TO_SYNC);
 100
 101         value = ((mode->vsync_end - mode->vsync_start) << 16) |
 102                 ((mode->hsync_end - mode->hsync_start) <<  0);
 103         tegra_dc_writel(dc, value, DC_DISP_SYNC_WIDTH);
 104
 105         value = ((mode->vtotal - mode->vsync_end) << 16) |
 106                 ((mode->htotal - mode->hsync_end) <<  0);
 107         tegra_dc_writel(dc, value, DC_DISP_BACK_PORCH);
 108
 109         value = ((mode->vsync_start - mode->vdisplay) << 16) |
 110                 ((mode->hsync_start - mode->hdisplay) <<  0);
 111         tegra_dc_writel(dc, value, DC_DISP_FRONT_PORCH);
 112
 113         value = (mode->vdisplay << 16) | mode->hdisplay;
 114         tegra_dc_writel(dc, value, DC_DISP_ACTIVE);
 115
 116         return 0;
 117 }
 118
 119 static int tegra_crtc_setup_clk(struct drm_crtc *crtc,
 120                                 struct drm_display_mode *mode,
 121                                 unsigned long *div)
 122 {
 123         unsigned long pclk = mode->clock * 1000, rate;
 124         struct tegra_dc *dc = to_tegra_dc(crtc);
 125         struct tegra_output *output = NULL;
 126         struct drm_encoder *encoder;
 127         long err;
 128
 129         list_for_each_entry(encoder, &crtc->dev->mode_config.encoder_list, head)
 130                 if (encoder->crtc == crtc) {
 131                         output = encoder_to_output(encoder);
 132                         break;
 133                 }
 134
 135         if (!output)
 136                 return -ENODEV;
 137
 138         /*
 139          * This assumes that the display controller will divide its parent
 140          * clock by 2 to generate the pixel clock.
 141          */
 142         err = tegra_output_setup_clock(output, dc->clk, pclk * 2);
 143         if (err < 0) {
 144                 dev_err(dc->dev, "failed to setup clock: %ld\n", err);
 145                 return err;
 146         }
 147
 148         rate = clk_get_rate(dc->clk);
 149         *div = (rate * 2 / pclk) - 2;
 150
 151         DRM_DEBUG_KMS("rate: %lu, div: %lu\n", rate, *div);
 152
 153         return 0;
 154 }
 155
 156 static int tegra_crtc_mode_set(struct drm_crtc *crtc,
 157                                struct drm_display_mode *mode,
 158                                struct drm_display_mode *adjusted,
 159                                int x, int y, struct drm_framebuffer *old_fb)
 160 {
 161         struct tegra_framebuffer *fb = to_tegra_fb(crtc->fb);
 162         struct tegra_dc *dc = to_tegra_dc(crtc);
 163         unsigned int h_dda, v_dda, bpp;
 164         struct tegra_dc_window win;
 165         unsigned long div, value;
 166         int err;
 167
 168         err = tegra_crtc_setup_clk(crtc, mode, &div);
 169         if (err) {
 170                 dev_err(dc->dev, "failed to setup clock for CRTC: %d\n", err);
 171                 return err;
 172         }
 173
 174         mutex_lock(&dc->regs_mutex);
 175
 176         /* program display mode */
 177         tegra_dc_set_timings(dc, mode);
 178
 179         value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
 180         tegra_dc_writel(dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
 181
 182         value = tegra_dc_readl(dc, DC_COM_PIN_OUTPUT_POLARITY(1));
 183         value &= ~LVS_OUTPUT_POLARITY_LOW;
 184         value &= ~LHS_OUTPUT_POLARITY_LOW;
 185         tegra_dc_writel(dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
 186
 187         value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB |
 188                 DISP_ORDER_RED_BLUE;
 189         tegra_dc_writel(dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
 190
 191         tegra_dc_writel(dc, 0x00010001, DC_DISP_SHIFT_CLOCK_OPTIONS);
 192
 193         value = SHIFT_CLK_DIVIDER(div) | PIXEL_CLK_DIVIDER_PCD1;
 194         tegra_dc_writel(dc, value, DC_DISP_DISP_CLOCK_CONTROL);
 195
 196         /* setup window parameters */
 197         memset(&win, 0, sizeof(win));
 198         win.x.full = dfixed_const(0);
 199         win.y.full = dfixed_const(0);
 200         win.w.full = dfixed_const(mode->hdisplay);
 201         win.h.full = dfixed_const(mode->vdisplay);
 202         win.outx = 0;
 203         win.outy = 0;
 204         win.outw = mode->hdisplay;
 205         win.outh = mode->vdisplay;
 206
 207         switch (crtc->fb->pixel_format) {
 208         case DRM_FORMAT_XRGB8888:
 209                 win.fmt = WIN_COLOR_DEPTH_B8G8R8A8;
 210                 break;
 211
 212         case DRM_FORMAT_RGB565:
 213                 win.fmt = WIN_COLOR_DEPTH_B5G6R5;
 214                 break;
 215
 216         default:
 217                 win.fmt = WIN_COLOR_DEPTH_B8G8R8A8;
 218                 WARN_ON(1);
 219                 break;
 220         }
 221
 222         bpp = crtc->fb->bits_per_pixel / 8;
 223         win.stride = crtc->fb->pitches[0];
 224
 225         /* program window registers */
 226         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_WINDOW_HEADER);
 227         value |= WINDOW_A_SELECT;
 228         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_WINDOW_HEADER);
 229
 230         tegra_dc_writel(dc, win.fmt, DC_WIN_COLOR_DEPTH);
 231         tegra_dc_writel(dc, 0, DC_WIN_BYTE_SWAP);
 232
 233         value = V_POSITION(win.outy) | H_POSITION(win.outx);
 234         tegra_dc_writel(dc, value, DC_WIN_POSITION);
 235
 236         value = V_SIZE(win.outh) | H_SIZE(win.outw);
 237         tegra_dc_writel(dc, value, DC_WIN_SIZE);
 238
 239         value = V_PRESCALED_SIZE(dfixed_trunc(win.h)) |
 240                 H_PRESCALED_SIZE(dfixed_trunc(win.w) * bpp);
 241         tegra_dc_writel(dc, value, DC_WIN_PRESCALED_SIZE);
 242
 243         h_dda = compute_dda_inc(win.w, win.outw, false, bpp);
 244         v_dda = compute_dda_inc(win.h, win.outh, true, bpp);
 245
 246         value = V_DDA_INC(v_dda) | H_DDA_INC(h_dda);
 247         tegra_dc_writel(dc, value, DC_WIN_DDA_INC);
 248
 249         h_dda = compute_initial_dda(win.x);
 250         v_dda = compute_initial_dda(win.y);
 251
 252         tegra_dc_writel(dc, h_dda, DC_WIN_H_INITIAL_DDA);
 253         tegra_dc_writel(dc, v_dda, DC_WIN_V_INITIAL_DDA);
 254
 255         tegra_dc_writel(dc, 0, DC_WIN_UV_BUF_STRIDE);
 256         tegra_dc_writel(dc, 0, DC_WIN_BUF_STRIDE);
 257
 258         tegra_dc_writel(dc, fb->obj->paddr, DC_WINBUF_START_ADDR);
 259         tegra_dc_writel(dc, win.stride, DC_WIN_LINE_STRIDE);
 260         tegra_dc_writel(dc, dfixed_trunc(win.x) * bpp,
 261                         DC_WINBUF_ADDR_H_OFFSET);
 262         tegra_dc_writel(dc, dfixed_trunc(win.y), DC_WINBUF_ADDR_V_OFFSET);
 263
 264         value = WIN_ENABLE;
 265
 266         if (bpp < 24)
 267                 value |= COLOR_EXPAND;
 268
 269         tegra_dc_writel(dc, value, DC_WIN_WIN_OPTIONS);
 270
 271         tegra_dc_writel(dc, 0xff00, DC_WIN_BLEND_NOKEY);
 272         tegra_dc_writel(dc, 0xff00, DC_WIN_BLEND_1WIN);
 273
 274         mutex_unlock(&dc->regs_mutex);
 275
 276         return 0;
 277 }
 278
 279 static void tegra_crtc_prepare(struct drm_crtc *crtc)
 280 {
 281         struct tegra_dc *dc = to_tegra_dc(crtc);
 282         unsigned int syncpt;
 283         unsigned long value;
 284
 285         /* hardware initialization */
 286         tegra_periph_reset_deassert(dc->clk);
 287         usleep_range(10000, 20000);
 288
 289         if (dc->pipe)
 290                 syncpt = SYNCPT_VBLANK1;
 291         else
 292                 syncpt = SYNCPT_VBLANK0;
 293
 294         mutex_lock(&dc->regs_mutex);
 295
 296         /* initialize display controller */
 297         tegra_dc_writel(dc, 0x00000100, DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
 298         tegra_dc_writel(dc, 0x100 | syncpt, DC_CMD_CONT_SYNCPT_VSYNC);
 299
 300         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT | WIN_A_OF_INT;
 301         tegra_dc_writel(dc, value, DC_CMD_INT_TYPE);
 302
 303         value = WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT |
 304                 WIN_A_OF_INT | WIN_B_OF_INT | WIN_C_OF_INT;
 305         tegra_dc_writel(dc, value, DC_CMD_INT_POLARITY);
 306
 307         value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
 308                 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
 309         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
 310
 311         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
 312         value |= DISP_CTRL_MODE_C_DISPLAY;
 313         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
 314
 315         /* initialize timer */
 316         value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(0x20) |
 317                 WINDOW_B_THRESHOLD(0x20) | WINDOW_C_THRESHOLD(0x20);
 318         tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY);
 319
 320         value = CURSOR_THRESHOLD(0) | WINDOW_A_THRESHOLD(1) |
 321                 WINDOW_B_THRESHOLD(1) | WINDOW_C_THRESHOLD(1);
 322         tegra_dc_writel(dc, value, DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
 323
 324         value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
 325         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
 326
 327         value = VBLANK_INT | WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT;
 328         tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
 329
 330         mutex_unlock(&dc->regs_mutex);
 331 }
 332
 333 static void tegra_crtc_commit(struct drm_crtc *crtc)
 334 {
 335         struct tegra_dc *dc = to_tegra_dc(crtc);
 336         unsigned long update_mask;
 337         unsigned long value;
 338
 339         update_mask = GENERAL_ACT_REQ | WIN_A_ACT_REQ;
 340
 341         mutex_lock(&dc->regs_mutex);
 342
 343         tegra_dc_writel(dc, update_mask << 8, DC_CMD_STATE_CONTROL);
 344
 345         value = tegra_dc_readl(dc, DC_CMD_INT_ENABLE);
 346         value |= FRAME_END_INT;
 347         tegra_dc_writel(dc, value, DC_CMD_INT_ENABLE);
 348
 349         value = tegra_dc_readl(dc, DC_CMD_INT_MASK);
 350         value |= FRAME_END_INT;
 351         tegra_dc_writel(dc, value, DC_CMD_INT_MASK);
 352
 353         tegra_dc_writel(dc, update_mask, DC_CMD_STATE_CONTROL);
 354
 355         mutex_unlock(&dc->regs_mutex);
 356 }
 357
 358 static void tegra_crtc_load_lut(struct drm_crtc *crtc)
 359 {
 360 }
 361
 362 static const struct drm_crtc_helper_funcs tegra_crtc_helper_funcs = {
 363         .dpms = tegra_crtc_dpms,
 364         .mode_fixup = tegra_crtc_mode_fixup,
 365         .mode_set = tegra_crtc_mode_set,
 366         .prepare = tegra_crtc_prepare,
 367         .commit = tegra_crtc_commit,
 368         .load_lut = tegra_crtc_load_lut,
 369 };
 370
 371 static irqreturn_t tegra_drm_irq(int irq, void *data)
 372 {
 373         struct tegra_dc *dc = data;
 374         unsigned long status;
 375
 376         status = tegra_dc_readl(dc, DC_CMD_INT_STATUS);
 377         tegra_dc_writel(dc, status, DC_CMD_INT_STATUS);
 378
 379         if (status & FRAME_END_INT) {
 380                 /*
 381                 dev_dbg(dc->dev, "%s(): frame end\n", __func__);
 382                 */
 383         }
 384
 385         if (status & VBLANK_INT) {
 386                 /*
 387                 dev_dbg(dc->dev, "%s(): vertical blank\n", __func__);
 388                 */
 389                 drm_handle_vblank(dc->base.dev, dc->pipe);
 390         }
 391
 392         if (status & (WIN_A_UF_INT | WIN_B_UF_INT | WIN_C_UF_INT)) {
 393                 /*
 394                 dev_dbg(dc->dev, "%s(): underflow\n", __func__);
 395                 */
 396         }
 397
 398         return IRQ_HANDLED;
 399 }
 400
 401 static int tegra_dc_show_regs(struct seq_file *s, void *data)
 402 {
 403         struct drm_info_node *node = s->private;
 404         struct tegra_dc *dc = node->info_ent->data;
 405
 406 #define DUMP_REG(name)                                          \
 407         seq_printf(s, "%-40s %#05x %08lx\n", #name, name,       \
 408                    tegra_dc_readl(dc, name))
 409
 410         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT);
 411         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_CNTRL);
 412         DUMP_REG(DC_CMD_GENERAL_INCR_SYNCPT_ERROR);
 413         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT);
 414         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_CNTRL);
 415         DUMP_REG(DC_CMD_WIN_A_INCR_SYNCPT_ERROR);
 416         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT);
 417         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_CNTRL);
 418         DUMP_REG(DC_CMD_WIN_B_INCR_SYNCPT_ERROR);
 419         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT);
 420         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_CNTRL);
 421         DUMP_REG(DC_CMD_WIN_C_INCR_SYNCPT_ERROR);
 422         DUMP_REG(DC_CMD_CONT_SYNCPT_VSYNC);
 423         DUMP_REG(DC_CMD_DISPLAY_COMMAND_OPTION0);
 424         DUMP_REG(DC_CMD_DISPLAY_COMMAND);
 425         DUMP_REG(DC_CMD_SIGNAL_RAISE);
 426         DUMP_REG(DC_CMD_DISPLAY_POWER_CONTROL);
 427         DUMP_REG(DC_CMD_INT_STATUS);
 428         DUMP_REG(DC_CMD_INT_MASK);
 429         DUMP_REG(DC_CMD_INT_ENABLE);
 430         DUMP_REG(DC_CMD_INT_TYPE);
 431         DUMP_REG(DC_CMD_INT_POLARITY);
 432         DUMP_REG(DC_CMD_SIGNAL_RAISE1);
 433         DUMP_REG(DC_CMD_SIGNAL_RAISE2);
 434         DUMP_REG(DC_CMD_SIGNAL_RAISE3);
 435         DUMP_REG(DC_CMD_STATE_ACCESS);
 436         DUMP_REG(DC_CMD_STATE_CONTROL);
 437         DUMP_REG(DC_CMD_DISPLAY_WINDOW_HEADER);
 438         DUMP_REG(DC_CMD_REG_ACT_CONTROL);
 439         DUMP_REG(DC_COM_CRC_CONTROL);
 440         DUMP_REG(DC_COM_CRC_CHECKSUM);
 441         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(0));
 442         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(1));
 443         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(2));
 444         DUMP_REG(DC_COM_PIN_OUTPUT_ENABLE(3));
 445         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(0));
 446         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(1));
 447         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(2));
 448         DUMP_REG(DC_COM_PIN_OUTPUT_POLARITY(3));
 449         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(0));
 450         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(1));
 451         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(2));
 452         DUMP_REG(DC_COM_PIN_OUTPUT_DATA(3));
 453         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(0));
 454         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(1));
 455         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(2));
 456         DUMP_REG(DC_COM_PIN_INPUT_ENABLE(3));
 457         DUMP_REG(DC_COM_PIN_INPUT_DATA(0));
 458         DUMP_REG(DC_COM_PIN_INPUT_DATA(1));
 459         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(0));
 460         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(1));
 461         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(2));
 462         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(3));
 463         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(4));
 464         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(5));
 465         DUMP_REG(DC_COM_PIN_OUTPUT_SELECT(6));
 466         DUMP_REG(DC_COM_PIN_MISC_CONTROL);
 467         DUMP_REG(DC_COM_PIN_PM0_CONTROL);
 468         DUMP_REG(DC_COM_PIN_PM0_DUTY_CYCLE);
 469         DUMP_REG(DC_COM_PIN_PM1_CONTROL);
 470         DUMP_REG(DC_COM_PIN_PM1_DUTY_CYCLE);
 471         DUMP_REG(DC_COM_SPI_CONTROL);
 472         DUMP_REG(DC_COM_SPI_START_BYTE);
 473         DUMP_REG(DC_COM_HSPI_WRITE_DATA_AB);
 474         DUMP_REG(DC_COM_HSPI_WRITE_DATA_CD);
 475         DUMP_REG(DC_COM_HSPI_CS_DC);
 476         DUMP_REG(DC_COM_SCRATCH_REGISTER_A);
 477         DUMP_REG(DC_COM_SCRATCH_REGISTER_B);
 478         DUMP_REG(DC_COM_GPIO_CTRL);
 479         DUMP_REG(DC_COM_GPIO_DEBOUNCE_COUNTER);
 480         DUMP_REG(DC_COM_CRC_CHECKSUM_LATCHED);
 481         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS0);
 482         DUMP_REG(DC_DISP_DISP_SIGNAL_OPTIONS1);
 483         DUMP_REG(DC_DISP_DISP_WIN_OPTIONS);
 484         DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY);
 485         DUMP_REG(DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER);
 486         DUMP_REG(DC_DISP_DISP_TIMING_OPTIONS);
 487         DUMP_REG(DC_DISP_REF_TO_SYNC);
 488         DUMP_REG(DC_DISP_SYNC_WIDTH);
 489         DUMP_REG(DC_DISP_BACK_PORCH);
 490         DUMP_REG(DC_DISP_ACTIVE);
 491         DUMP_REG(DC_DISP_FRONT_PORCH);
 492         DUMP_REG(DC_DISP_H_PULSE0_CONTROL);
 493         DUMP_REG(DC_DISP_H_PULSE0_POSITION_A);
 494         DUMP_REG(DC_DISP_H_PULSE0_POSITION_B);
 495         DUMP_REG(DC_DISP_H_PULSE0_POSITION_C);
 496         DUMP_REG(DC_DISP_H_PULSE0_POSITION_D);
 497         DUMP_REG(DC_DISP_H_PULSE1_CONTROL);
 498         DUMP_REG(DC_DISP_H_PULSE1_POSITION_A);
 499         DUMP_REG(DC_DISP_H_PULSE1_POSITION_B);
 500         DUMP_REG(DC_DISP_H_PULSE1_POSITION_C);
 501         DUMP_REG(DC_DISP_H_PULSE1_POSITION_D);
 502         DUMP_REG(DC_DISP_H_PULSE2_CONTROL);
 503         DUMP_REG(DC_DISP_H_PULSE2_POSITION_A);
 504         DUMP_REG(DC_DISP_H_PULSE2_POSITION_B);
 505         DUMP_REG(DC_DISP_H_PULSE2_POSITION_C);
 506         DUMP_REG(DC_DISP_H_PULSE2_POSITION_D);
 507         DUMP_REG(DC_DISP_V_PULSE0_CONTROL);
 508         DUMP_REG(DC_DISP_V_PULSE0_POSITION_A);
 509         DUMP_REG(DC_DISP_V_PULSE0_POSITION_B);
 510         DUMP_REG(DC_DISP_V_PULSE0_POSITION_C);
 511         DUMP_REG(DC_DISP_V_PULSE1_CONTROL);
 512         DUMP_REG(DC_DISP_V_PULSE1_POSITION_A);
 513         DUMP_REG(DC_DISP_V_PULSE1_POSITION_B);
 514         DUMP_REG(DC_DISP_V_PULSE1_POSITION_C);
 515         DUMP_REG(DC_DISP_V_PULSE2_CONTROL);
 516         DUMP_REG(DC_DISP_V_PULSE2_POSITION_A);
 517         DUMP_REG(DC_DISP_V_PULSE3_CONTROL);
 518         DUMP_REG(DC_DISP_V_PULSE3_POSITION_A);
 519         DUMP_REG(DC_DISP_M0_CONTROL);
 520         DUMP_REG(DC_DISP_M1_CONTROL);
 521         DUMP_REG(DC_DISP_DI_CONTROL);
 522         DUMP_REG(DC_DISP_PP_CONTROL);
 523         DUMP_REG(DC_DISP_PP_SELECT_A);
 524         DUMP_REG(DC_DISP_PP_SELECT_B);
 525         DUMP_REG(DC_DISP_PP_SELECT_C);
 526         DUMP_REG(DC_DISP_PP_SELECT_D);
 527         DUMP_REG(DC_DISP_DISP_CLOCK_CONTROL);
 528         DUMP_REG(DC_DISP_DISP_INTERFACE_CONTROL);
 529         DUMP_REG(DC_DISP_DISP_COLOR_CONTROL);
 530         DUMP_REG(DC_DISP_SHIFT_CLOCK_OPTIONS);
 531         DUMP_REG(DC_DISP_DATA_ENABLE_OPTIONS);
 532         DUMP_REG(DC_DISP_SERIAL_INTERFACE_OPTIONS);
 533         DUMP_REG(DC_DISP_LCD_SPI_OPTIONS);
 534         DUMP_REG(DC_DISP_BORDER_COLOR);
 535         DUMP_REG(DC_DISP_COLOR_KEY0_LOWER);
 536         DUMP_REG(DC_DISP_COLOR_KEY0_UPPER);
 537         DUMP_REG(DC_DISP_COLOR_KEY1_LOWER);
 538         DUMP_REG(DC_DISP_COLOR_KEY1_UPPER);
 539         DUMP_REG(DC_DISP_CURSOR_FOREGROUND);
 540         DUMP_REG(DC_DISP_CURSOR_BACKGROUND);
 541         DUMP_REG(DC_DISP_CURSOR_START_ADDR);
 542         DUMP_REG(DC_DISP_CURSOR_START_ADDR_NS);
 543         DUMP_REG(DC_DISP_CURSOR_POSITION);
 544         DUMP_REG(DC_DISP_CURSOR_POSITION_NS);
 545         DUMP_REG(DC_DISP_INIT_SEQ_CONTROL);
 546         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_A);
 547         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_B);
 548         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_C);
 549         DUMP_REG(DC_DISP_SPI_INIT_SEQ_DATA_D);
 550         DUMP_REG(DC_DISP_DC_MCCIF_FIFOCTRL);
 551         DUMP_REG(DC_DISP_MCCIF_DISPLAY0A_HYST);
 552         DUMP_REG(DC_DISP_MCCIF_DISPLAY0B_HYST);
 553         DUMP_REG(DC_DISP_MCCIF_DISPLAY1A_HYST);
 554         DUMP_REG(DC_DISP_MCCIF_DISPLAY1B_HYST);
 555         DUMP_REG(DC_DISP_DAC_CRT_CTRL);
 556         DUMP_REG(DC_DISP_DISP_MISC_CONTROL);
 557         DUMP_REG(DC_DISP_SD_CONTROL);
 558         DUMP_REG(DC_DISP_SD_CSC_COEFF);
 559         DUMP_REG(DC_DISP_SD_LUT(0));
 560         DUMP_REG(DC_DISP_SD_LUT(1));
 561         DUMP_REG(DC_DISP_SD_LUT(2));
 562         DUMP_REG(DC_DISP_SD_LUT(3));
 563         DUMP_REG(DC_DISP_SD_LUT(4));
 564         DUMP_REG(DC_DISP_SD_LUT(5));
 565         DUMP_REG(DC_DISP_SD_LUT(6));
 566         DUMP_REG(DC_DISP_SD_LUT(7));
 567         DUMP_REG(DC_DISP_SD_LUT(8));
 568         DUMP_REG(DC_DISP_SD_FLICKER_CONTROL);
 569         DUMP_REG(DC_DISP_DC_PIXEL_COUNT);
 570         DUMP_REG(DC_DISP_SD_HISTOGRAM(0));
 571         DUMP_REG(DC_DISP_SD_HISTOGRAM(1));
 572         DUMP_REG(DC_DISP_SD_HISTOGRAM(2));
 573         DUMP_REG(DC_DISP_SD_HISTOGRAM(3));
 574         DUMP_REG(DC_DISP_SD_HISTOGRAM(4));
 575         DUMP_REG(DC_DISP_SD_HISTOGRAM(5));
 576         DUMP_REG(DC_DISP_SD_HISTOGRAM(6));
 577         DUMP_REG(DC_DISP_SD_HISTOGRAM(7));
 578         DUMP_REG(DC_DISP_SD_BL_TF(0));
 579         DUMP_REG(DC_DISP_SD_BL_TF(1));
 580         DUMP_REG(DC_DISP_SD_BL_TF(2));
 581         DUMP_REG(DC_DISP_SD_BL_TF(3));
 582         DUMP_REG(DC_DISP_SD_BL_CONTROL);
 583         DUMP_REG(DC_DISP_SD_HW_K_VALUES);
 584         DUMP_REG(DC_DISP_SD_MAN_K_VALUES);
 585         DUMP_REG(DC_WIN_WIN_OPTIONS);
 586         DUMP_REG(DC_WIN_BYTE_SWAP);
 587         DUMP_REG(DC_WIN_BUFFER_CONTROL);
 588         DUMP_REG(DC_WIN_COLOR_DEPTH);
 589         DUMP_REG(DC_WIN_POSITION);
 590         DUMP_REG(DC_WIN_SIZE);
 591         DUMP_REG(DC_WIN_PRESCALED_SIZE);
 592         DUMP_REG(DC_WIN_H_INITIAL_DDA);
 593         DUMP_REG(DC_WIN_V_INITIAL_DDA);
 594         DUMP_REG(DC_WIN_DDA_INC);
 595         DUMP_REG(DC_WIN_LINE_STRIDE);
 596         DUMP_REG(DC_WIN_BUF_STRIDE);
 597         DUMP_REG(DC_WIN_UV_BUF_STRIDE);
 598         DUMP_REG(DC_WIN_BUFFER_ADDR_MODE);
 599         DUMP_REG(DC_WIN_DV_CONTROL);
 600         DUMP_REG(DC_WIN_BLEND_NOKEY);
 601         DUMP_REG(DC_WIN_BLEND_1WIN);
 602         DUMP_REG(DC_WIN_BLEND_2WIN_X);
 603         DUMP_REG(DC_WIN_BLEND_2WIN_Y);
 604         DUMP_REG(DC_WIN_BLEND32WIN_XY);
 605         DUMP_REG(DC_WIN_HP_FETCH_CONTROL);
 606         DUMP_REG(DC_WINBUF_START_ADDR);
 607         DUMP_REG(DC_WINBUF_START_ADDR_NS);
 608         DUMP_REG(DC_WINBUF_START_ADDR_U);
 609         DUMP_REG(DC_WINBUF_START_ADDR_U_NS);
 610         DUMP_REG(DC_WINBUF_START_ADDR_V);
 611         DUMP_REG(DC_WINBUF_START_ADDR_V_NS);
 612         DUMP_REG(DC_WINBUF_ADDR_H_OFFSET);
 613         DUMP_REG(DC_WINBUF_ADDR_H_OFFSET_NS);
 614         DUMP_REG(DC_WINBUF_ADDR_V_OFFSET);
 615         DUMP_REG(DC_WINBUF_ADDR_V_OFFSET_NS);
 616         DUMP_REG(DC_WINBUF_UFLOW_STATUS);
 617         DUMP_REG(DC_WINBUF_AD_UFLOW_STATUS);
 618         DUMP_REG(DC_WINBUF_BD_UFLOW_STATUS);
 619         DUMP_REG(DC_WINBUF_CD_UFLOW_STATUS);
 620
 621 #undef DUMP_REG
 622
 623         return 0;
 624 }
 625
 626 static struct drm_info_list debugfs_files[] = {
 627         { "regs", tegra_dc_show_regs, 0, NULL },
 628 };
 629
 630 static int tegra_dc_debugfs_init(struct tegra_dc *dc, struct drm_minor *minor)
 631 {
 632         unsigned int i;
 633         char *name;
 634         int err;
 635
 636         name = kasprintf(GFP_KERNEL, "dc.%d", dc->pipe);
 637         dc->debugfs = debugfs_create_dir(name, minor->debugfs_root);
 638         kfree(name);
 639
 640         if (!dc->debugfs)
 641                 return -ENOMEM;
 642
 643         dc->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
 644                                     GFP_KERNEL);
 645         if (!dc->debugfs_files) {
 646                 err = -ENOMEM;
 647                 goto remove;
 648         }
 649
 650         for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
 651                 dc->debugfs_files[i].data = dc;
 652
 653         err = drm_debugfs_create_files(dc->debugfs_files,
 654                                        ARRAY_SIZE(debugfs_files),
 655                                        dc->debugfs, minor);
 656         if (err < 0)
 657                 goto free;
 658
 659         dc->minor = minor;
 660
 661         return 0;
 662
 663 free:
 664         kfree(dc->debugfs_files);
 665         dc->debugfs_files = NULL;
 666 remove:
 667         debugfs_remove(dc->debugfs);
 668         dc->debugfs = NULL;
 669
 670         return err;
 671 }
 672
 673 static int tegra_dc_debugfs_exit(struct tegra_dc *dc)
 674 {
 675         drm_debugfs_remove_files(dc->debugfs_files, ARRAY_SIZE(debugfs_files),
 676                                  dc->minor);
 677         dc->minor = NULL;
 678
 679         kfree(dc->debugfs_files);
 680         dc->debugfs_files = NULL;
 681
 682         debugfs_remove(dc->debugfs);
 683         dc->debugfs = NULL;
 684
 685         return 0;
 686 }
 687
 688 static int tegra_dc_drm_init(struct host1x_client *client,
 689                              struct drm_device *drm)
 690 {
 691         struct tegra_dc *dc = host1x_client_to_dc(client);
 692         int err;
 693
 694         dc->pipe = drm->mode_config.num_crtc;
 695
 696         drm_crtc_init(drm, &dc->base, &tegra_crtc_funcs);
 697         drm_mode_crtc_set_gamma_size(&dc->base, 256);
 698         drm_crtc_helper_add(&dc->base, &tegra_crtc_helper_funcs);
 699
 700         err = tegra_dc_rgb_init(drm, dc);
 701         if (err < 0 && err != -ENODEV) {
 702                 dev_err(dc->dev, "failed to initialize RGB output: %d\n", err);
 703                 return err;
 704         }
 705
 706         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
 707                 err = tegra_dc_debugfs_init(dc, drm->primary);
 708                 if (err < 0)
 709                         dev_err(dc->dev, "debugfs setup failed: %d\n", err);
 710         }
 711
 712         err = devm_request_irq(dc->dev, dc->irq, tegra_drm_irq, 0,
 713                                dev_name(dc->dev), dc);
 714         if (err < 0) {
 715                 dev_err(dc->dev, "failed to request IRQ#%u: %d\n", dc->irq,
 716                         err);
 717                 return err;
 718         }
 719
 720         return 0;
 721 }
 722
 723 static int tegra_dc_drm_exit(struct host1x_client *client)
 724 {
 725         struct tegra_dc *dc = host1x_client_to_dc(client);
 726         int err;
 727
 728         devm_free_irq(dc->dev, dc->irq, dc);
 729
 730         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
 731                 err = tegra_dc_debugfs_exit(dc);
 732                 if (err < 0)
 733                         dev_err(dc->dev, "debugfs cleanup failed: %d\n", err);
 734         }
 735
 736         err = tegra_dc_rgb_exit(dc);
 737         if (err) {
 738                 dev_err(dc->dev, "failed to shutdown RGB output: %d\n", err);
 739                 return err;
 740         }
 741
 742         return 0;
 743 }
 744
 745 static const struct host1x_client_ops dc_client_ops = {
 746         .drm_init = tegra_dc_drm_init,
 747         .drm_exit = tegra_dc_drm_exit,
 748 };
 749
 750 static int tegra_dc_probe(struct platform_device *pdev)
 751 {
 752         struct host1x *host1x = dev_get_drvdata(pdev->dev.parent);
 753         struct resource *regs;
 754         struct tegra_dc *dc;
 755         int err;
 756
 757         dc = devm_kzalloc(&pdev->dev, sizeof(*dc), GFP_KERNEL);
 758         if (!dc)
 759                 return -ENOMEM;
 760
 761         INIT_LIST_HEAD(&dc->list);
 762         mutex_init(&dc->regs_mutex);
 763         dc->dev = &pdev->dev;
 764
 765         dc->clk = devm_clk_get(&pdev->dev, NULL);
 766         if (IS_ERR(dc->clk)) {
 767                 dev_err(&pdev->dev, "failed to get clock\n");
 768                 return PTR_ERR(dc->clk);
 769         }
 770
 771         err = clk_prepare_enable(dc->clk);
 772         if (err < 0)
 773                 return err;
 774
 775         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 776         if (!regs) {
 777                 dev_err(&pdev->dev, "failed to get registers\n");
 778                 return -ENXIO;
 779         }
 780
 781         dc->regs = devm_request_and_ioremap(&pdev->dev, regs);
 782         if (!dc->regs) {
 783                 dev_err(&pdev->dev, "failed to remap registers\n");
 784                 return -ENXIO;
 785         }
 786
 787         dc->irq = platform_get_irq(pdev, 0);
 788         if (dc->irq < 0) {
 789                 dev_err(&pdev->dev, "failed to get IRQ\n");
 790                 return -ENXIO;
 791         }
 792
 793         INIT_LIST_HEAD(&dc->client.list);
 794         dc->client.ops = &dc_client_ops;
 795         dc->client.dev = &pdev->dev;
 796
 797         err = tegra_dc_rgb_probe(dc);
 798         if (err < 0 && err != -ENODEV) {
 799                 dev_err(&pdev->dev, "failed to probe RGB output: %d\n", err);
 800                 return err;
 801         }
 802
 803         err = host1x_register_client(host1x, &dc->client);
 804         if (err < 0) {
 805                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
 806                         err);
 807                 return err;
 808         }
 809
 810         platform_set_drvdata(pdev, dc);
 811
 812         return 0;
 813 }
 814
 815 static int tegra_dc_remove(struct platform_device *pdev)
 816 {
 817         struct host1x *host1x = dev_get_drvdata(pdev->dev.parent);
 818         struct tegra_dc *dc = platform_get_drvdata(pdev);
 819         int err;
 820
 821         err = host1x_unregister_client(host1x, &dc->client);
 822         if (err < 0) {
 823                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
 824                         err);
 825                 return err;
 826         }
 827
 828         clk_disable_unprepare(dc->clk);
 829
 830         return 0;
 831 }
 832
 833 static struct of_device_id tegra_dc_of_match[] = {
 834         { .compatible = "nvidia,tegra30-dc", },
 835         { .compatible = "nvidia,tegra20-dc", },
 836         { },
 837 };
 838
 839 struct platform_driver tegra_dc_driver = {
 840         .driver = {
 841                 .name = "tegra-dc",
 842                 .owner = THIS_MODULE,
 843                 .of_match_table = tegra_dc_of_match,
 844         },
 845         .probe = tegra_dc_probe,
 846         .remove = tegra_dc_remove,
 847 };