2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
13 #define DC_CMD_GENERAL_INCR_SYNCPT 0x000
14 #define DC_CMD_GENERAL_INCR_SYNCPT_CNTRL 0x001
15 #define SYNCPT_CNTRL_NO_STALL (1 << 8)
16 #define SYNCPT_CNTRL_SOFT_RESET (1 << 0)
17 #define DC_CMD_GENERAL_INCR_SYNCPT_ERROR 0x002
18 #define DC_CMD_WIN_A_INCR_SYNCPT 0x008
19 #define DC_CMD_WIN_A_INCR_SYNCPT_CNTRL 0x009
20 #define DC_CMD_WIN_A_INCR_SYNCPT_ERROR 0x00a
21 #define DC_CMD_WIN_B_INCR_SYNCPT 0x010
22 #define DC_CMD_WIN_B_INCR_SYNCPT_CNTRL 0x011
23 #define DC_CMD_WIN_B_INCR_SYNCPT_ERROR 0x012
24 #define DC_CMD_WIN_C_INCR_SYNCPT 0x018
25 #define DC_CMD_WIN_C_INCR_SYNCPT_CNTRL 0x019
26 #define DC_CMD_WIN_C_INCR_SYNCPT_ERROR 0x01a
27 #define DC_CMD_CONT_SYNCPT_VSYNC 0x028
28 #define SYNCPT_VSYNC_ENABLE (1 << 8)
29 #define DC_CMD_DISPLAY_COMMAND_OPTION0 0x031
30 #define DC_CMD_DISPLAY_COMMAND 0x032
31 #define DISP_CTRL_MODE_STOP (0 << 5)
32 #define DISP_CTRL_MODE_C_DISPLAY (1 << 5)
33 #define DISP_CTRL_MODE_NC_DISPLAY (2 << 5)
34 #define DISP_CTRL_MODE_MASK (3 << 5)
35 #define DC_CMD_SIGNAL_RAISE 0x033
36 #define DC_CMD_DISPLAY_POWER_CONTROL 0x036
37 #define PW0_ENABLE (1 << 0)
38 #define PW1_ENABLE (1 << 2)
39 #define PW2_ENABLE (1 << 4)
40 #define PW3_ENABLE (1 << 6)
41 #define PW4_ENABLE (1 << 8)
42 #define PM0_ENABLE (1 << 16)
43 #define PM1_ENABLE (1 << 18)
45 #define DC_CMD_INT_STATUS 0x037
46 #define DC_CMD_INT_MASK 0x038
47 #define DC_CMD_INT_ENABLE 0x039
48 #define DC_CMD_INT_TYPE 0x03a
49 #define DC_CMD_INT_POLARITY 0x03b
50 #define CTXSW_INT (1 << 0)
51 #define FRAME_END_INT (1 << 1)
52 #define VBLANK_INT (1 << 2)
53 #define WIN_A_UF_INT (1 << 8)
54 #define WIN_B_UF_INT (1 << 9)
55 #define WIN_C_UF_INT (1 << 10)
56 #define WIN_A_OF_INT (1 << 14)
57 #define WIN_B_OF_INT (1 << 15)
58 #define WIN_C_OF_INT (1 << 16)
60 #define DC_CMD_SIGNAL_RAISE1 0x03c
61 #define DC_CMD_SIGNAL_RAISE2 0x03d
62 #define DC_CMD_SIGNAL_RAISE3 0x03e
64 #define DC_CMD_STATE_ACCESS 0x040
65 #define READ_MUX (1 << 0)
66 #define WRITE_MUX (1 << 2)
68 #define DC_CMD_STATE_CONTROL 0x041
69 #define GENERAL_ACT_REQ (1 << 0)
70 #define WIN_A_ACT_REQ (1 << 1)
71 #define WIN_B_ACT_REQ (1 << 2)
72 #define WIN_C_ACT_REQ (1 << 3)
73 #define CURSOR_ACT_REQ (1 << 7)
74 #define GENERAL_UPDATE (1 << 8)
75 #define WIN_A_UPDATE (1 << 9)
76 #define WIN_B_UPDATE (1 << 10)
77 #define WIN_C_UPDATE (1 << 11)
78 #define CURSOR_UPDATE (1 << 15)
79 #define NC_HOST_TRIG (1 << 24)
81 #define DC_CMD_DISPLAY_WINDOW_HEADER 0x042
82 #define WINDOW_A_SELECT (1 << 4)
83 #define WINDOW_B_SELECT (1 << 5)
84 #define WINDOW_C_SELECT (1 << 6)
86 #define DC_CMD_REG_ACT_CONTROL 0x043
88 #define DC_COM_CRC_CONTROL 0x300
89 #define DC_COM_CRC_CHECKSUM 0x301
90 #define DC_COM_PIN_OUTPUT_ENABLE(x) (0x302 + (x))
91 #define DC_COM_PIN_OUTPUT_POLARITY(x) (0x306 + (x))
92 #define LVS_OUTPUT_POLARITY_LOW (1 << 28)
93 #define LHS_OUTPUT_POLARITY_LOW (1 << 30)
94 #define DC_COM_PIN_OUTPUT_DATA(x) (0x30a + (x))
95 #define DC_COM_PIN_INPUT_ENABLE(x) (0x30e + (x))
96 #define DC_COM_PIN_INPUT_DATA(x) (0x312 + (x))
97 #define DC_COM_PIN_OUTPUT_SELECT(x) (0x314 + (x))
99 #define DC_COM_PIN_MISC_CONTROL 0x31b
100 #define DC_COM_PIN_PM0_CONTROL 0x31c
101 #define DC_COM_PIN_PM0_DUTY_CYCLE 0x31d
102 #define DC_COM_PIN_PM1_CONTROL 0x31e
103 #define DC_COM_PIN_PM1_DUTY_CYCLE 0x31f
105 #define DC_COM_SPI_CONTROL 0x320
106 #define DC_COM_SPI_START_BYTE 0x321
107 #define DC_COM_HSPI_WRITE_DATA_AB 0x322
108 #define DC_COM_HSPI_WRITE_DATA_CD 0x323
109 #define DC_COM_HSPI_CS_DC 0x324
110 #define DC_COM_SCRATCH_REGISTER_A 0x325
111 #define DC_COM_SCRATCH_REGISTER_B 0x326
112 #define DC_COM_GPIO_CTRL 0x327
113 #define DC_COM_GPIO_DEBOUNCE_COUNTER 0x328
114 #define DC_COM_CRC_CHECKSUM_LATCHED 0x329
116 #define DC_DISP_DISP_SIGNAL_OPTIONS0 0x400
117 #define H_PULSE_0_ENABLE (1 << 8)
118 #define H_PULSE_1_ENABLE (1 << 10)
119 #define H_PULSE_2_ENABLE (1 << 12)
121 #define DC_DISP_DISP_SIGNAL_OPTIONS1 0x401
123 #define DC_DISP_DISP_WIN_OPTIONS 0x402
124 #define HDMI_ENABLE (1 << 30)
125 #define DSI_ENABLE (1 << 29)
126 #define SOR_ENABLE (1 << 25)
127 #define CURSOR_ENABLE (1 << 16)
129 #define DC_DISP_DISP_MEM_HIGH_PRIORITY 0x403
130 #define CURSOR_THRESHOLD(x) (((x) & 0x03) << 24)
131 #define WINDOW_A_THRESHOLD(x) (((x) & 0x7f) << 16)
132 #define WINDOW_B_THRESHOLD(x) (((x) & 0x7f) << 8)
133 #define WINDOW_C_THRESHOLD(x) (((x) & 0xff) << 0)
135 #define DC_DISP_DISP_MEM_HIGH_PRIORITY_TIMER 0x404
136 #define CURSOR_DELAY(x) (((x) & 0x3f) << 24)
137 #define WINDOW_A_DELAY(x) (((x) & 0x3f) << 16)
138 #define WINDOW_B_DELAY(x) (((x) & 0x3f) << 8)
139 #define WINDOW_C_DELAY(x) (((x) & 0x3f) << 0)
141 #define DC_DISP_DISP_TIMING_OPTIONS 0x405
142 #define VSYNC_H_POSITION(x) ((x) & 0xfff)
144 #define DC_DISP_REF_TO_SYNC 0x406
145 #define DC_DISP_SYNC_WIDTH 0x407
146 #define DC_DISP_BACK_PORCH 0x408
147 #define DC_DISP_ACTIVE 0x409
148 #define DC_DISP_FRONT_PORCH 0x40a
149 #define DC_DISP_H_PULSE0_CONTROL 0x40b
150 #define DC_DISP_H_PULSE0_POSITION_A 0x40c
151 #define DC_DISP_H_PULSE0_POSITION_B 0x40d
152 #define DC_DISP_H_PULSE0_POSITION_C 0x40e
153 #define DC_DISP_H_PULSE0_POSITION_D 0x40f
154 #define DC_DISP_H_PULSE1_CONTROL 0x410
155 #define DC_DISP_H_PULSE1_POSITION_A 0x411
156 #define DC_DISP_H_PULSE1_POSITION_B 0x412
157 #define DC_DISP_H_PULSE1_POSITION_C 0x413
158 #define DC_DISP_H_PULSE1_POSITION_D 0x414
159 #define DC_DISP_H_PULSE2_CONTROL 0x415
160 #define DC_DISP_H_PULSE2_POSITION_A 0x416
161 #define DC_DISP_H_PULSE2_POSITION_B 0x417
162 #define DC_DISP_H_PULSE2_POSITION_C 0x418
163 #define DC_DISP_H_PULSE2_POSITION_D 0x419
164 #define DC_DISP_V_PULSE0_CONTROL 0x41a
165 #define DC_DISP_V_PULSE0_POSITION_A 0x41b
166 #define DC_DISP_V_PULSE0_POSITION_B 0x41c
167 #define DC_DISP_V_PULSE0_POSITION_C 0x41d
168 #define DC_DISP_V_PULSE1_CONTROL 0x41e
169 #define DC_DISP_V_PULSE1_POSITION_A 0x41f
170 #define DC_DISP_V_PULSE1_POSITION_B 0x420
171 #define DC_DISP_V_PULSE1_POSITION_C 0x421
172 #define DC_DISP_V_PULSE2_CONTROL 0x422
173 #define DC_DISP_V_PULSE2_POSITION_A 0x423
174 #define DC_DISP_V_PULSE3_CONTROL 0x424
175 #define DC_DISP_V_PULSE3_POSITION_A 0x425
176 #define DC_DISP_M0_CONTROL 0x426
177 #define DC_DISP_M1_CONTROL 0x427
178 #define DC_DISP_DI_CONTROL 0x428
179 #define DC_DISP_PP_CONTROL 0x429
180 #define DC_DISP_PP_SELECT_A 0x42a
181 #define DC_DISP_PP_SELECT_B 0x42b
182 #define DC_DISP_PP_SELECT_C 0x42c
183 #define DC_DISP_PP_SELECT_D 0x42d
185 #define PULSE_MODE_NORMAL (0 << 3)
186 #define PULSE_MODE_ONE_CLOCK (1 << 3)
187 #define PULSE_POLARITY_HIGH (0 << 4)
188 #define PULSE_POLARITY_LOW (1 << 4)
189 #define PULSE_QUAL_ALWAYS (0 << 6)
190 #define PULSE_QUAL_VACTIVE (2 << 6)
191 #define PULSE_QUAL_VACTIVE1 (3 << 6)
192 #define PULSE_LAST_START_A (0 << 8)
193 #define PULSE_LAST_END_A (1 << 8)
194 #define PULSE_LAST_START_B (2 << 8)
195 #define PULSE_LAST_END_B (3 << 8)
196 #define PULSE_LAST_START_C (4 << 8)
197 #define PULSE_LAST_END_C (5 << 8)
198 #define PULSE_LAST_START_D (6 << 8)
199 #define PULSE_LAST_END_D (7 << 8)
201 #define PULSE_START(x) (((x) & 0xfff) << 0)
202 #define PULSE_END(x) (((x) & 0xfff) << 16)
204 #define DC_DISP_DISP_CLOCK_CONTROL 0x42e
205 #define PIXEL_CLK_DIVIDER_PCD1 (0 << 8)
206 #define PIXEL_CLK_DIVIDER_PCD1H (1 << 8)
207 #define PIXEL_CLK_DIVIDER_PCD2 (2 << 8)
208 #define PIXEL_CLK_DIVIDER_PCD3 (3 << 8)
209 #define PIXEL_CLK_DIVIDER_PCD4 (4 << 8)
210 #define PIXEL_CLK_DIVIDER_PCD6 (5 << 8)
211 #define PIXEL_CLK_DIVIDER_PCD8 (6 << 8)
212 #define PIXEL_CLK_DIVIDER_PCD9 (7 << 8)
213 #define PIXEL_CLK_DIVIDER_PCD12 (8 << 8)
214 #define PIXEL_CLK_DIVIDER_PCD16 (9 << 8)
215 #define PIXEL_CLK_DIVIDER_PCD18 (10 << 8)
216 #define PIXEL_CLK_DIVIDER_PCD24 (11 << 8)
217 #define PIXEL_CLK_DIVIDER_PCD13 (12 << 8)
218 #define SHIFT_CLK_DIVIDER(x) ((x) & 0xff)
220 #define DC_DISP_DISP_INTERFACE_CONTROL 0x42f
221 #define DISP_DATA_FORMAT_DF1P1C (0 << 0)
222 #define DISP_DATA_FORMAT_DF1P2C24B (1 << 0)
223 #define DISP_DATA_FORMAT_DF1P2C18B (2 << 0)
224 #define DISP_DATA_FORMAT_DF1P2C16B (3 << 0)
225 #define DISP_DATA_FORMAT_DF2S (4 << 0)
226 #define DISP_DATA_FORMAT_DF3S (5 << 0)
227 #define DISP_DATA_FORMAT_DFSPI (6 << 0)
228 #define DISP_DATA_FORMAT_DF1P3C24B (7 << 0)
229 #define DISP_DATA_FORMAT_DF1P3C18B (8 << 0)
230 #define DISP_ALIGNMENT_MSB (0 << 8)
231 #define DISP_ALIGNMENT_LSB (1 << 8)
232 #define DISP_ORDER_RED_BLUE (0 << 9)
233 #define DISP_ORDER_BLUE_RED (1 << 9)
235 #define DC_DISP_DISP_COLOR_CONTROL 0x430
236 #define BASE_COLOR_SIZE666 (0 << 0)
237 #define BASE_COLOR_SIZE111 (1 << 0)
238 #define BASE_COLOR_SIZE222 (2 << 0)
239 #define BASE_COLOR_SIZE333 (3 << 0)
240 #define BASE_COLOR_SIZE444 (4 << 0)
241 #define BASE_COLOR_SIZE555 (5 << 0)
242 #define BASE_COLOR_SIZE565 (6 << 0)
243 #define BASE_COLOR_SIZE332 (7 << 0)
244 #define BASE_COLOR_SIZE888 (8 << 0)
245 #define DITHER_CONTROL_DISABLE (0 << 8)
246 #define DITHER_CONTROL_ORDERED (2 << 8)
247 #define DITHER_CONTROL_ERRDIFF (3 << 8)
249 #define DC_DISP_SHIFT_CLOCK_OPTIONS 0x431
250 #define SC1_H_QUALIFIER_NONE (1 << 16)
251 #define SC0_H_QUALIFIER_NONE (1 << 0)
253 #define DC_DISP_DATA_ENABLE_OPTIONS 0x432
254 #define DE_SELECT_ACTIVE_BLANK (0 << 0)
255 #define DE_SELECT_ACTIVE (1 << 0)
256 #define DE_SELECT_ACTIVE_IS (2 << 0)
257 #define DE_CONTROL_ONECLK (0 << 2)
258 #define DE_CONTROL_NORMAL (1 << 2)
259 #define DE_CONTROL_EARLY_EXT (2 << 2)
260 #define DE_CONTROL_EARLY (3 << 2)
261 #define DE_CONTROL_ACTIVE_BLANK (4 << 2)
263 #define DC_DISP_SERIAL_INTERFACE_OPTIONS 0x433
264 #define DC_DISP_LCD_SPI_OPTIONS 0x434
265 #define DC_DISP_BORDER_COLOR 0x435
266 #define DC_DISP_COLOR_KEY0_LOWER 0x436
267 #define DC_DISP_COLOR_KEY0_UPPER 0x437
268 #define DC_DISP_COLOR_KEY1_LOWER 0x438
269 #define DC_DISP_COLOR_KEY1_UPPER 0x439
271 #define DC_DISP_CURSOR_FOREGROUND 0x43c
272 #define DC_DISP_CURSOR_BACKGROUND 0x43d
274 #define DC_DISP_CURSOR_START_ADDR 0x43e
275 #define CURSOR_CLIP_DISPLAY (0 << 28)
276 #define CURSOR_CLIP_WIN_A (1 << 28)
277 #define CURSOR_CLIP_WIN_B (2 << 28)
278 #define CURSOR_CLIP_WIN_C (3 << 28)
279 #define CURSOR_SIZE_32x32 (0 << 24)
280 #define CURSOR_SIZE_64x64 (1 << 24)
281 #define CURSOR_SIZE_128x128 (2 << 24)
282 #define CURSOR_SIZE_256x256 (3 << 24)
283 #define DC_DISP_CURSOR_START_ADDR_NS 0x43f
285 #define DC_DISP_CURSOR_POSITION 0x440
286 #define DC_DISP_CURSOR_POSITION_NS 0x441
288 #define DC_DISP_INIT_SEQ_CONTROL 0x442
289 #define DC_DISP_SPI_INIT_SEQ_DATA_A 0x443
290 #define DC_DISP_SPI_INIT_SEQ_DATA_B 0x444
291 #define DC_DISP_SPI_INIT_SEQ_DATA_C 0x445
292 #define DC_DISP_SPI_INIT_SEQ_DATA_D 0x446
294 #define DC_DISP_DC_MCCIF_FIFOCTRL 0x480
295 #define DC_DISP_MCCIF_DISPLAY0A_HYST 0x481
296 #define DC_DISP_MCCIF_DISPLAY0B_HYST 0x482
297 #define DC_DISP_MCCIF_DISPLAY1A_HYST 0x483
298 #define DC_DISP_MCCIF_DISPLAY1B_HYST 0x484
300 #define DC_DISP_DAC_CRT_CTRL 0x4c0
301 #define DC_DISP_DISP_MISC_CONTROL 0x4c1
302 #define DC_DISP_SD_CONTROL 0x4c2
303 #define DC_DISP_SD_CSC_COEFF 0x4c3
304 #define DC_DISP_SD_LUT(x) (0x4c4 + (x))
305 #define DC_DISP_SD_FLICKER_CONTROL 0x4cd
306 #define DC_DISP_DC_PIXEL_COUNT 0x4ce
307 #define DC_DISP_SD_HISTOGRAM(x) (0x4cf + (x))
308 #define DC_DISP_SD_BL_PARAMETERS 0x4d7
309 #define DC_DISP_SD_BL_TF(x) (0x4d8 + (x))
310 #define DC_DISP_SD_BL_CONTROL 0x4dc
311 #define DC_DISP_SD_HW_K_VALUES 0x4dd
312 #define DC_DISP_SD_MAN_K_VALUES 0x4de
314 #define DC_DISP_INTERLACE_CONTROL 0x4e5
315 #define INTERLACE_STATUS (1 << 2)
316 #define INTERLACE_START (1 << 1)
317 #define INTERLACE_ENABLE (1 << 0)
319 #define DC_DISP_CURSOR_START_ADDR_HI 0x4ec
320 #define DC_DISP_BLEND_CURSOR_CONTROL 0x4f1
321 #define CURSOR_MODE_LEGACY (0 << 24)
322 #define CURSOR_MODE_NORMAL (1 << 24)
323 #define CURSOR_DST_BLEND_ZERO (0 << 16)
324 #define CURSOR_DST_BLEND_K1 (1 << 16)
325 #define CURSOR_DST_BLEND_NEG_K1_TIMES_SRC (2 << 16)
326 #define CURSOR_DST_BLEND_MASK (3 << 16)
327 #define CURSOR_SRC_BLEND_K1 (0 << 8)
328 #define CURSOR_SRC_BLEND_K1_TIMES_SRC (1 << 8)
329 #define CURSOR_SRC_BLEND_MASK (3 << 8)
330 #define CURSOR_ALPHA 0xff
332 #define DC_WIN_CSC_YOF 0x611
333 #define DC_WIN_CSC_KYRGB 0x612
334 #define DC_WIN_CSC_KUR 0x613
335 #define DC_WIN_CSC_KVR 0x614
336 #define DC_WIN_CSC_KUG 0x615
337 #define DC_WIN_CSC_KVG 0x616
338 #define DC_WIN_CSC_KUB 0x617
339 #define DC_WIN_CSC_KVB 0x618
341 #define DC_WIN_WIN_OPTIONS 0x700
342 #define H_DIRECTION (1 << 0)
343 #define V_DIRECTION (1 << 2)
344 #define COLOR_EXPAND (1 << 6)
345 #define CSC_ENABLE (1 << 18)
346 #define WIN_ENABLE (1 << 30)
348 #define DC_WIN_BYTE_SWAP 0x701
349 #define BYTE_SWAP_NOSWAP (0 << 0)
350 #define BYTE_SWAP_SWAP2 (1 << 0)
351 #define BYTE_SWAP_SWAP4 (2 << 0)
352 #define BYTE_SWAP_SWAP4HW (3 << 0)
354 #define DC_WIN_BUFFER_CONTROL 0x702
355 #define BUFFER_CONTROL_HOST (0 << 0)
356 #define BUFFER_CONTROL_VI (1 << 0)
357 #define BUFFER_CONTROL_EPP (2 << 0)
358 #define BUFFER_CONTROL_MPEGE (3 << 0)
359 #define BUFFER_CONTROL_SB2D (4 << 0)
361 #define DC_WIN_COLOR_DEPTH 0x703
362 #define WIN_COLOR_DEPTH_P1 0
363 #define WIN_COLOR_DEPTH_P2 1
364 #define WIN_COLOR_DEPTH_P4 2
365 #define WIN_COLOR_DEPTH_P8 3
366 #define WIN_COLOR_DEPTH_B4G4R4A4 4
367 #define WIN_COLOR_DEPTH_B5G5R5A 5
368 #define WIN_COLOR_DEPTH_B5G6R5 6
369 #define WIN_COLOR_DEPTH_AB5G5R5 7
370 #define WIN_COLOR_DEPTH_B8G8R8A8 12
371 #define WIN_COLOR_DEPTH_R8G8B8A8 13
372 #define WIN_COLOR_DEPTH_B6x2G6x2R6x2A8 14
373 #define WIN_COLOR_DEPTH_R6x2G6x2B6x2A8 15
374 #define WIN_COLOR_DEPTH_YCbCr422 16
375 #define WIN_COLOR_DEPTH_YUV422 17
376 #define WIN_COLOR_DEPTH_YCbCr420P 18
377 #define WIN_COLOR_DEPTH_YUV420P 19
378 #define WIN_COLOR_DEPTH_YCbCr422P 20
379 #define WIN_COLOR_DEPTH_YUV422P 21
380 #define WIN_COLOR_DEPTH_YCbCr422R 22
381 #define WIN_COLOR_DEPTH_YUV422R 23
382 #define WIN_COLOR_DEPTH_YCbCr422RA 24
383 #define WIN_COLOR_DEPTH_YUV422RA 25
385 #define DC_WIN_POSITION 0x704
386 #define H_POSITION(x) (((x) & 0x1fff) << 0)
387 #define V_POSITION(x) (((x) & 0x1fff) << 16)
389 #define DC_WIN_SIZE 0x705
390 #define H_SIZE(x) (((x) & 0x1fff) << 0)
391 #define V_SIZE(x) (((x) & 0x1fff) << 16)
393 #define DC_WIN_PRESCALED_SIZE 0x706
394 #define H_PRESCALED_SIZE(x) (((x) & 0x7fff) << 0)
395 #define V_PRESCALED_SIZE(x) (((x) & 0x1fff) << 16)
397 #define DC_WIN_H_INITIAL_DDA 0x707
398 #define DC_WIN_V_INITIAL_DDA 0x708
399 #define DC_WIN_DDA_INC 0x709
400 #define H_DDA_INC(x) (((x) & 0xffff) << 0)
401 #define V_DDA_INC(x) (((x) & 0xffff) << 16)
403 #define DC_WIN_LINE_STRIDE 0x70a
404 #define DC_WIN_BUF_STRIDE 0x70b
405 #define DC_WIN_UV_BUF_STRIDE 0x70c
406 #define DC_WIN_BUFFER_ADDR_MODE 0x70d
407 #define DC_WIN_BUFFER_ADDR_MODE_LINEAR (0 << 0)
408 #define DC_WIN_BUFFER_ADDR_MODE_TILE (1 << 0)
409 #define DC_WIN_BUFFER_ADDR_MODE_LINEAR_UV (0 << 16)
410 #define DC_WIN_BUFFER_ADDR_MODE_TILE_UV (1 << 16)
411 #define DC_WIN_DV_CONTROL 0x70e
413 #define DC_WIN_BLEND_NOKEY 0x70f
414 #define DC_WIN_BLEND_1WIN 0x710
415 #define DC_WIN_BLEND_2WIN_X 0x711
416 #define DC_WIN_BLEND_2WIN_Y 0x712
417 #define DC_WIN_BLEND_3WIN_XY 0x713
419 #define DC_WIN_HP_FETCH_CONTROL 0x714
421 #define DC_WINBUF_START_ADDR 0x800
422 #define DC_WINBUF_START_ADDR_NS 0x801
423 #define DC_WINBUF_START_ADDR_U 0x802
424 #define DC_WINBUF_START_ADDR_U_NS 0x803
425 #define DC_WINBUF_START_ADDR_V 0x804
426 #define DC_WINBUF_START_ADDR_V_NS 0x805
428 #define DC_WINBUF_ADDR_H_OFFSET 0x806
429 #define DC_WINBUF_ADDR_H_OFFSET_NS 0x807
430 #define DC_WINBUF_ADDR_V_OFFSET 0x808
431 #define DC_WINBUF_ADDR_V_OFFSET_NS 0x809
433 #define DC_WINBUF_UFLOW_STATUS 0x80a
434 #define DC_WINBUF_SURFACE_KIND 0x80b
435 #define DC_WINBUF_SURFACE_KIND_PITCH (0 << 0)
436 #define DC_WINBUF_SURFACE_KIND_TILED (1 << 0)
437 #define DC_WINBUF_SURFACE_KIND_BLOCK (2 << 0)
438 #define DC_WINBUF_SURFACE_KIND_BLOCK_HEIGHT(x) (((x) & 0x7) << 4)
440 #define DC_WINBUF_AD_UFLOW_STATUS 0xbca
441 #define DC_WINBUF_BD_UFLOW_STATUS 0xdca
442 #define DC_WINBUF_CD_UFLOW_STATUS 0xfca
444 #endif /* TEGRA_DC_H */