2 * Copyright (C) 2013 NVIDIA Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
10 #include <linux/debugfs.h>
11 #include <linux/host1x.h>
12 #include <linux/module.h>
14 #include <linux/platform_device.h>
15 #include <linux/reset.h>
17 #include <linux/regulator/consumer.h>
19 #include <drm/drm_mipi_dsi.h>
20 #include <drm/drm_panel.h>
22 #include <video/mipi_display.h>
29 #define DSI_VIDEO_FIFO_DEPTH (1920 / 4)
30 #define DSI_HOST_FIFO_DEPTH 64
33 struct host1x_client client;
34 struct tegra_output output;
39 struct reset_control *rst;
40 struct clk *clk_parent;
44 struct drm_info_list *debugfs_files;
45 struct drm_minor *minor;
46 struct dentry *debugfs;
49 enum mipi_dsi_pixel_format format;
52 struct tegra_mipi_device *mipi;
53 struct mipi_dsi_host host;
55 struct regulator *vdd;
59 static inline struct tegra_dsi *
60 host1x_client_to_dsi(struct host1x_client *client)
62 return container_of(client, struct tegra_dsi, client);
65 static inline struct tegra_dsi *host_to_tegra(struct mipi_dsi_host *host)
67 return container_of(host, struct tegra_dsi, host);
70 static inline struct tegra_dsi *to_dsi(struct tegra_output *output)
72 return container_of(output, struct tegra_dsi, output);
75 static inline unsigned long tegra_dsi_readl(struct tegra_dsi *dsi,
78 return readl(dsi->regs + (reg << 2));
81 static inline void tegra_dsi_writel(struct tegra_dsi *dsi, unsigned long value,
84 writel(value, dsi->regs + (reg << 2));
87 static int tegra_dsi_show_regs(struct seq_file *s, void *data)
89 struct drm_info_node *node = s->private;
90 struct tegra_dsi *dsi = node->info_ent->data;
92 #define DUMP_REG(name) \
93 seq_printf(s, "%-32s %#05x %08lx\n", #name, name, \
94 tegra_dsi_readl(dsi, name))
96 DUMP_REG(DSI_INCR_SYNCPT);
97 DUMP_REG(DSI_INCR_SYNCPT_CONTROL);
98 DUMP_REG(DSI_INCR_SYNCPT_ERROR);
100 DUMP_REG(DSI_RD_DATA);
101 DUMP_REG(DSI_WR_DATA);
102 DUMP_REG(DSI_POWER_CONTROL);
103 DUMP_REG(DSI_INT_ENABLE);
104 DUMP_REG(DSI_INT_STATUS);
105 DUMP_REG(DSI_INT_MASK);
106 DUMP_REG(DSI_HOST_CONTROL);
107 DUMP_REG(DSI_CONTROL);
108 DUMP_REG(DSI_SOL_DELAY);
109 DUMP_REG(DSI_MAX_THRESHOLD);
110 DUMP_REG(DSI_TRIGGER);
111 DUMP_REG(DSI_TX_CRC);
112 DUMP_REG(DSI_STATUS);
114 DUMP_REG(DSI_INIT_SEQ_CONTROL);
115 DUMP_REG(DSI_INIT_SEQ_DATA_0);
116 DUMP_REG(DSI_INIT_SEQ_DATA_1);
117 DUMP_REG(DSI_INIT_SEQ_DATA_2);
118 DUMP_REG(DSI_INIT_SEQ_DATA_3);
119 DUMP_REG(DSI_INIT_SEQ_DATA_4);
120 DUMP_REG(DSI_INIT_SEQ_DATA_5);
121 DUMP_REG(DSI_INIT_SEQ_DATA_6);
122 DUMP_REG(DSI_INIT_SEQ_DATA_7);
124 DUMP_REG(DSI_PKT_SEQ_0_LO);
125 DUMP_REG(DSI_PKT_SEQ_0_HI);
126 DUMP_REG(DSI_PKT_SEQ_1_LO);
127 DUMP_REG(DSI_PKT_SEQ_1_HI);
128 DUMP_REG(DSI_PKT_SEQ_2_LO);
129 DUMP_REG(DSI_PKT_SEQ_2_HI);
130 DUMP_REG(DSI_PKT_SEQ_3_LO);
131 DUMP_REG(DSI_PKT_SEQ_3_HI);
132 DUMP_REG(DSI_PKT_SEQ_4_LO);
133 DUMP_REG(DSI_PKT_SEQ_4_HI);
134 DUMP_REG(DSI_PKT_SEQ_5_LO);
135 DUMP_REG(DSI_PKT_SEQ_5_HI);
137 DUMP_REG(DSI_DCS_CMDS);
139 DUMP_REG(DSI_PKT_LEN_0_1);
140 DUMP_REG(DSI_PKT_LEN_2_3);
141 DUMP_REG(DSI_PKT_LEN_4_5);
142 DUMP_REG(DSI_PKT_LEN_6_7);
144 DUMP_REG(DSI_PHY_TIMING_0);
145 DUMP_REG(DSI_PHY_TIMING_1);
146 DUMP_REG(DSI_PHY_TIMING_2);
147 DUMP_REG(DSI_BTA_TIMING);
149 DUMP_REG(DSI_TIMEOUT_0);
150 DUMP_REG(DSI_TIMEOUT_1);
151 DUMP_REG(DSI_TO_TALLY);
153 DUMP_REG(DSI_PAD_CONTROL_0);
154 DUMP_REG(DSI_PAD_CONTROL_CD);
155 DUMP_REG(DSI_PAD_CD_STATUS);
156 DUMP_REG(DSI_VIDEO_MODE_CONTROL);
157 DUMP_REG(DSI_PAD_CONTROL_1);
158 DUMP_REG(DSI_PAD_CONTROL_2);
159 DUMP_REG(DSI_PAD_CONTROL_3);
160 DUMP_REG(DSI_PAD_CONTROL_4);
162 DUMP_REG(DSI_GANGED_MODE_CONTROL);
163 DUMP_REG(DSI_GANGED_MODE_START);
164 DUMP_REG(DSI_GANGED_MODE_SIZE);
166 DUMP_REG(DSI_RAW_DATA_BYTE_COUNT);
167 DUMP_REG(DSI_ULTRA_LOW_POWER_CONTROL);
169 DUMP_REG(DSI_INIT_SEQ_DATA_8);
170 DUMP_REG(DSI_INIT_SEQ_DATA_9);
171 DUMP_REG(DSI_INIT_SEQ_DATA_10);
172 DUMP_REG(DSI_INIT_SEQ_DATA_11);
173 DUMP_REG(DSI_INIT_SEQ_DATA_12);
174 DUMP_REG(DSI_INIT_SEQ_DATA_13);
175 DUMP_REG(DSI_INIT_SEQ_DATA_14);
176 DUMP_REG(DSI_INIT_SEQ_DATA_15);
183 static struct drm_info_list debugfs_files[] = {
184 { "regs", tegra_dsi_show_regs, 0, NULL },
187 static int tegra_dsi_debugfs_init(struct tegra_dsi *dsi,
188 struct drm_minor *minor)
190 const char *name = dev_name(dsi->dev);
194 dsi->debugfs = debugfs_create_dir(name, minor->debugfs_root);
198 dsi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
200 if (!dsi->debugfs_files) {
205 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
206 dsi->debugfs_files[i].data = dsi;
208 err = drm_debugfs_create_files(dsi->debugfs_files,
209 ARRAY_SIZE(debugfs_files),
210 dsi->debugfs, minor);
219 kfree(dsi->debugfs_files);
220 dsi->debugfs_files = NULL;
222 debugfs_remove(dsi->debugfs);
228 static int tegra_dsi_debugfs_exit(struct tegra_dsi *dsi)
230 drm_debugfs_remove_files(dsi->debugfs_files, ARRAY_SIZE(debugfs_files),
234 kfree(dsi->debugfs_files);
235 dsi->debugfs_files = NULL;
237 debugfs_remove(dsi->debugfs);
243 #define PKT_ID0(id) ((((id) & 0x3f) << 3) | (1 << 9))
244 #define PKT_LEN0(len) (((len) & 0x07) << 0)
245 #define PKT_ID1(id) ((((id) & 0x3f) << 13) | (1 << 19))
246 #define PKT_LEN1(len) (((len) & 0x07) << 10)
247 #define PKT_ID2(id) ((((id) & 0x3f) << 23) | (1 << 29))
248 #define PKT_LEN2(len) (((len) & 0x07) << 20)
250 #define PKT_LP (1 << 30)
251 #define NUM_PKT_SEQ 12
254 * non-burst mode with sync pulses
256 static const u32 pkt_seq_video_non_burst_sync_pulses[NUM_PKT_SEQ] = {
257 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
258 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
259 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
262 [ 2] = PKT_ID0(MIPI_DSI_V_SYNC_END) | PKT_LEN0(0) |
263 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
264 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
267 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
268 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
269 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
272 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
273 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
274 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
275 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
276 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
277 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
278 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
279 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
280 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0) |
283 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
284 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(1) |
285 PKT_ID2(MIPI_DSI_H_SYNC_END) | PKT_LEN2(0),
286 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(2) |
287 PKT_ID1(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN1(3) |
288 PKT_ID2(MIPI_DSI_BLANKING_PACKET) | PKT_LEN2(4),
292 * non-burst mode with sync events
294 static const u32 pkt_seq_video_non_burst_sync_events[NUM_PKT_SEQ] = {
295 [ 0] = PKT_ID0(MIPI_DSI_V_SYNC_START) | PKT_LEN0(0) |
296 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
299 [ 2] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
300 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
303 [ 4] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
304 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
307 [ 6] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
308 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
309 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
310 [ 7] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
311 [ 8] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
312 PKT_ID1(MIPI_DSI_END_OF_TRANSMISSION) | PKT_LEN1(7) |
315 [10] = PKT_ID0(MIPI_DSI_H_SYNC_START) | PKT_LEN0(0) |
316 PKT_ID1(MIPI_DSI_BLANKING_PACKET) | PKT_LEN1(2) |
317 PKT_ID2(MIPI_DSI_PACKED_PIXEL_STREAM_24) | PKT_LEN2(3),
318 [11] = PKT_ID0(MIPI_DSI_BLANKING_PACKET) | PKT_LEN0(4),
321 static int tegra_dsi_set_phy_timing(struct tegra_dsi *dsi)
323 struct mipi_dphy_timing timing;
324 unsigned long value, period;
328 rate = clk_get_rate(dsi->clk);
332 period = DIV_ROUND_CLOSEST(1000000000UL, rate * 2);
334 err = mipi_dphy_timing_get_default(&timing, period);
338 err = mipi_dphy_timing_validate(&timing, period);
340 dev_err(dsi->dev, "failed to validate D-PHY timing: %d\n", err);
345 * The D-PHY timing fields below are expressed in byte-clock cycles,
346 * so multiply the period by 8.
350 value = DSI_TIMING_FIELD(timing.hsexit, period, 1) << 24 |
351 DSI_TIMING_FIELD(timing.hstrail, period, 0) << 16 |
352 DSI_TIMING_FIELD(timing.hszero, period, 3) << 8 |
353 DSI_TIMING_FIELD(timing.hsprepare, period, 1);
354 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_0);
356 value = DSI_TIMING_FIELD(timing.clktrail, period, 1) << 24 |
357 DSI_TIMING_FIELD(timing.clkpost, period, 1) << 16 |
358 DSI_TIMING_FIELD(timing.clkzero, period, 1) << 8 |
359 DSI_TIMING_FIELD(timing.lpx, period, 1);
360 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_1);
362 value = DSI_TIMING_FIELD(timing.clkprepare, period, 1) << 16 |
363 DSI_TIMING_FIELD(timing.clkpre, period, 1) << 8 |
364 DSI_TIMING_FIELD(0xff * period, period, 0) << 0;
365 tegra_dsi_writel(dsi, value, DSI_PHY_TIMING_2);
367 value = DSI_TIMING_FIELD(timing.taget, period, 1) << 16 |
368 DSI_TIMING_FIELD(timing.tasure, period, 1) << 8 |
369 DSI_TIMING_FIELD(timing.tago, period, 1);
370 tegra_dsi_writel(dsi, value, DSI_BTA_TIMING);
375 static int tegra_dsi_get_muldiv(enum mipi_dsi_pixel_format format,
376 unsigned int *mulp, unsigned int *divp)
379 case MIPI_DSI_FMT_RGB666_PACKED:
380 case MIPI_DSI_FMT_RGB888:
385 case MIPI_DSI_FMT_RGB565:
390 case MIPI_DSI_FMT_RGB666:
402 static int tegra_dsi_get_format(enum mipi_dsi_pixel_format format,
403 enum tegra_dsi_format *fmt)
406 case MIPI_DSI_FMT_RGB888:
407 *fmt = TEGRA_DSI_FORMAT_24P;
410 case MIPI_DSI_FMT_RGB666:
411 *fmt = TEGRA_DSI_FORMAT_18NP;
414 case MIPI_DSI_FMT_RGB666_PACKED:
415 *fmt = TEGRA_DSI_FORMAT_18P;
418 case MIPI_DSI_FMT_RGB565:
419 *fmt = TEGRA_DSI_FORMAT_16P;
429 static int tegra_output_dsi_enable(struct tegra_output *output)
431 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
432 struct drm_display_mode *mode = &dc->base.mode;
433 unsigned int hact, hsw, hbp, hfp, i, mul, div;
434 struct tegra_dsi *dsi = to_dsi(output);
435 enum tegra_dsi_format format;
443 if (dsi->flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) {
444 DRM_DEBUG_KMS("Non-burst video mode with sync pulses\n");
445 pkt_seq = pkt_seq_video_non_burst_sync_pulses;
447 DRM_DEBUG_KMS("Non-burst video mode with sync events\n");
448 pkt_seq = pkt_seq_video_non_burst_sync_events;
451 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
455 err = tegra_dsi_get_format(dsi->format, &format);
459 err = clk_enable(dsi->clk);
463 reset_control_deassert(dsi->rst);
465 value = DSI_CONTROL_CHANNEL(0) | DSI_CONTROL_FORMAT(format) |
466 DSI_CONTROL_LANES(dsi->lanes - 1) |
467 DSI_CONTROL_SOURCE(dc->pipe);
468 tegra_dsi_writel(dsi, value, DSI_CONTROL);
470 tegra_dsi_writel(dsi, DSI_VIDEO_FIFO_DEPTH, DSI_MAX_THRESHOLD);
472 value = DSI_HOST_CONTROL_HS | DSI_HOST_CONTROL_CS |
473 DSI_HOST_CONTROL_ECC;
474 tegra_dsi_writel(dsi, value, DSI_HOST_CONTROL);
476 value = tegra_dsi_readl(dsi, DSI_CONTROL);
477 value |= DSI_CONTROL_HS_CLK_CTRL;
478 value &= ~DSI_CONTROL_TX_TRIG(3);
479 value &= ~DSI_CONTROL_DCS_ENABLE;
480 value |= DSI_CONTROL_VIDEO_ENABLE;
481 value &= ~DSI_CONTROL_HOST_ENABLE;
482 tegra_dsi_writel(dsi, value, DSI_CONTROL);
484 err = tegra_dsi_set_phy_timing(dsi);
488 for (i = 0; i < NUM_PKT_SEQ; i++)
489 tegra_dsi_writel(dsi, pkt_seq[i], DSI_PKT_SEQ_0_LO + i);
491 /* horizontal active pixels */
492 hact = mode->hdisplay * mul / div;
494 /* horizontal sync width */
495 hsw = (mode->hsync_end - mode->hsync_start) * mul / div;
498 /* horizontal back porch */
499 hbp = (mode->htotal - mode->hsync_end) * mul / div;
502 /* horizontal front porch */
503 hfp = (mode->hsync_start - mode->hdisplay) * mul / div;
506 tegra_dsi_writel(dsi, hsw << 16 | 0, DSI_PKT_LEN_0_1);
507 tegra_dsi_writel(dsi, hact << 16 | hbp, DSI_PKT_LEN_2_3);
508 tegra_dsi_writel(dsi, hfp, DSI_PKT_LEN_4_5);
509 tegra_dsi_writel(dsi, 0x0f0f << 16, DSI_PKT_LEN_6_7);
512 tegra_dsi_writel(dsi, 8 * mul / div, DSI_SOL_DELAY);
514 /* enable display controller */
515 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
517 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
519 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
520 value &= ~DISP_CTRL_MODE_MASK;
521 value |= DISP_CTRL_MODE_C_DISPLAY;
522 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
524 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
525 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
526 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
527 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
529 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
530 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
532 /* enable DSI controller */
533 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
534 value |= DSI_POWER_CONTROL_ENABLE;
535 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
542 static int tegra_output_dsi_disable(struct tegra_output *output)
544 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
545 struct tegra_dsi *dsi = to_dsi(output);
551 /* disable DSI controller */
552 value = tegra_dsi_readl(dsi, DSI_POWER_CONTROL);
553 value &= ~DSI_POWER_CONTROL_ENABLE;
554 tegra_dsi_writel(dsi, value, DSI_POWER_CONTROL);
557 * The following accesses registers of the display controller, so make
558 * sure it's only executed when the output is attached to one.
561 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
562 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
563 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
564 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
566 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
567 value &= ~DISP_CTRL_MODE_MASK;
568 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
570 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
571 value &= ~DSI_ENABLE;
572 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
574 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
575 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
578 clk_disable(dsi->clk);
580 dsi->enabled = false;
585 static int tegra_output_dsi_setup_clock(struct tegra_output *output,
586 struct clk *clk, unsigned long pclk,
589 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
590 struct drm_display_mode *mode = &dc->base.mode;
591 unsigned int timeout, mul, div, vrefresh;
592 struct tegra_dsi *dsi = to_dsi(output);
593 unsigned long bclk, plld, value;
596 err = tegra_dsi_get_muldiv(dsi->format, &mul, &div);
600 DRM_DEBUG_KMS("mul: %u, div: %u, lanes: %u\n", mul, div, dsi->lanes);
601 vrefresh = drm_mode_vrefresh(mode);
602 DRM_DEBUG_KMS("vrefresh: %u\n", vrefresh);
604 /* compute byte clock */
605 bclk = (pclk * mul) / (div * dsi->lanes);
608 * Compute bit clock and round up to the next MHz.
610 plld = DIV_ROUND_UP(bclk * 8, 1000000) * 1000000;
613 * We divide the frequency by two here, but we make up for that by
614 * setting the shift clock divider (further below) to half of the
619 err = clk_set_parent(clk, dsi->clk_parent);
621 dev_err(dsi->dev, "failed to set parent clock: %d\n", err);
625 err = clk_set_rate(dsi->clk_parent, plld);
627 dev_err(dsi->dev, "failed to set base clock rate to %lu Hz\n",
633 * Derive pixel clock from bit clock using the shift clock divider.
634 * Note that this is only half of what we would expect, but we need
635 * that to make up for the fact that we divided the bit clock by a
636 * factor of two above.
638 * It's not clear exactly why this is necessary, but the display is
639 * not working properly otherwise. Perhaps the PLLs cannot generate
640 * frequencies sufficiently high.
642 *divp = ((8 * mul) / (div * dsi->lanes)) - 2;
645 * XXX: Move the below somewhere else so that we don't need to have
646 * access to the vrefresh in this function?
649 /* one frame high-speed transmission timeout */
650 timeout = (bclk / vrefresh) / 512;
651 value = DSI_TIMEOUT_LRX(0x2000) | DSI_TIMEOUT_HTX(timeout);
652 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_0);
654 /* 2 ms peripheral timeout for panel */
655 timeout = 2 * bclk / 512 * 1000;
656 value = DSI_TIMEOUT_PR(timeout) | DSI_TIMEOUT_TA(0x2000);
657 tegra_dsi_writel(dsi, value, DSI_TIMEOUT_1);
659 value = DSI_TALLY_TA(0) | DSI_TALLY_LRX(0) | DSI_TALLY_HTX(0);
660 tegra_dsi_writel(dsi, value, DSI_TO_TALLY);
665 static int tegra_output_dsi_check_mode(struct tegra_output *output,
666 struct drm_display_mode *mode,
667 enum drm_mode_status *status)
670 * FIXME: For now, always assume that the mode is okay.
678 static const struct tegra_output_ops dsi_ops = {
679 .enable = tegra_output_dsi_enable,
680 .disable = tegra_output_dsi_disable,
681 .setup_clock = tegra_output_dsi_setup_clock,
682 .check_mode = tegra_output_dsi_check_mode,
685 static int tegra_dsi_pad_enable(struct tegra_dsi *dsi)
689 value = DSI_PAD_CONTROL_VS1_PULLDN(0) | DSI_PAD_CONTROL_VS1_PDIO(0);
690 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_0);
695 static int tegra_dsi_pad_calibrate(struct tegra_dsi *dsi)
699 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_0);
700 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_1);
701 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_2);
702 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_3);
703 tegra_dsi_writel(dsi, 0, DSI_PAD_CONTROL_4);
705 /* start calibration */
706 tegra_dsi_pad_enable(dsi);
708 value = DSI_PAD_SLEW_UP(0x7) | DSI_PAD_SLEW_DN(0x7) |
709 DSI_PAD_LP_UP(0x1) | DSI_PAD_LP_DN(0x1) |
710 DSI_PAD_OUT_CLK(0x0);
711 tegra_dsi_writel(dsi, value, DSI_PAD_CONTROL_2);
713 return tegra_mipi_calibrate(dsi->mipi);
716 static int tegra_dsi_init(struct host1x_client *client)
718 struct tegra_drm *tegra = dev_get_drvdata(client->parent);
719 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
722 dsi->output.type = TEGRA_OUTPUT_DSI;
723 dsi->output.dev = client->dev;
724 dsi->output.ops = &dsi_ops;
726 err = tegra_output_init(tegra->drm, &dsi->output);
728 dev_err(client->dev, "output setup failed: %d\n", err);
732 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
733 err = tegra_dsi_debugfs_init(dsi, tegra->drm->primary);
735 dev_err(dsi->dev, "debugfs setup failed: %d\n", err);
738 err = tegra_dsi_pad_calibrate(dsi);
740 dev_err(dsi->dev, "MIPI calibration failed: %d\n", err);
747 static int tegra_dsi_exit(struct host1x_client *client)
749 struct tegra_dsi *dsi = host1x_client_to_dsi(client);
752 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
753 err = tegra_dsi_debugfs_exit(dsi);
755 dev_err(dsi->dev, "debugfs cleanup failed: %d\n", err);
758 err = tegra_output_disable(&dsi->output);
760 dev_err(client->dev, "output failed to disable: %d\n", err);
764 err = tegra_output_exit(&dsi->output);
766 dev_err(client->dev, "output cleanup failed: %d\n", err);
773 static const struct host1x_client_ops dsi_client_ops = {
774 .init = tegra_dsi_init,
775 .exit = tegra_dsi_exit,
778 static int tegra_dsi_setup_clocks(struct tegra_dsi *dsi)
783 parent = clk_get_parent(dsi->clk);
787 err = clk_set_parent(parent, dsi->clk_parent);
794 static int tegra_dsi_host_attach(struct mipi_dsi_host *host,
795 struct mipi_dsi_device *device)
797 struct tegra_dsi *dsi = host_to_tegra(host);
798 struct tegra_output *output = &dsi->output;
800 dsi->flags = device->mode_flags;
801 dsi->format = device->format;
802 dsi->lanes = device->lanes;
804 output->panel = of_drm_find_panel(device->dev.of_node);
806 if (output->connector.dev)
807 drm_helper_hpd_irq_event(output->connector.dev);
813 static int tegra_dsi_host_detach(struct mipi_dsi_host *host,
814 struct mipi_dsi_device *device)
816 struct tegra_dsi *dsi = host_to_tegra(host);
817 struct tegra_output *output = &dsi->output;
819 if (output->panel && &device->dev == output->panel->dev) {
820 if (output->connector.dev)
821 drm_helper_hpd_irq_event(output->connector.dev);
823 output->panel = NULL;
829 static const struct mipi_dsi_host_ops tegra_dsi_host_ops = {
830 .attach = tegra_dsi_host_attach,
831 .detach = tegra_dsi_host_detach,
834 static int tegra_dsi_probe(struct platform_device *pdev)
836 struct tegra_dsi *dsi;
837 struct resource *regs;
840 dsi = devm_kzalloc(&pdev->dev, sizeof(*dsi), GFP_KERNEL);
844 dsi->output.dev = dsi->dev = &pdev->dev;
846 err = tegra_output_probe(&dsi->output);
851 * Assume these values by default. When a DSI peripheral driver
852 * attaches to the DSI host, the parameters will be taken from
853 * the attached device.
855 dsi->flags = MIPI_DSI_MODE_VIDEO;
856 dsi->format = MIPI_DSI_FMT_RGB888;
859 dsi->rst = devm_reset_control_get(&pdev->dev, "dsi");
860 if (IS_ERR(dsi->rst))
861 return PTR_ERR(dsi->rst);
863 dsi->clk = devm_clk_get(&pdev->dev, NULL);
864 if (IS_ERR(dsi->clk)) {
865 dev_err(&pdev->dev, "cannot get DSI clock\n");
866 return PTR_ERR(dsi->clk);
869 err = clk_prepare_enable(dsi->clk);
871 dev_err(&pdev->dev, "cannot enable DSI clock\n");
875 dsi->clk_lp = devm_clk_get(&pdev->dev, "lp");
876 if (IS_ERR(dsi->clk_lp)) {
877 dev_err(&pdev->dev, "cannot get low-power clock\n");
878 return PTR_ERR(dsi->clk_lp);
881 err = clk_prepare_enable(dsi->clk_lp);
883 dev_err(&pdev->dev, "cannot enable low-power clock\n");
887 dsi->clk_parent = devm_clk_get(&pdev->dev, "parent");
888 if (IS_ERR(dsi->clk_parent)) {
889 dev_err(&pdev->dev, "cannot get parent clock\n");
890 return PTR_ERR(dsi->clk_parent);
893 err = clk_prepare_enable(dsi->clk_parent);
895 dev_err(&pdev->dev, "cannot enable parent clock\n");
899 dsi->vdd = devm_regulator_get(&pdev->dev, "avdd-dsi-csi");
900 if (IS_ERR(dsi->vdd)) {
901 dev_err(&pdev->dev, "cannot get VDD supply\n");
902 return PTR_ERR(dsi->vdd);
905 err = regulator_enable(dsi->vdd);
907 dev_err(&pdev->dev, "cannot enable VDD supply\n");
911 err = tegra_dsi_setup_clocks(dsi);
913 dev_err(&pdev->dev, "cannot setup clocks\n");
917 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
918 dsi->regs = devm_ioremap_resource(&pdev->dev, regs);
919 if (IS_ERR(dsi->regs))
920 return PTR_ERR(dsi->regs);
922 dsi->mipi = tegra_mipi_request(&pdev->dev);
923 if (IS_ERR(dsi->mipi))
924 return PTR_ERR(dsi->mipi);
926 dsi->host.ops = &tegra_dsi_host_ops;
927 dsi->host.dev = &pdev->dev;
929 err = mipi_dsi_host_register(&dsi->host);
931 dev_err(&pdev->dev, "failed to register DSI host: %d\n", err);
935 INIT_LIST_HEAD(&dsi->client.list);
936 dsi->client.ops = &dsi_client_ops;
937 dsi->client.dev = &pdev->dev;
939 err = host1x_client_register(&dsi->client);
941 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
946 platform_set_drvdata(pdev, dsi);
951 static int tegra_dsi_remove(struct platform_device *pdev)
953 struct tegra_dsi *dsi = platform_get_drvdata(pdev);
956 err = host1x_client_unregister(&dsi->client);
958 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
963 mipi_dsi_host_unregister(&dsi->host);
964 tegra_mipi_free(dsi->mipi);
966 regulator_disable(dsi->vdd);
967 clk_disable_unprepare(dsi->clk_parent);
968 clk_disable_unprepare(dsi->clk_lp);
969 clk_disable_unprepare(dsi->clk);
970 reset_control_assert(dsi->rst);
972 err = tegra_output_remove(&dsi->output);
974 dev_err(&pdev->dev, "failed to remove output: %d\n", err);
981 static const struct of_device_id tegra_dsi_of_match[] = {
982 { .compatible = "nvidia,tegra114-dsi", },
986 struct platform_driver tegra_dsi_driver = {
989 .of_match_table = tegra_dsi_of_match,
991 .probe = tegra_dsi_probe,
992 .remove = tegra_dsi_remove,