2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <linux/clk.h>
11 #include <linux/debugfs.h>
12 #include <linux/gpio.h>
13 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/regulator/consumer.h>
25 struct host1x_client client;
26 struct tegra_output output;
29 struct regulator *vdd;
30 struct regulator *pll;
35 struct clk *clk_parent;
38 unsigned int audio_source;
39 unsigned int audio_freq;
43 struct drm_info_list *debugfs_files;
44 struct drm_minor *minor;
45 struct dentry *debugfs;
48 static inline struct tegra_hdmi *
49 host1x_client_to_hdmi(struct host1x_client *client)
51 return container_of(client, struct tegra_hdmi, client);
54 static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
56 return container_of(output, struct tegra_hdmi, output);
59 #define HDMI_AUDIOCLK_FREQ 216000000
60 #define HDMI_REKEY_DEFAULT 56
68 static inline unsigned long tegra_hdmi_readl(struct tegra_hdmi *hdmi,
71 return readl(hdmi->regs + (reg << 2));
74 static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, unsigned long val,
77 writel(val, hdmi->regs + (reg << 2));
80 struct tegra_hdmi_audio_config {
87 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
88 { 25200000, 4096, 25200, 24000 },
89 { 27000000, 4096, 27000, 24000 },
90 { 74250000, 4096, 74250, 24000 },
91 { 148500000, 4096, 148500, 24000 },
95 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
96 { 25200000, 5880, 26250, 25000 },
97 { 27000000, 5880, 28125, 25000 },
98 { 74250000, 4704, 61875, 20000 },
99 { 148500000, 4704, 123750, 20000 },
103 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
104 { 25200000, 6144, 25200, 24000 },
105 { 27000000, 6144, 27000, 24000 },
106 { 74250000, 6144, 74250, 24000 },
107 { 148500000, 6144, 148500, 24000 },
111 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = {
112 { 25200000, 11760, 26250, 25000 },
113 { 27000000, 11760, 28125, 25000 },
114 { 74250000, 9408, 61875, 20000 },
115 { 148500000, 9408, 123750, 20000 },
119 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = {
120 { 25200000, 12288, 25200, 24000 },
121 { 27000000, 12288, 27000, 24000 },
122 { 74250000, 12288, 74250, 24000 },
123 { 148500000, 12288, 148500, 24000 },
127 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = {
128 { 25200000, 23520, 26250, 25000 },
129 { 27000000, 23520, 28125, 25000 },
130 { 74250000, 18816, 61875, 20000 },
131 { 148500000, 18816, 123750, 20000 },
135 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = {
136 { 25200000, 24576, 25200, 24000 },
137 { 27000000, 24576, 27000, 24000 },
138 { 74250000, 24576, 74250, 24000 },
139 { 148500000, 24576, 148500, 24000 },
151 static const struct tmds_config tegra2_tmds_config[] = {
154 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
155 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
156 SOR_PLL_TX_REG_LOAD(3),
157 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
158 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
159 PE_CURRENT1(PE_CURRENT_0_0_mA) |
160 PE_CURRENT2(PE_CURRENT_0_0_mA) |
161 PE_CURRENT3(PE_CURRENT_0_0_mA),
162 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
163 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
164 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
165 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
166 }, { /* 720p modes */
168 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
169 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
170 SOR_PLL_TX_REG_LOAD(3),
171 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
172 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
173 PE_CURRENT1(PE_CURRENT_6_0_mA) |
174 PE_CURRENT2(PE_CURRENT_6_0_mA) |
175 PE_CURRENT3(PE_CURRENT_6_0_mA),
176 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
177 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
178 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
179 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
180 }, { /* 1080p modes */
182 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
183 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
184 SOR_PLL_TX_REG_LOAD(3),
185 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
186 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
187 PE_CURRENT1(PE_CURRENT_6_0_mA) |
188 PE_CURRENT2(PE_CURRENT_6_0_mA) |
189 PE_CURRENT3(PE_CURRENT_6_0_mA),
190 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
191 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
192 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
193 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
197 static const struct tmds_config tegra3_tmds_config[] = {
200 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
201 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
202 SOR_PLL_TX_REG_LOAD(0),
203 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
204 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
205 PE_CURRENT1(PE_CURRENT_0_0_mA) |
206 PE_CURRENT2(PE_CURRENT_0_0_mA) |
207 PE_CURRENT3(PE_CURRENT_0_0_mA),
208 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
209 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
210 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
211 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
212 }, { /* 720p modes */
214 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
215 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
216 SOR_PLL_TX_REG_LOAD(0),
217 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
218 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
219 PE_CURRENT1(PE_CURRENT_5_0_mA) |
220 PE_CURRENT2(PE_CURRENT_5_0_mA) |
221 PE_CURRENT3(PE_CURRENT_5_0_mA),
222 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
223 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
224 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
225 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
226 }, { /* 1080p modes */
228 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
229 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
230 SOR_PLL_TX_REG_LOAD(0),
231 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
232 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
233 PE_CURRENT1(PE_CURRENT_5_0_mA) |
234 PE_CURRENT2(PE_CURRENT_5_0_mA) |
235 PE_CURRENT3(PE_CURRENT_5_0_mA),
236 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
237 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
238 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
239 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
243 static const struct tegra_hdmi_audio_config *
244 tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pclk)
246 const struct tegra_hdmi_audio_config *table;
248 switch (audio_freq) {
250 table = tegra_hdmi_audio_32k;
254 table = tegra_hdmi_audio_44_1k;
258 table = tegra_hdmi_audio_48k;
262 table = tegra_hdmi_audio_88_2k;
266 table = tegra_hdmi_audio_96k;
270 table = tegra_hdmi_audio_176_4k;
274 table = tegra_hdmi_audio_192k;
281 while (table->pclk) {
282 if (table->pclk == pclk)
291 static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
293 const unsigned int freqs[] = {
294 32000, 44100, 48000, 88200, 96000, 176400, 192000
298 for (i = 0; i < ARRAY_SIZE(freqs); i++) {
299 unsigned int f = freqs[i];
300 unsigned int eight_half;
311 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
312 value = AUDIO_FS_LOW(eight_half - delta) |
313 AUDIO_FS_HIGH(eight_half + delta);
314 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
318 static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi, unsigned int pclk)
320 struct device_node *node = hdmi->dev->of_node;
321 const struct tegra_hdmi_audio_config *config;
322 unsigned int offset = 0;
325 switch (hdmi->audio_source) {
327 value = AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
331 value = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
335 value = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
339 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
340 value |= AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
341 AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
342 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
344 value |= AUDIO_CNTRL0_INJECT_NULLSMPL;
345 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
347 value = AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
348 AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
349 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
352 config = tegra_hdmi_get_audio_config(hdmi->audio_freq, pclk);
354 dev_err(hdmi->dev, "cannot set audio to %u at %u pclk\n",
355 hdmi->audio_freq, pclk);
359 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
361 value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
362 AUDIO_N_VALUE(config->n - 1);
363 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
365 tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
366 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
368 value = ACR_SUBPACK_CTS(config->cts);
369 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
371 value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
372 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
374 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
375 value &= ~AUDIO_N_RESETF;
376 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
378 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
379 switch (hdmi->audio_freq) {
381 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320;
385 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441;
389 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480;
393 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882;
397 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960;
401 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764;
405 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920;
409 tegra_hdmi_writel(hdmi, config->aval, offset);
412 tegra_hdmi_setup_audio_fs_tables(hdmi);
417 static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi,
418 unsigned int offset, u8 type,
419 u8 version, void *data, size_t size)
427 /* first byte of data is the checksum */
428 csum = type + version + size - 1;
430 for (i = 1; i < size; i++)
433 ptr[0] = 0x100 - csum;
435 value = INFOFRAME_HEADER_TYPE(type) |
436 INFOFRAME_HEADER_VERSION(version) |
437 INFOFRAME_HEADER_LEN(size - 1);
438 tegra_hdmi_writel(hdmi, value, offset);
440 /* The audio inforame only has one set of subpack registers. The hdmi
441 * block pads the rest of the data as per the spec so we have to fixup
442 * the length before filling in the subpacks.
444 if (offset == HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER)
447 /* each subpack 7 bytes devided into:
448 * subpack_low - bytes 0 - 3
449 * subpack_high - bytes 4 - 6 (with byte 7 padded to 0x00)
451 for (i = 0; i < size; i++) {
452 size_t index = i % 7;
455 memset(subpack, 0x0, sizeof(subpack));
457 ((u8 *)subpack)[index] = ptr[i];
459 if (index == 6 || (i + 1 == size)) {
460 unsigned int reg = offset + 1 + (i / 7) * 2;
462 tegra_hdmi_writel(hdmi, subpack[0], reg);
463 tegra_hdmi_writel(hdmi, subpack[1], reg + 1);
468 static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
469 struct drm_display_mode *mode)
471 struct hdmi_avi_infoframe frame;
472 unsigned int h_front_porch;
473 unsigned int hsize = 16;
474 unsigned int vsize = 9;
477 tegra_hdmi_writel(hdmi, 0,
478 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
482 h_front_porch = mode->htotal - mode->hsync_end;
483 memset(&frame, 0, sizeof(frame));
484 frame.r = HDMI_AVI_R_SAME;
486 switch (mode->vdisplay) {
488 if (mode->hdisplay == 640) {
489 frame.m = HDMI_AVI_M_4_3;
492 frame.m = HDMI_AVI_M_16_9;
498 if (((hsize * 10) / vsize) > 14) {
499 frame.m = HDMI_AVI_M_16_9;
502 frame.m = HDMI_AVI_M_4_3;
508 case 1470: /* stereo mode */
509 frame.m = HDMI_AVI_M_16_9;
511 if (h_front_porch == 110)
518 case 2205: /* stereo mode */
519 frame.m = HDMI_AVI_M_16_9;
521 switch (h_front_porch) {
537 frame.m = HDMI_AVI_M_16_9;
542 tegra_hdmi_write_infopack(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER,
543 HDMI_INFOFRAME_TYPE_AVI, HDMI_AVI_VERSION,
544 &frame, sizeof(frame));
546 tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
547 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
550 static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
552 struct hdmi_audio_infoframe frame;
555 tegra_hdmi_writel(hdmi, 0,
556 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
560 memset(&frame, 0, sizeof(frame));
561 frame.cc = HDMI_AUDIO_CC_2;
563 tegra_hdmi_write_infopack(hdmi,
564 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER,
565 HDMI_INFOFRAME_TYPE_AUDIO,
567 &frame, sizeof(frame));
569 tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
570 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
573 static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
575 struct hdmi_stereo_infoframe frame;
579 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
580 value &= ~GENERIC_CTRL_ENABLE;
581 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
585 memset(&frame, 0, sizeof(frame));
589 frame.hdmi_video_format = 2;
591 /* TODO: 74 MHz limit? */
593 frame._3d_structure = 0;
595 frame._3d_structure = 8;
596 frame._3d_ext_data = 0;
599 tegra_hdmi_write_infopack(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_HEADER,
600 HDMI_INFOFRAME_TYPE_VENDOR,
601 HDMI_VENDOR_VERSION, &frame, 6);
603 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
604 value |= GENERIC_CTRL_ENABLE;
605 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
608 static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
609 const struct tmds_config *tmds)
613 tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
614 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
615 tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
617 value = tmds->drive_current | DRIVE_CURRENT_FUSE_OVERRIDE;
618 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
621 static int tegra_output_hdmi_enable(struct tegra_output *output)
623 unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
624 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
625 struct drm_display_mode *mode = &dc->base.mode;
626 struct tegra_hdmi *hdmi = to_hdmi(output);
627 struct device_node *node = hdmi->dev->of_node;
628 unsigned int pulse_start, div82, pclk;
629 const struct tmds_config *tmds;
630 unsigned int num_tmds;
635 pclk = mode->clock * 1000;
636 h_sync_width = mode->hsync_end - mode->hsync_start;
637 h_front_porch = mode->htotal - mode->hsync_end;
638 h_back_porch = mode->hsync_start - mode->hdisplay;
640 err = regulator_enable(hdmi->vdd);
642 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
646 err = regulator_enable(hdmi->pll);
648 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
653 * This assumes that the display controller will divide its parent
654 * clock by 2 to generate the pixel clock.
656 err = tegra_output_setup_clock(output, hdmi->clk, pclk * 2);
658 dev_err(hdmi->dev, "failed to setup clock: %d\n", err);
662 err = clk_set_rate(hdmi->clk, pclk);
666 err = clk_enable(hdmi->clk);
668 dev_err(hdmi->dev, "failed to enable clock: %d\n", err);
672 tegra_periph_reset_assert(hdmi->clk);
673 usleep_range(1000, 2000);
674 tegra_periph_reset_deassert(hdmi->clk);
676 tegra_dc_writel(dc, VSYNC_H_POSITION(1),
677 DC_DISP_DISP_TIMING_OPTIONS);
678 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE888,
679 DC_DISP_DISP_COLOR_CONTROL);
681 /* video_preamble uses h_pulse2 */
682 pulse_start = 1 + h_sync_width + h_back_porch - 10;
684 tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
686 value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
688 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
690 value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
691 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
693 value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
695 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
698 value = HDMI_SRC_DISPLAYB;
700 value = HDMI_SRC_DISPLAYA;
702 if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
703 (mode->vdisplay == 576)))
704 tegra_hdmi_writel(hdmi,
705 value | ARM_VIDEO_RANGE_FULL,
706 HDMI_NV_PDISP_INPUT_CONTROL);
708 tegra_hdmi_writel(hdmi,
709 value | ARM_VIDEO_RANGE_LIMITED,
710 HDMI_NV_PDISP_INPUT_CONTROL);
712 div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
713 value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
714 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
717 err = tegra_hdmi_setup_audio(hdmi, pclk);
722 if (of_device_is_compatible(node, "nvidia,tegra20-hdmi")) {
724 * TODO: add ELD support
728 rekey = HDMI_REKEY_DEFAULT;
729 value = HDMI_CTRL_REKEY(rekey);
730 value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
731 h_front_porch - rekey - 18) / 32);
734 value |= HDMI_CTRL_ENABLE;
736 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
739 tegra_hdmi_writel(hdmi, 0x0,
740 HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
742 tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO,
743 HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
745 tegra_hdmi_setup_avi_infoframe(hdmi, mode);
746 tegra_hdmi_setup_audio_infoframe(hdmi);
747 tegra_hdmi_setup_stereo_infoframe(hdmi);
750 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
751 num_tmds = ARRAY_SIZE(tegra3_tmds_config);
752 tmds = tegra3_tmds_config;
754 num_tmds = ARRAY_SIZE(tegra2_tmds_config);
755 tmds = tegra2_tmds_config;
758 for (i = 0; i < num_tmds; i++) {
759 if (pclk <= tmds[i].pclk) {
760 tegra_hdmi_setup_tmds(hdmi, &tmds[i]);
765 tegra_hdmi_writel(hdmi,
766 SOR_SEQ_CTL_PU_PC(0) |
767 SOR_SEQ_PU_PC_ALT(0) |
769 SOR_SEQ_PD_PC_ALT(8),
770 HDMI_NV_PDISP_SOR_SEQ_CTL);
772 value = SOR_SEQ_INST_WAIT_TIME(1) |
773 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
775 SOR_SEQ_INST_PIN_A_LOW |
776 SOR_SEQ_INST_PIN_B_LOW |
777 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
779 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
780 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
783 value &= ~SOR_CSTM_ROTCLK(~0);
784 value |= SOR_CSTM_ROTCLK(2);
785 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
787 tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
788 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
789 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
792 tegra_hdmi_writel(hdmi,
793 SOR_PWR_NORMAL_STATE_PU |
794 SOR_PWR_NORMAL_START_NORMAL |
795 SOR_PWR_SAFE_STATE_PD |
796 SOR_PWR_SETTING_NEW_TRIGGER,
797 HDMI_NV_PDISP_SOR_PWR);
798 tegra_hdmi_writel(hdmi,
799 SOR_PWR_NORMAL_STATE_PU |
800 SOR_PWR_NORMAL_START_NORMAL |
801 SOR_PWR_SAFE_STATE_PD |
802 SOR_PWR_SETTING_NEW_DONE,
803 HDMI_NV_PDISP_SOR_PWR);
806 BUG_ON(--retries < 0);
807 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
808 } while (value & SOR_PWR_SETTING_NEW_PENDING);
810 value = SOR_STATE_ASY_CRCMODE_COMPLETE |
811 SOR_STATE_ASY_OWNER_HEAD0 |
812 SOR_STATE_ASY_SUBOWNER_BOTH |
813 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
814 SOR_STATE_ASY_DEPOL_POS;
816 /* setup sync polarities */
817 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
818 value |= SOR_STATE_ASY_HSYNCPOL_POS;
820 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
821 value |= SOR_STATE_ASY_HSYNCPOL_NEG;
823 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
824 value |= SOR_STATE_ASY_VSYNCPOL_POS;
826 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
827 value |= SOR_STATE_ASY_VSYNCPOL_NEG;
829 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
831 value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
832 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
834 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
835 tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
836 tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
837 HDMI_NV_PDISP_SOR_STATE1);
838 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
840 tegra_dc_writel(dc, HDMI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
842 value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
843 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
844 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
846 value = DISP_CTRL_MODE_C_DISPLAY;
847 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
849 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
850 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
852 /* TODO: add HDCP support */
857 static int tegra_output_hdmi_disable(struct tegra_output *output)
859 struct tegra_hdmi *hdmi = to_hdmi(output);
861 tegra_periph_reset_assert(hdmi->clk);
862 clk_disable(hdmi->clk);
863 regulator_disable(hdmi->pll);
864 regulator_disable(hdmi->vdd);
869 static int tegra_output_hdmi_setup_clock(struct tegra_output *output,
870 struct clk *clk, unsigned long pclk)
872 struct tegra_hdmi *hdmi = to_hdmi(output);
876 err = clk_set_parent(clk, hdmi->clk_parent);
878 dev_err(output->dev, "failed to set parent: %d\n", err);
882 base = clk_get_parent(hdmi->clk_parent);
885 * This assumes that the parent clock is pll_d_out0 or pll_d2_out
886 * respectively, each of which divides the base pll_d by 2.
888 err = clk_set_rate(base, pclk * 2);
891 "failed to set base clock rate to %lu Hz\n",
897 static int tegra_output_hdmi_check_mode(struct tegra_output *output,
898 struct drm_display_mode *mode,
899 enum drm_mode_status *status)
901 struct tegra_hdmi *hdmi = to_hdmi(output);
902 unsigned long pclk = mode->clock * 1000;
906 parent = clk_get_parent(hdmi->clk_parent);
908 err = clk_round_rate(parent, pclk * 4);
910 *status = MODE_NOCLOCK;
917 static const struct tegra_output_ops hdmi_ops = {
918 .enable = tegra_output_hdmi_enable,
919 .disable = tegra_output_hdmi_disable,
920 .setup_clock = tegra_output_hdmi_setup_clock,
921 .check_mode = tegra_output_hdmi_check_mode,
924 static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
926 struct drm_info_node *node = s->private;
927 struct tegra_hdmi *hdmi = node->info_ent->data;
929 #define DUMP_REG(name) \
930 seq_printf(s, "%-56s %#05x %08lx\n", #name, name, \
931 tegra_hdmi_readl(hdmi, name))
933 DUMP_REG(HDMI_CTXSW);
934 DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
935 DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
936 DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
937 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
938 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
939 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
940 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
941 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
942 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
943 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
944 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
945 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
946 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
947 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
948 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
949 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
950 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
951 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
952 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
953 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
954 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
955 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
956 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
957 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
958 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
959 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
960 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
961 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
962 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
963 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
964 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
965 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
966 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
967 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
968 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
969 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
970 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
971 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
972 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
973 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
974 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
975 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
976 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
977 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
978 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
979 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
980 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
981 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
982 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
983 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
984 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
985 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
986 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
987 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
988 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
989 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
990 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
991 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
992 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
993 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
994 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
995 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
996 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
997 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
998 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
999 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
1000 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
1001 DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
1002 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
1003 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
1004 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
1005 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
1006 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
1007 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
1008 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
1009 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
1010 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
1011 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
1012 DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
1013 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
1014 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
1015 DUMP_REG(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL);
1016 DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
1017 DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
1018 DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
1019 DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
1020 DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
1021 DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
1022 DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
1023 DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
1024 DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
1025 DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
1026 DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
1027 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
1028 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(0));
1029 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(1));
1030 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(2));
1031 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(3));
1032 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(4));
1033 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(5));
1034 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(6));
1035 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(7));
1036 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(8));
1037 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(9));
1038 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(10));
1039 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(11));
1040 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(12));
1041 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(13));
1042 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(14));
1043 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(15));
1044 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
1045 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
1046 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
1047 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
1048 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
1049 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
1050 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
1051 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
1052 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
1053 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
1054 DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
1055 DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
1056 DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1057 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
1058 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
1059 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
1060 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
1061 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
1062 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
1063 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
1064 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
1065 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
1066 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
1067 DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
1068 DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
1069 DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
1070 DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
1071 DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
1072 DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
1073 DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
1074 DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
1075 DUMP_REG(HDMI_NV_PDISP_SCRATCH);
1076 DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
1077 DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
1078 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
1079 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
1080 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
1081 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
1082 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
1083 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
1084 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
1085 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
1086 DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
1087 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
1088 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
1089 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
1096 static struct drm_info_list debugfs_files[] = {
1097 { "regs", tegra_hdmi_show_regs, 0, NULL },
1100 static int tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi,
1101 struct drm_minor *minor)
1106 hdmi->debugfs = debugfs_create_dir("hdmi", minor->debugfs_root);
1110 hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1112 if (!hdmi->debugfs_files) {
1117 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1118 hdmi->debugfs_files[i].data = hdmi;
1120 err = drm_debugfs_create_files(hdmi->debugfs_files,
1121 ARRAY_SIZE(debugfs_files),
1122 hdmi->debugfs, minor);
1126 hdmi->minor = minor;
1131 kfree(hdmi->debugfs_files);
1132 hdmi->debugfs_files = NULL;
1134 debugfs_remove(hdmi->debugfs);
1135 hdmi->debugfs = NULL;
1140 static int tegra_hdmi_debugfs_exit(struct tegra_hdmi *hdmi)
1142 drm_debugfs_remove_files(hdmi->debugfs_files, ARRAY_SIZE(debugfs_files),
1146 kfree(hdmi->debugfs_files);
1147 hdmi->debugfs_files = NULL;
1149 debugfs_remove(hdmi->debugfs);
1150 hdmi->debugfs = NULL;
1155 static int tegra_hdmi_drm_init(struct host1x_client *client,
1156 struct drm_device *drm)
1158 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1161 hdmi->output.type = TEGRA_OUTPUT_HDMI;
1162 hdmi->output.dev = client->dev;
1163 hdmi->output.ops = &hdmi_ops;
1165 err = tegra_output_init(drm, &hdmi->output);
1167 dev_err(client->dev, "output setup failed: %d\n", err);
1171 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1172 err = tegra_hdmi_debugfs_init(hdmi, drm->primary);
1174 dev_err(client->dev, "debugfs setup failed: %d\n", err);
1180 static int tegra_hdmi_drm_exit(struct host1x_client *client)
1182 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1185 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1186 err = tegra_hdmi_debugfs_exit(hdmi);
1188 dev_err(client->dev, "debugfs cleanup failed: %d\n",
1192 err = tegra_output_disable(&hdmi->output);
1194 dev_err(client->dev, "output failed to disable: %d\n", err);
1198 err = tegra_output_exit(&hdmi->output);
1200 dev_err(client->dev, "output cleanup failed: %d\n", err);
1207 static const struct host1x_client_ops hdmi_client_ops = {
1208 .drm_init = tegra_hdmi_drm_init,
1209 .drm_exit = tegra_hdmi_drm_exit,
1212 static int tegra_hdmi_probe(struct platform_device *pdev)
1214 struct host1x *host1x = dev_get_drvdata(pdev->dev.parent);
1215 struct tegra_hdmi *hdmi;
1216 struct resource *regs;
1219 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1223 hdmi->dev = &pdev->dev;
1224 hdmi->audio_source = AUTO;
1225 hdmi->audio_freq = 44100;
1226 hdmi->stereo = false;
1229 hdmi->clk = devm_clk_get(&pdev->dev, NULL);
1230 if (IS_ERR(hdmi->clk)) {
1231 dev_err(&pdev->dev, "failed to get clock\n");
1232 return PTR_ERR(hdmi->clk);
1235 err = clk_prepare(hdmi->clk);
1239 hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1240 if (IS_ERR(hdmi->clk_parent))
1241 return PTR_ERR(hdmi->clk_parent);
1243 err = clk_prepare(hdmi->clk_parent);
1247 err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
1249 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
1253 hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
1254 if (IS_ERR(hdmi->vdd)) {
1255 dev_err(&pdev->dev, "failed to get VDD regulator\n");
1256 return PTR_ERR(hdmi->vdd);
1259 hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
1260 if (IS_ERR(hdmi->pll)) {
1261 dev_err(&pdev->dev, "failed to get PLL regulator\n");
1262 return PTR_ERR(hdmi->pll);
1265 hdmi->output.dev = &pdev->dev;
1267 err = tegra_output_parse_dt(&hdmi->output);
1271 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1275 hdmi->regs = devm_request_and_ioremap(&pdev->dev, regs);
1277 return -EADDRNOTAVAIL;
1279 err = platform_get_irq(pdev, 0);
1285 hdmi->client.ops = &hdmi_client_ops;
1286 INIT_LIST_HEAD(&hdmi->client.list);
1287 hdmi->client.dev = &pdev->dev;
1289 err = host1x_register_client(host1x, &hdmi->client);
1291 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1296 platform_set_drvdata(pdev, hdmi);
1301 static int tegra_hdmi_remove(struct platform_device *pdev)
1303 struct host1x *host1x = dev_get_drvdata(pdev->dev.parent);
1304 struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
1307 err = host1x_unregister_client(host1x, &hdmi->client);
1309 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1314 clk_unprepare(hdmi->clk_parent);
1315 clk_unprepare(hdmi->clk);
1320 static struct of_device_id tegra_hdmi_of_match[] = {
1321 { .compatible = "nvidia,tegra30-hdmi", },
1322 { .compatible = "nvidia,tegra20-hdmi", },
1326 struct platform_driver tegra_hdmi_driver = {
1328 .name = "tegra-hdmi",
1329 .owner = THIS_MODULE,
1330 .of_match_table = tegra_hdmi_of_match,
1332 .probe = tegra_hdmi_probe,
1333 .remove = tegra_hdmi_remove,