2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <linux/clk.h>
11 #include <linux/debugfs.h>
12 #include <linux/gpio.h>
13 #include <linux/module.h>
15 #include <linux/platform_device.h>
16 #include <linux/regulator/consumer.h>
25 struct host1x_client client;
26 struct tegra_output output;
29 struct regulator *vdd;
30 struct regulator *pll;
35 struct clk *clk_parent;
38 unsigned int audio_source;
39 unsigned int audio_freq;
43 struct drm_info_list *debugfs_files;
44 struct drm_minor *minor;
45 struct dentry *debugfs;
48 static inline struct tegra_hdmi *
49 host1x_client_to_hdmi(struct host1x_client *client)
51 return container_of(client, struct tegra_hdmi, client);
54 static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
56 return container_of(output, struct tegra_hdmi, output);
59 #define HDMI_AUDIOCLK_FREQ 216000000
60 #define HDMI_REKEY_DEFAULT 56
68 static inline unsigned long tegra_hdmi_readl(struct tegra_hdmi *hdmi,
71 return readl(hdmi->regs + (reg << 2));
74 static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, unsigned long val,
77 writel(val, hdmi->regs + (reg << 2));
80 struct tegra_hdmi_audio_config {
87 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
88 { 25200000, 4096, 25200, 24000 },
89 { 27000000, 4096, 27000, 24000 },
90 { 74250000, 4096, 74250, 24000 },
91 { 148500000, 4096, 148500, 24000 },
95 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
96 { 25200000, 5880, 26250, 25000 },
97 { 27000000, 5880, 28125, 25000 },
98 { 74250000, 4704, 61875, 20000 },
99 { 148500000, 4704, 123750, 20000 },
103 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
104 { 25200000, 6144, 25200, 24000 },
105 { 27000000, 6144, 27000, 24000 },
106 { 74250000, 6144, 74250, 24000 },
107 { 148500000, 6144, 148500, 24000 },
111 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = {
112 { 25200000, 11760, 26250, 25000 },
113 { 27000000, 11760, 28125, 25000 },
114 { 74250000, 9408, 61875, 20000 },
115 { 148500000, 9408, 123750, 20000 },
119 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = {
120 { 25200000, 12288, 25200, 24000 },
121 { 27000000, 12288, 27000, 24000 },
122 { 74250000, 12288, 74250, 24000 },
123 { 148500000, 12288, 148500, 24000 },
127 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = {
128 { 25200000, 23520, 26250, 25000 },
129 { 27000000, 23520, 28125, 25000 },
130 { 74250000, 18816, 61875, 20000 },
131 { 148500000, 18816, 123750, 20000 },
135 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = {
136 { 25200000, 24576, 25200, 24000 },
137 { 27000000, 24576, 27000, 24000 },
138 { 74250000, 24576, 74250, 24000 },
139 { 148500000, 24576, 148500, 24000 },
151 static const struct tmds_config tegra2_tmds_config[] = {
152 { /* slow pixel clock modes */
154 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
155 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
156 SOR_PLL_TX_REG_LOAD(3),
157 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
158 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
159 PE_CURRENT1(PE_CURRENT_0_0_mA) |
160 PE_CURRENT2(PE_CURRENT_0_0_mA) |
161 PE_CURRENT3(PE_CURRENT_0_0_mA),
162 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
163 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
164 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
165 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
167 { /* high pixel clock modes */
169 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
170 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
171 SOR_PLL_TX_REG_LOAD(3),
172 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
173 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
174 PE_CURRENT1(PE_CURRENT_6_0_mA) |
175 PE_CURRENT2(PE_CURRENT_6_0_mA) |
176 PE_CURRENT3(PE_CURRENT_6_0_mA),
177 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
178 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
179 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
180 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
184 static const struct tmds_config tegra3_tmds_config[] = {
187 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
188 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
189 SOR_PLL_TX_REG_LOAD(0),
190 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
191 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
192 PE_CURRENT1(PE_CURRENT_0_0_mA) |
193 PE_CURRENT2(PE_CURRENT_0_0_mA) |
194 PE_CURRENT3(PE_CURRENT_0_0_mA),
195 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
196 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
197 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
198 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
199 }, { /* 720p modes */
201 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
202 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
203 SOR_PLL_TX_REG_LOAD(0),
204 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
205 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
206 PE_CURRENT1(PE_CURRENT_5_0_mA) |
207 PE_CURRENT2(PE_CURRENT_5_0_mA) |
208 PE_CURRENT3(PE_CURRENT_5_0_mA),
209 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
210 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
211 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
212 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
213 }, { /* 1080p modes */
215 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
216 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
217 SOR_PLL_TX_REG_LOAD(0),
218 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
219 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
220 PE_CURRENT1(PE_CURRENT_5_0_mA) |
221 PE_CURRENT2(PE_CURRENT_5_0_mA) |
222 PE_CURRENT3(PE_CURRENT_5_0_mA),
223 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
224 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
225 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
226 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
230 static const struct tegra_hdmi_audio_config *
231 tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pclk)
233 const struct tegra_hdmi_audio_config *table;
235 switch (audio_freq) {
237 table = tegra_hdmi_audio_32k;
241 table = tegra_hdmi_audio_44_1k;
245 table = tegra_hdmi_audio_48k;
249 table = tegra_hdmi_audio_88_2k;
253 table = tegra_hdmi_audio_96k;
257 table = tegra_hdmi_audio_176_4k;
261 table = tegra_hdmi_audio_192k;
268 while (table->pclk) {
269 if (table->pclk == pclk)
278 static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
280 const unsigned int freqs[] = {
281 32000, 44100, 48000, 88200, 96000, 176400, 192000
285 for (i = 0; i < ARRAY_SIZE(freqs); i++) {
286 unsigned int f = freqs[i];
287 unsigned int eight_half;
298 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
299 value = AUDIO_FS_LOW(eight_half - delta) |
300 AUDIO_FS_HIGH(eight_half + delta);
301 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
305 static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi, unsigned int pclk)
307 struct device_node *node = hdmi->dev->of_node;
308 const struct tegra_hdmi_audio_config *config;
309 unsigned int offset = 0;
312 switch (hdmi->audio_source) {
314 value = AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
318 value = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
322 value = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
326 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
327 value |= AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
328 AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
329 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
331 value |= AUDIO_CNTRL0_INJECT_NULLSMPL;
332 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
334 value = AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
335 AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
336 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
339 config = tegra_hdmi_get_audio_config(hdmi->audio_freq, pclk);
341 dev_err(hdmi->dev, "cannot set audio to %u at %u pclk\n",
342 hdmi->audio_freq, pclk);
346 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
348 value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
349 AUDIO_N_VALUE(config->n - 1);
350 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
352 tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
353 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
355 value = ACR_SUBPACK_CTS(config->cts);
356 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
358 value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
359 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
361 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
362 value &= ~AUDIO_N_RESETF;
363 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
365 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
366 switch (hdmi->audio_freq) {
368 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320;
372 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441;
376 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480;
380 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882;
384 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960;
388 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764;
392 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920;
396 tegra_hdmi_writel(hdmi, config->aval, offset);
399 tegra_hdmi_setup_audio_fs_tables(hdmi);
404 static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi,
405 unsigned int offset, u8 type,
406 u8 version, void *data, size_t size)
414 /* first byte of data is the checksum */
415 csum = type + version + size - 1;
417 for (i = 1; i < size; i++)
420 ptr[0] = 0x100 - csum;
422 value = INFOFRAME_HEADER_TYPE(type) |
423 INFOFRAME_HEADER_VERSION(version) |
424 INFOFRAME_HEADER_LEN(size - 1);
425 tegra_hdmi_writel(hdmi, value, offset);
427 /* The audio inforame only has one set of subpack registers. The hdmi
428 * block pads the rest of the data as per the spec so we have to fixup
429 * the length before filling in the subpacks.
431 if (offset == HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER)
434 /* each subpack 7 bytes devided into:
435 * subpack_low - bytes 0 - 3
436 * subpack_high - bytes 4 - 6 (with byte 7 padded to 0x00)
438 for (i = 0; i < size; i++) {
439 size_t index = i % 7;
442 memset(subpack, 0x0, sizeof(subpack));
444 ((u8 *)subpack)[index] = ptr[i];
446 if (index == 6 || (i + 1 == size)) {
447 unsigned int reg = offset + 1 + (i / 7) * 2;
449 tegra_hdmi_writel(hdmi, subpack[0], reg);
450 tegra_hdmi_writel(hdmi, subpack[1], reg + 1);
455 static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
456 struct drm_display_mode *mode)
458 struct hdmi_avi_infoframe frame;
459 unsigned int h_front_porch;
460 unsigned int hsize = 16;
461 unsigned int vsize = 9;
464 tegra_hdmi_writel(hdmi, 0,
465 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
469 h_front_porch = mode->hsync_start - mode->hdisplay;
470 memset(&frame, 0, sizeof(frame));
471 frame.r = HDMI_AVI_R_SAME;
473 switch (mode->vdisplay) {
475 if (mode->hdisplay == 640) {
476 frame.m = HDMI_AVI_M_4_3;
479 frame.m = HDMI_AVI_M_16_9;
485 if (((hsize * 10) / vsize) > 14) {
486 frame.m = HDMI_AVI_M_16_9;
489 frame.m = HDMI_AVI_M_4_3;
495 case 1470: /* stereo mode */
496 frame.m = HDMI_AVI_M_16_9;
498 if (h_front_porch == 110)
505 case 2205: /* stereo mode */
506 frame.m = HDMI_AVI_M_16_9;
508 switch (h_front_porch) {
524 frame.m = HDMI_AVI_M_16_9;
529 tegra_hdmi_write_infopack(hdmi, HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER,
530 HDMI_INFOFRAME_TYPE_AVI, HDMI_AVI_VERSION,
531 &frame, sizeof(frame));
533 tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
534 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
537 static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
539 struct hdmi_audio_infoframe frame;
542 tegra_hdmi_writel(hdmi, 0,
543 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
547 memset(&frame, 0, sizeof(frame));
548 frame.cc = HDMI_AUDIO_CC_2;
550 tegra_hdmi_write_infopack(hdmi,
551 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER,
552 HDMI_INFOFRAME_TYPE_AUDIO,
554 &frame, sizeof(frame));
556 tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
557 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
560 static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
562 struct hdmi_stereo_infoframe frame;
566 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
567 value &= ~GENERIC_CTRL_ENABLE;
568 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
572 memset(&frame, 0, sizeof(frame));
576 frame.hdmi_video_format = 2;
578 /* TODO: 74 MHz limit? */
580 frame._3d_structure = 0;
582 frame._3d_structure = 8;
583 frame._3d_ext_data = 0;
586 tegra_hdmi_write_infopack(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_HEADER,
587 HDMI_INFOFRAME_TYPE_VENDOR,
588 HDMI_VENDOR_VERSION, &frame, 6);
590 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
591 value |= GENERIC_CTRL_ENABLE;
592 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
595 static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
596 const struct tmds_config *tmds)
600 tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
601 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
602 tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
604 value = tmds->drive_current | DRIVE_CURRENT_FUSE_OVERRIDE;
605 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
608 static int tegra_output_hdmi_enable(struct tegra_output *output)
610 unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
611 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
612 struct drm_display_mode *mode = &dc->base.mode;
613 struct tegra_hdmi *hdmi = to_hdmi(output);
614 struct device_node *node = hdmi->dev->of_node;
615 unsigned int pulse_start, div82, pclk;
616 const struct tmds_config *tmds;
617 unsigned int num_tmds;
622 pclk = mode->clock * 1000;
623 h_sync_width = mode->hsync_end - mode->hsync_start;
624 h_back_porch = mode->htotal - mode->hsync_end;
625 h_front_porch = mode->hsync_start - mode->hdisplay;
627 err = regulator_enable(hdmi->vdd);
629 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
633 err = regulator_enable(hdmi->pll);
635 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
640 * This assumes that the display controller will divide its parent
641 * clock by 2 to generate the pixel clock.
643 err = tegra_output_setup_clock(output, hdmi->clk, pclk * 2);
645 dev_err(hdmi->dev, "failed to setup clock: %d\n", err);
649 err = clk_set_rate(hdmi->clk, pclk);
653 err = clk_enable(hdmi->clk);
655 dev_err(hdmi->dev, "failed to enable clock: %d\n", err);
659 tegra_periph_reset_assert(hdmi->clk);
660 usleep_range(1000, 2000);
661 tegra_periph_reset_deassert(hdmi->clk);
663 tegra_dc_writel(dc, VSYNC_H_POSITION(1),
664 DC_DISP_DISP_TIMING_OPTIONS);
665 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE888,
666 DC_DISP_DISP_COLOR_CONTROL);
668 /* video_preamble uses h_pulse2 */
669 pulse_start = 1 + h_sync_width + h_back_porch - 10;
671 tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
673 value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
675 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
677 value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
678 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
680 value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
682 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
685 value = HDMI_SRC_DISPLAYB;
687 value = HDMI_SRC_DISPLAYA;
689 if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
690 (mode->vdisplay == 576)))
691 tegra_hdmi_writel(hdmi,
692 value | ARM_VIDEO_RANGE_FULL,
693 HDMI_NV_PDISP_INPUT_CONTROL);
695 tegra_hdmi_writel(hdmi,
696 value | ARM_VIDEO_RANGE_LIMITED,
697 HDMI_NV_PDISP_INPUT_CONTROL);
699 div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
700 value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
701 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
704 err = tegra_hdmi_setup_audio(hdmi, pclk);
709 if (of_device_is_compatible(node, "nvidia,tegra20-hdmi")) {
711 * TODO: add ELD support
715 rekey = HDMI_REKEY_DEFAULT;
716 value = HDMI_CTRL_REKEY(rekey);
717 value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
718 h_front_porch - rekey - 18) / 32);
721 value |= HDMI_CTRL_ENABLE;
723 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
726 tegra_hdmi_writel(hdmi, 0x0,
727 HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
729 tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO,
730 HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
732 tegra_hdmi_setup_avi_infoframe(hdmi, mode);
733 tegra_hdmi_setup_audio_infoframe(hdmi);
734 tegra_hdmi_setup_stereo_infoframe(hdmi);
737 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
738 num_tmds = ARRAY_SIZE(tegra3_tmds_config);
739 tmds = tegra3_tmds_config;
741 num_tmds = ARRAY_SIZE(tegra2_tmds_config);
742 tmds = tegra2_tmds_config;
745 for (i = 0; i < num_tmds; i++) {
746 if (pclk <= tmds[i].pclk) {
747 tegra_hdmi_setup_tmds(hdmi, &tmds[i]);
752 tegra_hdmi_writel(hdmi,
753 SOR_SEQ_CTL_PU_PC(0) |
754 SOR_SEQ_PU_PC_ALT(0) |
756 SOR_SEQ_PD_PC_ALT(8),
757 HDMI_NV_PDISP_SOR_SEQ_CTL);
759 value = SOR_SEQ_INST_WAIT_TIME(1) |
760 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
762 SOR_SEQ_INST_PIN_A_LOW |
763 SOR_SEQ_INST_PIN_B_LOW |
764 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
766 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
767 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
770 value &= ~SOR_CSTM_ROTCLK(~0);
771 value |= SOR_CSTM_ROTCLK(2);
772 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
774 tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
775 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
776 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
779 tegra_hdmi_writel(hdmi,
780 SOR_PWR_NORMAL_STATE_PU |
781 SOR_PWR_NORMAL_START_NORMAL |
782 SOR_PWR_SAFE_STATE_PD |
783 SOR_PWR_SETTING_NEW_TRIGGER,
784 HDMI_NV_PDISP_SOR_PWR);
785 tegra_hdmi_writel(hdmi,
786 SOR_PWR_NORMAL_STATE_PU |
787 SOR_PWR_NORMAL_START_NORMAL |
788 SOR_PWR_SAFE_STATE_PD |
789 SOR_PWR_SETTING_NEW_DONE,
790 HDMI_NV_PDISP_SOR_PWR);
793 BUG_ON(--retries < 0);
794 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
795 } while (value & SOR_PWR_SETTING_NEW_PENDING);
797 value = SOR_STATE_ASY_CRCMODE_COMPLETE |
798 SOR_STATE_ASY_OWNER_HEAD0 |
799 SOR_STATE_ASY_SUBOWNER_BOTH |
800 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
801 SOR_STATE_ASY_DEPOL_POS;
803 /* setup sync polarities */
804 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
805 value |= SOR_STATE_ASY_HSYNCPOL_POS;
807 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
808 value |= SOR_STATE_ASY_HSYNCPOL_NEG;
810 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
811 value |= SOR_STATE_ASY_VSYNCPOL_POS;
813 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
814 value |= SOR_STATE_ASY_VSYNCPOL_NEG;
816 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
818 value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
819 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
821 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
822 tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
823 tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
824 HDMI_NV_PDISP_SOR_STATE1);
825 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
827 tegra_dc_writel(dc, HDMI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
829 value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
830 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
831 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
833 value = DISP_CTRL_MODE_C_DISPLAY;
834 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
836 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
837 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
839 /* TODO: add HDCP support */
844 static int tegra_output_hdmi_disable(struct tegra_output *output)
846 struct tegra_hdmi *hdmi = to_hdmi(output);
848 tegra_periph_reset_assert(hdmi->clk);
849 clk_disable(hdmi->clk);
850 regulator_disable(hdmi->pll);
851 regulator_disable(hdmi->vdd);
856 static int tegra_output_hdmi_setup_clock(struct tegra_output *output,
857 struct clk *clk, unsigned long pclk)
859 struct tegra_hdmi *hdmi = to_hdmi(output);
863 err = clk_set_parent(clk, hdmi->clk_parent);
865 dev_err(output->dev, "failed to set parent: %d\n", err);
869 base = clk_get_parent(hdmi->clk_parent);
872 * This assumes that the parent clock is pll_d_out0 or pll_d2_out
873 * respectively, each of which divides the base pll_d by 2.
875 err = clk_set_rate(base, pclk * 2);
878 "failed to set base clock rate to %lu Hz\n",
884 static int tegra_output_hdmi_check_mode(struct tegra_output *output,
885 struct drm_display_mode *mode,
886 enum drm_mode_status *status)
888 struct tegra_hdmi *hdmi = to_hdmi(output);
889 unsigned long pclk = mode->clock * 1000;
893 parent = clk_get_parent(hdmi->clk_parent);
895 err = clk_round_rate(parent, pclk * 4);
897 *status = MODE_NOCLOCK;
904 static const struct tegra_output_ops hdmi_ops = {
905 .enable = tegra_output_hdmi_enable,
906 .disable = tegra_output_hdmi_disable,
907 .setup_clock = tegra_output_hdmi_setup_clock,
908 .check_mode = tegra_output_hdmi_check_mode,
911 static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
913 struct drm_info_node *node = s->private;
914 struct tegra_hdmi *hdmi = node->info_ent->data;
916 #define DUMP_REG(name) \
917 seq_printf(s, "%-56s %#05x %08lx\n", #name, name, \
918 tegra_hdmi_readl(hdmi, name))
920 DUMP_REG(HDMI_CTXSW);
921 DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
922 DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
923 DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
924 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
925 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
926 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
927 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
928 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
929 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
930 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
931 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
932 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
933 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
934 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
935 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
936 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
937 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
938 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
939 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
940 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
941 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
942 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
943 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
944 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
945 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
946 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
947 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
948 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
949 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
950 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
951 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
952 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
953 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
954 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
955 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
956 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
957 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
958 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
959 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
960 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
961 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
962 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
963 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
964 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
965 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
966 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
967 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
968 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
969 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
970 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
971 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
972 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
973 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
974 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
975 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
976 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
977 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
978 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
979 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
980 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
981 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
982 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
983 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
984 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
985 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
986 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
987 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
988 DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
989 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
990 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
991 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
992 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
993 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
994 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
995 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
996 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
997 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
998 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
999 DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
1000 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
1001 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
1002 DUMP_REG(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL);
1003 DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
1004 DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
1005 DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
1006 DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
1007 DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
1008 DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
1009 DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
1010 DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
1011 DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
1012 DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
1013 DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
1014 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
1015 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(0));
1016 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(1));
1017 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(2));
1018 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(3));
1019 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(4));
1020 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(5));
1021 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(6));
1022 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(7));
1023 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(8));
1024 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(9));
1025 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(10));
1026 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(11));
1027 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(12));
1028 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(13));
1029 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(14));
1030 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(15));
1031 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
1032 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
1033 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
1034 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
1035 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
1036 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
1037 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
1038 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
1039 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
1040 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
1041 DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
1042 DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
1043 DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1044 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
1045 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
1046 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
1047 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
1048 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
1049 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
1050 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
1051 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
1052 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
1053 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
1054 DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
1055 DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
1056 DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
1057 DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
1058 DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
1059 DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
1060 DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
1061 DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
1062 DUMP_REG(HDMI_NV_PDISP_SCRATCH);
1063 DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
1064 DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
1065 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
1066 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
1067 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
1068 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
1069 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
1070 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
1071 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
1072 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
1073 DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
1074 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
1075 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
1076 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
1083 static struct drm_info_list debugfs_files[] = {
1084 { "regs", tegra_hdmi_show_regs, 0, NULL },
1087 static int tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi,
1088 struct drm_minor *minor)
1093 hdmi->debugfs = debugfs_create_dir("hdmi", minor->debugfs_root);
1097 hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1099 if (!hdmi->debugfs_files) {
1104 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1105 hdmi->debugfs_files[i].data = hdmi;
1107 err = drm_debugfs_create_files(hdmi->debugfs_files,
1108 ARRAY_SIZE(debugfs_files),
1109 hdmi->debugfs, minor);
1113 hdmi->minor = minor;
1118 kfree(hdmi->debugfs_files);
1119 hdmi->debugfs_files = NULL;
1121 debugfs_remove(hdmi->debugfs);
1122 hdmi->debugfs = NULL;
1127 static int tegra_hdmi_debugfs_exit(struct tegra_hdmi *hdmi)
1129 drm_debugfs_remove_files(hdmi->debugfs_files, ARRAY_SIZE(debugfs_files),
1133 kfree(hdmi->debugfs_files);
1134 hdmi->debugfs_files = NULL;
1136 debugfs_remove(hdmi->debugfs);
1137 hdmi->debugfs = NULL;
1142 static int tegra_hdmi_drm_init(struct host1x_client *client,
1143 struct drm_device *drm)
1145 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1148 hdmi->output.type = TEGRA_OUTPUT_HDMI;
1149 hdmi->output.dev = client->dev;
1150 hdmi->output.ops = &hdmi_ops;
1152 err = tegra_output_init(drm, &hdmi->output);
1154 dev_err(client->dev, "output setup failed: %d\n", err);
1158 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1159 err = tegra_hdmi_debugfs_init(hdmi, drm->primary);
1161 dev_err(client->dev, "debugfs setup failed: %d\n", err);
1167 static int tegra_hdmi_drm_exit(struct host1x_client *client)
1169 struct tegra_hdmi *hdmi = host1x_client_to_hdmi(client);
1172 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1173 err = tegra_hdmi_debugfs_exit(hdmi);
1175 dev_err(client->dev, "debugfs cleanup failed: %d\n",
1179 err = tegra_output_disable(&hdmi->output);
1181 dev_err(client->dev, "output failed to disable: %d\n", err);
1185 err = tegra_output_exit(&hdmi->output);
1187 dev_err(client->dev, "output cleanup failed: %d\n", err);
1194 static const struct host1x_client_ops hdmi_client_ops = {
1195 .drm_init = tegra_hdmi_drm_init,
1196 .drm_exit = tegra_hdmi_drm_exit,
1199 static int tegra_hdmi_probe(struct platform_device *pdev)
1201 struct host1x *host1x = dev_get_drvdata(pdev->dev.parent);
1202 struct tegra_hdmi *hdmi;
1203 struct resource *regs;
1206 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1210 hdmi->dev = &pdev->dev;
1211 hdmi->audio_source = AUTO;
1212 hdmi->audio_freq = 44100;
1213 hdmi->stereo = false;
1216 hdmi->clk = devm_clk_get(&pdev->dev, NULL);
1217 if (IS_ERR(hdmi->clk)) {
1218 dev_err(&pdev->dev, "failed to get clock\n");
1219 return PTR_ERR(hdmi->clk);
1222 err = clk_prepare(hdmi->clk);
1226 hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1227 if (IS_ERR(hdmi->clk_parent))
1228 return PTR_ERR(hdmi->clk_parent);
1230 err = clk_prepare(hdmi->clk_parent);
1234 err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
1236 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
1240 hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
1241 if (IS_ERR(hdmi->vdd)) {
1242 dev_err(&pdev->dev, "failed to get VDD regulator\n");
1243 return PTR_ERR(hdmi->vdd);
1246 hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
1247 if (IS_ERR(hdmi->pll)) {
1248 dev_err(&pdev->dev, "failed to get PLL regulator\n");
1249 return PTR_ERR(hdmi->pll);
1252 hdmi->output.dev = &pdev->dev;
1254 err = tegra_output_parse_dt(&hdmi->output);
1258 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1262 hdmi->regs = devm_request_and_ioremap(&pdev->dev, regs);
1264 return -EADDRNOTAVAIL;
1266 err = platform_get_irq(pdev, 0);
1272 hdmi->client.ops = &hdmi_client_ops;
1273 INIT_LIST_HEAD(&hdmi->client.list);
1274 hdmi->client.dev = &pdev->dev;
1276 err = host1x_register_client(host1x, &hdmi->client);
1278 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1283 platform_set_drvdata(pdev, hdmi);
1288 static int tegra_hdmi_remove(struct platform_device *pdev)
1290 struct host1x *host1x = dev_get_drvdata(pdev->dev.parent);
1291 struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
1294 err = host1x_unregister_client(host1x, &hdmi->client);
1296 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1301 clk_unprepare(hdmi->clk_parent);
1302 clk_unprepare(hdmi->clk);
1307 static struct of_device_id tegra_hdmi_of_match[] = {
1308 { .compatible = "nvidia,tegra30-hdmi", },
1309 { .compatible = "nvidia,tegra20-hdmi", },
1313 struct platform_driver tegra_hdmi_driver = {
1315 .name = "tegra-hdmi",
1316 .owner = THIS_MODULE,
1317 .of_match_table = tegra_hdmi_of_match,
1319 .probe = tegra_hdmi_probe,
1320 .remove = tegra_hdmi_remove,