2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
11 #define TEGRA_HDMI_H 1
13 #define HDMI_INFOFRAME_TYPE_VENDOR 0x81
14 #define HDMI_INFOFRAME_TYPE_AVI 0x82
15 #define HDMI_INFOFRAME_TYPE_SPD 0x83
16 #define HDMI_INFOFRAME_TYPE_AUDIO 0x84
17 #define HDMI_INFOFRAME_TYPE_MPEG_SRC 0x85
18 #define HDMI_INFOFRAME_TYPE_NTSC_VBI 0x86
20 /* all fields little endian */
21 struct hdmi_avi_infoframe {
26 unsigned s:2; /* scan information */
27 unsigned b:2; /* bar info data valid */
28 unsigned a:1; /* active info present */
29 unsigned y:2; /* RGB or YCbCr */
33 unsigned r:4; /* active format aspect ratio */
34 unsigned m:2; /* picture aspect ratio */
35 unsigned c:2; /* colorimetry */
38 unsigned sc:2; /* scan information */
39 unsigned q:2; /* quantization range */
40 unsigned ec:3; /* extended colorimetry */
41 unsigned itc:1; /* it content */
44 unsigned vic:7; /* video format id code */
48 unsigned pr:4; /* pixel repetition factor */
49 unsigned cn:2; /* it content type*/
50 unsigned yq:2; /* ycc quantization range */
56 u16 bot_bar_start_line;
59 u16 left_bar_end_pixel;
62 u16 right_bar_start_pixel;
65 #define HDMI_AVI_VERSION 0x02
67 #define HDMI_AVI_Y_RGB 0x0
68 #define HDMI_AVI_Y_YCBCR_422 0x1
69 #define HDMI_AVI_Y_YCBCR_444 0x2
71 #define HDMI_AVI_B_VERT 0x1
72 #define HDMI_AVI_B_HORIZ 0x2
74 #define HDMI_AVI_S_NONE 0x0
75 #define HDMI_AVI_S_OVERSCAN 0x1
76 #define HDMI_AVI_S_UNDERSCAN 0x2
78 #define HDMI_AVI_C_NONE 0x0
79 #define HDMI_AVI_C_SMPTE 0x1
80 #define HDMI_AVI_C_ITU_R 0x2
81 #define HDMI_AVI_C_EXTENDED 0x4
83 #define HDMI_AVI_M_4_3 0x1
84 #define HDMI_AVI_M_16_9 0x2
86 #define HDMI_AVI_R_SAME 0x8
87 #define HDMI_AVI_R_4_3_CENTER 0x9
88 #define HDMI_AVI_R_16_9_CENTER 0xa
89 #define HDMI_AVI_R_14_9_CENTER 0xb
91 /* all fields little endian */
92 struct hdmi_audio_infoframe {
97 unsigned cc:3; /* channel count */
99 unsigned ct:4; /* coding type */
102 unsigned ss:2; /* sample size */
103 unsigned sf:3; /* sample frequency */
107 unsigned cxt:5; /* coding extention type */
111 u8 ca; /* channel/speaker allocation */
115 unsigned lsv:4; /* level shift value */
116 unsigned dm_inh:1; /* downmix inhibit */
118 /* PB6-10 reserved */
126 #define HDMI_AUDIO_VERSION 0x01
128 #define HDMI_AUDIO_CC_STREAM 0x0 /* specified by audio stream */
129 #define HDMI_AUDIO_CC_2 0x1
130 #define HDMI_AUDIO_CC_3 0x2
131 #define HDMI_AUDIO_CC_4 0x3
132 #define HDMI_AUDIO_CC_5 0x4
133 #define HDMI_AUDIO_CC_6 0x5
134 #define HDMI_AUDIO_CC_7 0x6
135 #define HDMI_AUDIO_CC_8 0x7
137 #define HDMI_AUDIO_CT_STREAM 0x0 /* specified by audio stream */
138 #define HDMI_AUDIO_CT_PCM 0x1
139 #define HDMI_AUDIO_CT_AC3 0x2
140 #define HDMI_AUDIO_CT_MPEG1 0x3
141 #define HDMI_AUDIO_CT_MP3 0x4
142 #define HDMI_AUDIO_CT_MPEG2 0x5
143 #define HDMI_AUDIO_CT_AAC_LC 0x6
144 #define HDMI_AUDIO_CT_DTS 0x7
145 #define HDMI_AUDIO_CT_ATRAC 0x8
146 #define HDMI_AUDIO_CT_DSD 0x9
147 #define HDMI_AUDIO_CT_E_AC3 0xa
148 #define HDMI_AUDIO_CT_DTS_HD 0xb
149 #define HDMI_AUDIO_CT_MLP 0xc
150 #define HDMI_AUDIO_CT_DST 0xd
151 #define HDMI_AUDIO_CT_WMA_PRO 0xe
152 #define HDMI_AUDIO_CT_CXT 0xf
154 #define HDMI_AUDIO_SF_STREAM 0x0 /* specified by audio stream */
155 #define HDMI_AUIDO_SF_32K 0x1
156 #define HDMI_AUDIO_SF_44_1K 0x2
157 #define HDMI_AUDIO_SF_48K 0x3
158 #define HDMI_AUDIO_SF_88_2K 0x4
159 #define HDMI_AUDIO_SF_96K 0x5
160 #define HDMI_AUDIO_SF_176_4K 0x6
161 #define HDMI_AUDIO_SF_192K 0x7
163 #define HDMI_AUDIO_SS_STREAM 0x0 /* specified by audio stream */
164 #define HDMI_AUDIO_SS_16BIT 0x1
165 #define HDMI_AUDIO_SS_20BIT 0x2
166 #define HDMI_AUDIO_SS_24BIT 0x3
168 #define HDMI_AUDIO_CXT_CT 0x0 /* refer to coding in CT */
169 #define HDMI_AUDIO_CXT_HE_AAC 0x1
170 #define HDMI_AUDIO_CXT_HE_AAC_V2 0x2
171 #define HDMI_AUDIO_CXT_MPEG_SURROUND 0x3
173 /* all fields little endian */
174 struct hdmi_stereo_infoframe {
189 unsigned hdmi_video_format:3;
193 unsigned _3d_structure:4;
197 unsigned _3d_ext_data:4;
200 #define HDMI_VENDOR_VERSION 0x01
202 /* register definitions */
203 #define HDMI_CTXSW 0x00
205 #define HDMI_NV_PDISP_SOR_STATE0 0x01
206 #define SOR_STATE_UPDATE (1 << 0)
208 #define HDMI_NV_PDISP_SOR_STATE1 0x02
209 #define SOR_STATE_ASY_HEAD_OPMODE_AWAKE (2 << 0)
210 #define SOR_STATE_ASY_ORMODE_NORMAL (1 << 2)
211 #define SOR_STATE_ATTACHED (1 << 3)
213 #define HDMI_NV_PDISP_SOR_STATE2 0x03
214 #define SOR_STATE_ASY_OWNER_NONE (0 << 0)
215 #define SOR_STATE_ASY_OWNER_HEAD0 (1 << 0)
216 #define SOR_STATE_ASY_SUBOWNER_NONE (0 << 4)
217 #define SOR_STATE_ASY_SUBOWNER_SUBHEAD0 (1 << 4)
218 #define SOR_STATE_ASY_SUBOWNER_SUBHEAD1 (2 << 4)
219 #define SOR_STATE_ASY_SUBOWNER_BOTH (3 << 4)
220 #define SOR_STATE_ASY_CRCMODE_ACTIVE (0 << 6)
221 #define SOR_STATE_ASY_CRCMODE_COMPLETE (1 << 6)
222 #define SOR_STATE_ASY_CRCMODE_NON_ACTIVE (2 << 6)
223 #define SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A (1 << 8)
224 #define SOR_STATE_ASY_PROTOCOL_CUSTOM (15 << 8)
225 #define SOR_STATE_ASY_HSYNCPOL_POS (0 << 12)
226 #define SOR_STATE_ASY_HSYNCPOL_NEG (1 << 12)
227 #define SOR_STATE_ASY_VSYNCPOL_POS (0 << 13)
228 #define SOR_STATE_ASY_VSYNCPOL_NEG (1 << 13)
229 #define SOR_STATE_ASY_DEPOL_POS (0 << 14)
230 #define SOR_STATE_ASY_DEPOL_NEG (1 << 14)
232 #define HDMI_NV_PDISP_RG_HDCP_AN_MSB 0x04
233 #define HDMI_NV_PDISP_RG_HDCP_AN_LSB 0x05
234 #define HDMI_NV_PDISP_RG_HDCP_CN_MSB 0x06
235 #define HDMI_NV_PDISP_RG_HDCP_CN_LSB 0x07
236 #define HDMI_NV_PDISP_RG_HDCP_AKSV_MSB 0x08
237 #define HDMI_NV_PDISP_RG_HDCP_AKSV_LSB 0x09
238 #define HDMI_NV_PDISP_RG_HDCP_BKSV_MSB 0x0a
239 #define HDMI_NV_PDISP_RG_HDCP_BKSV_LSB 0x0b
240 #define HDMI_NV_PDISP_RG_HDCP_CKSV_MSB 0x0c
241 #define HDMI_NV_PDISP_RG_HDCP_CKSV_LSB 0x0d
242 #define HDMI_NV_PDISP_RG_HDCP_DKSV_MSB 0x0e
243 #define HDMI_NV_PDISP_RG_HDCP_DKSV_LSB 0x0f
244 #define HDMI_NV_PDISP_RG_HDCP_CTRL 0x10
245 #define HDMI_NV_PDISP_RG_HDCP_CMODE 0x11
246 #define HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB 0x12
247 #define HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB 0x13
248 #define HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB 0x14
249 #define HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2 0x15
250 #define HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1 0x16
251 #define HDMI_NV_PDISP_RG_HDCP_RI 0x17
252 #define HDMI_NV_PDISP_RG_HDCP_CS_MSB 0x18
253 #define HDMI_NV_PDISP_RG_HDCP_CS_LSB 0x19
254 #define HDMI_NV_PDISP_HDMI_AUDIO_EMU0 0x1a
255 #define HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0 0x1b
256 #define HDMI_NV_PDISP_HDMI_AUDIO_EMU1 0x1c
257 #define HDMI_NV_PDISP_HDMI_AUDIO_EMU2 0x1d
259 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL 0x1e
260 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS 0x1f
261 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER 0x20
262 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW 0x21
263 #define HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH 0x22
264 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL 0x23
265 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS 0x24
266 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER 0x25
267 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW 0x26
268 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH 0x27
269 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW 0x28
270 #define HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH 0x29
272 #define INFOFRAME_CTRL_ENABLE (1 << 0)
274 #define INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0)
275 #define INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8)
276 #define INFOFRAME_HEADER_LEN(x) (((x) & 0x0f) << 16)
278 #define HDMI_NV_PDISP_HDMI_GENERIC_CTRL 0x2a
279 #define GENERIC_CTRL_ENABLE (1 << 0)
280 #define GENERIC_CTRL_OTHER (1 << 4)
281 #define GENERIC_CTRL_SINGLE (1 << 8)
282 #define GENERIC_CTRL_HBLANK (1 << 12)
283 #define GENERIC_CTRL_AUDIO (1 << 16)
285 #define HDMI_NV_PDISP_HDMI_GENERIC_STATUS 0x2b
286 #define HDMI_NV_PDISP_HDMI_GENERIC_HEADER 0x2c
287 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW 0x2d
288 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH 0x2e
289 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW 0x2f
290 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH 0x30
291 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW 0x31
292 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH 0x32
293 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW 0x33
294 #define HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH 0x34
296 #define HDMI_NV_PDISP_HDMI_ACR_CTRL 0x35
297 #define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW 0x36
298 #define HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH 0x37
299 #define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW 0x38
300 #define HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH 0x39
301 #define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW 0x3a
302 #define HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH 0x3b
303 #define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW 0x3c
304 #define HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH 0x3d
305 #define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW 0x3e
306 #define HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH 0x3f
307 #define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW 0x40
308 #define HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH 0x41
309 #define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW 0x42
310 #define HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH 0x43
312 #define ACR_SUBPACK_CTS(x) (((x) & 0xffffff) << 8)
313 #define ACR_SUBPACK_N(x) (((x) & 0xffffff) << 0)
314 #define ACR_ENABLE (1 << 31)
316 #define HDMI_NV_PDISP_HDMI_CTRL 0x44
317 #define HDMI_CTRL_REKEY(x) (((x) & 0x7f) << 0)
318 #define HDMI_CTRL_MAX_AC_PACKET(x) (((x) & 0x1f) << 16)
319 #define HDMI_CTRL_ENABLE (1 << 30)
321 #define HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT 0x45
322 #define HDMI_NV_PDISP_HDMI_VSYNC_WINDOW 0x46
323 #define VSYNC_WINDOW_END(x) (((x) & 0x3ff) << 0)
324 #define VSYNC_WINDOW_START(x) (((x) & 0x3ff) << 16)
325 #define VSYNC_WINDOW_ENABLE (1 << 31)
327 #define HDMI_NV_PDISP_HDMI_GCP_CTRL 0x47
328 #define HDMI_NV_PDISP_HDMI_GCP_STATUS 0x48
329 #define HDMI_NV_PDISP_HDMI_GCP_SUBPACK 0x49
330 #define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1 0x4a
331 #define HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2 0x4b
332 #define HDMI_NV_PDISP_HDMI_EMU0 0x4c
333 #define HDMI_NV_PDISP_HDMI_EMU1 0x4d
334 #define HDMI_NV_PDISP_HDMI_EMU1_RDATA 0x4e
336 #define HDMI_NV_PDISP_HDMI_SPARE 0x4f
337 #define SPARE_HW_CTS (1 << 0)
338 #define SPARE_FORCE_SW_CTS (1 << 1)
339 #define SPARE_CTS_RESET_VAL(x) (((x) & 0x7) << 16)
341 #define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1 0x50
342 #define HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2 0x51
343 #define HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL 0x53
344 #define HDMI_NV_PDISP_SOR_CAP 0x54
345 #define HDMI_NV_PDISP_SOR_PWR 0x55
346 #define SOR_PWR_NORMAL_STATE_PD (0 << 0)
347 #define SOR_PWR_NORMAL_STATE_PU (1 << 0)
348 #define SOR_PWR_NORMAL_START_NORMAL (0 << 1)
349 #define SOR_PWR_NORMAL_START_ALT (1 << 1)
350 #define SOR_PWR_SAFE_STATE_PD (0 << 16)
351 #define SOR_PWR_SAFE_STATE_PU (1 << 16)
352 #define SOR_PWR_SETTING_NEW_DONE (0 << 31)
353 #define SOR_PWR_SETTING_NEW_PENDING (1 << 31)
354 #define SOR_PWR_SETTING_NEW_TRIGGER (1 << 31)
356 #define HDMI_NV_PDISP_SOR_TEST 0x56
357 #define HDMI_NV_PDISP_SOR_PLL0 0x57
358 #define SOR_PLL_PWR (1 << 0)
359 #define SOR_PLL_PDBG (1 << 1)
360 #define SOR_PLL_VCAPD (1 << 2)
361 #define SOR_PLL_PDPORT (1 << 3)
362 #define SOR_PLL_RESISTORSEL (1 << 4)
363 #define SOR_PLL_PULLDOWN (1 << 5)
364 #define SOR_PLL_VCOCAP(x) (((x) & 0xf) << 8)
365 #define SOR_PLL_BG_V17_S(x) (((x) & 0xf) << 12)
366 #define SOR_PLL_FILTER(x) (((x) & 0xf) << 16)
367 #define SOR_PLL_ICHPMP(x) (((x) & 0xf) << 24)
368 #define SOR_PLL_TX_REG_LOAD(x) (((x) & 0xf) << 28)
370 #define HDMI_NV_PDISP_SOR_PLL1 0x58
371 #define SOR_PLL_TMDS_TERM_ENABLE (1 << 8)
372 #define SOR_PLL_TMDS_TERMADJ(x) (((x) & 0xf) << 9)
373 #define SOR_PLL_LOADADJ(x) (((x) & 0xf) << 20)
374 #define SOR_PLL_PE_EN (1 << 28)
375 #define SOR_PLL_HALF_FULL_PE (1 << 29)
376 #define SOR_PLL_S_D_PIN_PE (1 << 30)
378 #define HDMI_NV_PDISP_SOR_PLL2 0x59
380 #define HDMI_NV_PDISP_SOR_CSTM 0x5a
381 #define SOR_CSTM_ROTCLK(x) (((x) & 0xf) << 24)
383 #define HDMI_NV_PDISP_SOR_LVDS 0x5b
384 #define HDMI_NV_PDISP_SOR_CRCA 0x5c
385 #define HDMI_NV_PDISP_SOR_CRCB 0x5d
386 #define HDMI_NV_PDISP_SOR_BLANK 0x5e
387 #define HDMI_NV_PDISP_SOR_SEQ_CTL 0x5f
388 #define SOR_SEQ_CTL_PU_PC(x) (((x) & 0xf) << 0)
389 #define SOR_SEQ_PU_PC_ALT(x) (((x) & 0xf) << 4)
390 #define SOR_SEQ_PD_PC(x) (((x) & 0xf) << 8)
391 #define SOR_SEQ_PD_PC_ALT(x) (((x) & 0xf) << 12)
392 #define SOR_SEQ_PC(x) (((x) & 0xf) << 16)
393 #define SOR_SEQ_STATUS (1 << 28)
394 #define SOR_SEQ_SWITCH (1 << 30)
396 #define HDMI_NV_PDISP_SOR_SEQ_INST(x) (0x60 + (x))
398 #define SOR_SEQ_INST_WAIT_TIME(x) (((x) & 0x3ff) << 0)
399 #define SOR_SEQ_INST_WAIT_UNITS_VSYNC (2 << 12)
400 #define SOR_SEQ_INST_HALT (1 << 15)
401 #define SOR_SEQ_INST_PIN_A_LOW (0 << 21)
402 #define SOR_SEQ_INST_PIN_A_HIGH (1 << 21)
403 #define SOR_SEQ_INST_PIN_B_LOW (0 << 22)
404 #define SOR_SEQ_INST_PIN_B_HIGH (1 << 22)
405 #define SOR_SEQ_INST_DRIVE_PWM_OUT_LO (1 << 23)
407 #define HDMI_NV_PDISP_SOR_VCRCA0 0x72
408 #define HDMI_NV_PDISP_SOR_VCRCA1 0x73
409 #define HDMI_NV_PDISP_SOR_CCRCA0 0x74
410 #define HDMI_NV_PDISP_SOR_CCRCA1 0x75
411 #define HDMI_NV_PDISP_SOR_EDATAA0 0x76
412 #define HDMI_NV_PDISP_SOR_EDATAA1 0x77
413 #define HDMI_NV_PDISP_SOR_COUNTA0 0x78
414 #define HDMI_NV_PDISP_SOR_COUNTA1 0x79
415 #define HDMI_NV_PDISP_SOR_DEBUGA0 0x7a
416 #define HDMI_NV_PDISP_SOR_DEBUGA1 0x7b
417 #define HDMI_NV_PDISP_SOR_TRIG 0x7c
418 #define HDMI_NV_PDISP_SOR_MSCHECK 0x7d
420 #define HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT 0x7e
421 #define DRIVE_CURRENT_LANE0(x) (((x) & 0x3f) << 0)
422 #define DRIVE_CURRENT_LANE1(x) (((x) & 0x3f) << 8)
423 #define DRIVE_CURRENT_LANE2(x) (((x) & 0x3f) << 16)
424 #define DRIVE_CURRENT_LANE3(x) (((x) & 0x3f) << 24)
425 #define DRIVE_CURRENT_FUSE_OVERRIDE (1 << 31)
427 #define DRIVE_CURRENT_1_500_mA 0x00
428 #define DRIVE_CURRENT_1_875_mA 0x01
429 #define DRIVE_CURRENT_2_250_mA 0x02
430 #define DRIVE_CURRENT_2_625_mA 0x03
431 #define DRIVE_CURRENT_3_000_mA 0x04
432 #define DRIVE_CURRENT_3_375_mA 0x05
433 #define DRIVE_CURRENT_3_750_mA 0x06
434 #define DRIVE_CURRENT_4_125_mA 0x07
435 #define DRIVE_CURRENT_4_500_mA 0x08
436 #define DRIVE_CURRENT_4_875_mA 0x09
437 #define DRIVE_CURRENT_5_250_mA 0x0a
438 #define DRIVE_CURRENT_5_625_mA 0x0b
439 #define DRIVE_CURRENT_6_000_mA 0x0c
440 #define DRIVE_CURRENT_6_375_mA 0x0d
441 #define DRIVE_CURRENT_6_750_mA 0x0e
442 #define DRIVE_CURRENT_7_125_mA 0x0f
443 #define DRIVE_CURRENT_7_500_mA 0x10
444 #define DRIVE_CURRENT_7_875_mA 0x11
445 #define DRIVE_CURRENT_8_250_mA 0x12
446 #define DRIVE_CURRENT_8_625_mA 0x13
447 #define DRIVE_CURRENT_9_000_mA 0x14
448 #define DRIVE_CURRENT_9_375_mA 0x15
449 #define DRIVE_CURRENT_9_750_mA 0x16
450 #define DRIVE_CURRENT_10_125_mA 0x17
451 #define DRIVE_CURRENT_10_500_mA 0x18
452 #define DRIVE_CURRENT_10_875_mA 0x19
453 #define DRIVE_CURRENT_11_250_mA 0x1a
454 #define DRIVE_CURRENT_11_625_mA 0x1b
455 #define DRIVE_CURRENT_12_000_mA 0x1c
456 #define DRIVE_CURRENT_12_375_mA 0x1d
457 #define DRIVE_CURRENT_12_750_mA 0x1e
458 #define DRIVE_CURRENT_13_125_mA 0x1f
459 #define DRIVE_CURRENT_13_500_mA 0x20
460 #define DRIVE_CURRENT_13_875_mA 0x21
461 #define DRIVE_CURRENT_14_250_mA 0x22
462 #define DRIVE_CURRENT_14_625_mA 0x23
463 #define DRIVE_CURRENT_15_000_mA 0x24
464 #define DRIVE_CURRENT_15_375_mA 0x25
465 #define DRIVE_CURRENT_15_750_mA 0x26
466 #define DRIVE_CURRENT_16_125_mA 0x27
467 #define DRIVE_CURRENT_16_500_mA 0x28
468 #define DRIVE_CURRENT_16_875_mA 0x29
469 #define DRIVE_CURRENT_17_250_mA 0x2a
470 #define DRIVE_CURRENT_17_625_mA 0x2b
471 #define DRIVE_CURRENT_18_000_mA 0x2c
472 #define DRIVE_CURRENT_18_375_mA 0x2d
473 #define DRIVE_CURRENT_18_750_mA 0x2e
474 #define DRIVE_CURRENT_19_125_mA 0x2f
475 #define DRIVE_CURRENT_19_500_mA 0x30
476 #define DRIVE_CURRENT_19_875_mA 0x31
477 #define DRIVE_CURRENT_20_250_mA 0x32
478 #define DRIVE_CURRENT_20_625_mA 0x33
479 #define DRIVE_CURRENT_21_000_mA 0x34
480 #define DRIVE_CURRENT_21_375_mA 0x35
481 #define DRIVE_CURRENT_21_750_mA 0x36
482 #define DRIVE_CURRENT_22_125_mA 0x37
483 #define DRIVE_CURRENT_22_500_mA 0x38
484 #define DRIVE_CURRENT_22_875_mA 0x39
485 #define DRIVE_CURRENT_23_250_mA 0x3a
486 #define DRIVE_CURRENT_23_625_mA 0x3b
487 #define DRIVE_CURRENT_24_000_mA 0x3c
488 #define DRIVE_CURRENT_24_375_mA 0x3d
489 #define DRIVE_CURRENT_24_750_mA 0x3e
491 #define HDMI_NV_PDISP_AUDIO_DEBUG0 0x7f
492 #define HDMI_NV_PDISP_AUDIO_DEBUG1 0x80
493 #define HDMI_NV_PDISP_AUDIO_DEBUG2 0x81
495 #define HDMI_NV_PDISP_AUDIO_FS(x) (0x82 + (x))
496 #define AUDIO_FS_LOW(x) (((x) & 0xfff) << 0)
497 #define AUDIO_FS_HIGH(x) (((x) & 0xfff) << 16)
499 #define HDMI_NV_PDISP_AUDIO_PULSE_WIDTH 0x89
500 #define HDMI_NV_PDISP_AUDIO_THRESHOLD 0x8a
501 #define HDMI_NV_PDISP_AUDIO_CNTRL0 0x8b
502 #define AUDIO_CNTRL0_ERROR_TOLERANCE(x) (((x) & 0xff) << 0)
503 #define AUDIO_CNTRL0_SOURCE_SELECT_AUTO (0 << 20)
504 #define AUDIO_CNTRL0_SOURCE_SELECT_SPDIF (1 << 20)
505 #define AUDIO_CNTRL0_SOURCE_SELECT_HDAL (2 << 20)
506 #define AUDIO_CNTRL0_FRAMES_PER_BLOCK(x) (((x) & 0xff) << 24)
508 #define HDMI_NV_PDISP_AUDIO_N 0x8c
509 #define AUDIO_N_VALUE(x) (((x) & 0xfffff) << 0)
510 #define AUDIO_N_RESETF (1 << 20)
511 #define AUDIO_N_GENERATE_NORMAL (0 << 24)
512 #define AUDIO_N_GENERATE_ALTERNATE (1 << 24)
514 #define HDMI_NV_PDISP_HDCPRIF_ROM_TIMING 0x94
515 #define HDMI_NV_PDISP_SOR_REFCLK 0x95
516 #define SOR_REFCLK_DIV_INT(x) (((x) & 0xff) << 8)
517 #define SOR_REFCLK_DIV_FRAC(x) (((x) & 0x03) << 6)
519 #define HDMI_NV_PDISP_CRC_CONTROL 0x96
520 #define HDMI_NV_PDISP_INPUT_CONTROL 0x97
521 #define HDMI_SRC_DISPLAYA (0 << 0)
522 #define HDMI_SRC_DISPLAYB (1 << 0)
523 #define ARM_VIDEO_RANGE_FULL (0 << 1)
524 #define ARM_VIDEO_RANGE_LIMITED (1 << 1)
526 #define HDMI_NV_PDISP_SCRATCH 0x98
527 #define HDMI_NV_PDISP_PE_CURRENT 0x99
528 #define PE_CURRENT0(x) (((x) & 0xf) << 0)
529 #define PE_CURRENT1(x) (((x) & 0xf) << 8)
530 #define PE_CURRENT2(x) (((x) & 0xf) << 16)
531 #define PE_CURRENT3(x) (((x) & 0xf) << 24)
533 #define PE_CURRENT_0_0_mA 0x0
534 #define PE_CURRENT_0_5_mA 0x1
535 #define PE_CURRENT_1_0_mA 0x2
536 #define PE_CURRENT_1_5_mA 0x3
537 #define PE_CURRENT_2_0_mA 0x4
538 #define PE_CURRENT_2_5_mA 0x5
539 #define PE_CURRENT_3_0_mA 0x6
540 #define PE_CURRENT_3_5_mA 0x7
541 #define PE_CURRENT_4_0_mA 0x8
542 #define PE_CURRENT_4_5_mA 0x9
543 #define PE_CURRENT_5_0_mA 0xa
544 #define PE_CURRENT_5_5_mA 0xb
545 #define PE_CURRENT_6_0_mA 0xc
546 #define PE_CURRENT_6_5_mA 0xd
547 #define PE_CURRENT_7_0_mA 0xe
548 #define PE_CURRENT_7_5_mA 0xf
550 #define HDMI_NV_PDISP_KEY_CTRL 0x9a
551 #define HDMI_NV_PDISP_KEY_DEBUG0 0x9b
552 #define HDMI_NV_PDISP_KEY_DEBUG1 0x9c
553 #define HDMI_NV_PDISP_KEY_DEBUG2 0x9d
554 #define HDMI_NV_PDISP_KEY_HDCP_KEY_0 0x9e
555 #define HDMI_NV_PDISP_KEY_HDCP_KEY_1 0x9f
556 #define HDMI_NV_PDISP_KEY_HDCP_KEY_2 0xa0
557 #define HDMI_NV_PDISP_KEY_HDCP_KEY_3 0xa1
558 #define HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG 0xa2
559 #define HDMI_NV_PDISP_KEY_SKEY_INDEX 0xa3
561 #define HDMI_NV_PDISP_SOR_AUDIO_CNTRL0 0xac
562 #define AUDIO_CNTRL0_INJECT_NULLSMPL (1 << 29)
563 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR 0xbc
564 #define HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE 0xbd
566 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320 0xbf
567 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441 0xc0
568 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882 0xc1
569 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764 0xc2
570 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480 0xc3
571 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960 0xc4
572 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920 0xc5
573 #define HDMI_NV_PDISP_SOR_AUDIO_AVAL_DEFAULT 0xc5
575 #endif /* TEGRA_HDMI_H */