2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <linux/clk.h>
12 #include <drm/drm_panel.h>
18 struct tegra_output output;
22 struct clk *clk_parent;
26 static inline struct tegra_rgb *to_rgb(struct tegra_output *output)
28 return container_of(output, struct tegra_rgb, output);
36 static const struct reg_entry rgb_enable[] = {
37 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x00000000 },
38 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x00000000 },
39 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x00000000 },
40 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x00000000 },
41 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
42 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x01000000 },
43 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
44 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
45 { DC_COM_PIN_OUTPUT_DATA(0), 0x00000000 },
46 { DC_COM_PIN_OUTPUT_DATA(1), 0x00000000 },
47 { DC_COM_PIN_OUTPUT_DATA(2), 0x00000000 },
48 { DC_COM_PIN_OUTPUT_DATA(3), 0x00000000 },
49 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
50 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
51 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
52 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
53 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00210222 },
54 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00002200 },
55 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00020000 },
58 static const struct reg_entry rgb_disable[] = {
59 { DC_COM_PIN_OUTPUT_SELECT(6), 0x00000000 },
60 { DC_COM_PIN_OUTPUT_SELECT(5), 0x00000000 },
61 { DC_COM_PIN_OUTPUT_SELECT(4), 0x00000000 },
62 { DC_COM_PIN_OUTPUT_SELECT(3), 0x00000000 },
63 { DC_COM_PIN_OUTPUT_SELECT(2), 0x00000000 },
64 { DC_COM_PIN_OUTPUT_SELECT(1), 0x00000000 },
65 { DC_COM_PIN_OUTPUT_SELECT(0), 0x00000000 },
66 { DC_COM_PIN_OUTPUT_DATA(3), 0xaaaaaaaa },
67 { DC_COM_PIN_OUTPUT_DATA(2), 0xaaaaaaaa },
68 { DC_COM_PIN_OUTPUT_DATA(1), 0xaaaaaaaa },
69 { DC_COM_PIN_OUTPUT_DATA(0), 0xaaaaaaaa },
70 { DC_COM_PIN_OUTPUT_POLARITY(3), 0x00000000 },
71 { DC_COM_PIN_OUTPUT_POLARITY(2), 0x00000000 },
72 { DC_COM_PIN_OUTPUT_POLARITY(1), 0x00000000 },
73 { DC_COM_PIN_OUTPUT_POLARITY(0), 0x00000000 },
74 { DC_COM_PIN_OUTPUT_ENABLE(3), 0x55555555 },
75 { DC_COM_PIN_OUTPUT_ENABLE(2), 0x55555555 },
76 { DC_COM_PIN_OUTPUT_ENABLE(1), 0x55150005 },
77 { DC_COM_PIN_OUTPUT_ENABLE(0), 0x55555555 },
80 static void tegra_dc_write_regs(struct tegra_dc *dc,
81 const struct reg_entry *table,
86 for (i = 0; i < num; i++)
87 tegra_dc_writel(dc, table[i].value, table[i].offset);
90 static void tegra_rgb_connector_dpms(struct drm_connector *connector,
95 static const struct drm_connector_funcs tegra_rgb_connector_funcs = {
96 .dpms = tegra_rgb_connector_dpms,
97 .detect = tegra_output_connector_detect,
98 .fill_modes = drm_helper_probe_single_connector_modes,
99 .destroy = tegra_output_connector_destroy,
102 static enum drm_mode_status
103 tegra_rgb_connector_mode_valid(struct drm_connector *connector,
104 struct drm_display_mode *mode)
107 * FIXME: For now, always assume that the mode is okay. There are
108 * unresolved issues with clk_round_rate(), which doesn't always
109 * reliably report whether a frequency can be set or not.
114 static const struct drm_connector_helper_funcs tegra_rgb_connector_helper_funcs = {
115 .get_modes = tegra_output_connector_get_modes,
116 .mode_valid = tegra_rgb_connector_mode_valid,
117 .best_encoder = tegra_output_connector_best_encoder,
120 static const struct drm_encoder_funcs tegra_rgb_encoder_funcs = {
121 .destroy = tegra_output_encoder_destroy,
124 static void tegra_rgb_encoder_dpms(struct drm_encoder *encoder, int mode)
128 static bool tegra_rgb_encoder_mode_fixup(struct drm_encoder *encoder,
129 const struct drm_display_mode *mode,
130 struct drm_display_mode *adjusted)
132 struct tegra_output *output = encoder_to_output(encoder);
133 unsigned long pclk = mode->clock * 1000;
134 struct tegra_rgb *rgb = to_rgb(output);
139 * We may not want to change the frequency of the parent clock, since
140 * it may be a parent for other peripherals. This is due to the fact
141 * that on Tegra20 there's only a single clock dedicated to display
142 * (pll_d_out0), whereas later generations have a second one that can
143 * be used to independently drive a second output (pll_d2_out0).
145 * As a way to support multiple outputs on Tegra20 as well, pll_p is
146 * typically used as the parent clock for the display controllers.
147 * But this comes at a cost: pll_p is the parent of several other
148 * peripherals, so its frequency shouldn't change out of the blue.
150 * The best we can do at this point is to use the shift clock divider
151 * and hope that the desired frequency can be matched (or at least
152 * matched sufficiently close that the panel will still work).
154 div = ((clk_get_rate(rgb->clk) * 2) / pclk) - 2;
156 err = tegra_dc_setup_clock(rgb->dc, rgb->clk_parent, pclk, div);
158 dev_err(output->dev, "failed to setup DC clock: %d\n", err);
165 static void tegra_rgb_encoder_prepare(struct drm_encoder *encoder)
169 static void tegra_rgb_encoder_commit(struct drm_encoder *encoder)
173 static void tegra_rgb_encoder_mode_set(struct drm_encoder *encoder,
174 struct drm_display_mode *mode,
175 struct drm_display_mode *adjusted)
177 struct tegra_output *output = encoder_to_output(encoder);
178 struct tegra_rgb *rgb = to_rgb(output);
182 drm_panel_prepare(output->panel);
184 tegra_dc_write_regs(rgb->dc, rgb_enable, ARRAY_SIZE(rgb_enable));
186 value = DE_SELECT_ACTIVE | DE_CONTROL_NORMAL;
187 tegra_dc_writel(rgb->dc, value, DC_DISP_DATA_ENABLE_OPTIONS);
189 /* XXX: parameterize? */
190 value = tegra_dc_readl(rgb->dc, DC_COM_PIN_OUTPUT_POLARITY(1));
191 value &= ~LVS_OUTPUT_POLARITY_LOW;
192 value &= ~LHS_OUTPUT_POLARITY_LOW;
193 tegra_dc_writel(rgb->dc, value, DC_COM_PIN_OUTPUT_POLARITY(1));
195 /* XXX: parameterize? */
196 value = DISP_DATA_FORMAT_DF1P1C | DISP_ALIGNMENT_MSB |
198 tegra_dc_writel(rgb->dc, value, DC_DISP_DISP_INTERFACE_CONTROL);
200 /* XXX: parameterize? */
201 value = SC0_H_QUALIFIER_NONE | SC1_H_QUALIFIER_NONE;
202 tegra_dc_writel(rgb->dc, value, DC_DISP_SHIFT_CLOCK_OPTIONS);
204 value = tegra_dc_readl(rgb->dc, DC_CMD_DISPLAY_COMMAND);
205 value &= ~DISP_CTRL_MODE_MASK;
206 value |= DISP_CTRL_MODE_C_DISPLAY;
207 tegra_dc_writel(rgb->dc, value, DC_CMD_DISPLAY_COMMAND);
209 value = tegra_dc_readl(rgb->dc, DC_CMD_DISPLAY_POWER_CONTROL);
210 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
211 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
212 tegra_dc_writel(rgb->dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
214 tegra_dc_commit(rgb->dc);
217 drm_panel_enable(output->panel);
220 static void tegra_rgb_encoder_disable(struct drm_encoder *encoder)
222 struct tegra_output *output = encoder_to_output(encoder);
223 struct tegra_rgb *rgb = to_rgb(output);
226 drm_panel_disable(output->panel);
228 tegra_dc_write_regs(rgb->dc, rgb_disable, ARRAY_SIZE(rgb_disable));
231 drm_panel_unprepare(output->panel);
234 static const struct drm_encoder_helper_funcs tegra_rgb_encoder_helper_funcs = {
235 .dpms = tegra_rgb_encoder_dpms,
236 .mode_fixup = tegra_rgb_encoder_mode_fixup,
237 .prepare = tegra_rgb_encoder_prepare,
238 .commit = tegra_rgb_encoder_commit,
239 .mode_set = tegra_rgb_encoder_mode_set,
240 .disable = tegra_rgb_encoder_disable,
243 int tegra_dc_rgb_probe(struct tegra_dc *dc)
245 struct device_node *np;
246 struct tegra_rgb *rgb;
249 np = of_get_child_by_name(dc->dev->of_node, "rgb");
250 if (!np || !of_device_is_available(np))
253 rgb = devm_kzalloc(dc->dev, sizeof(*rgb), GFP_KERNEL);
257 rgb->output.dev = dc->dev;
258 rgb->output.of_node = np;
261 err = tegra_output_probe(&rgb->output);
265 rgb->clk = devm_clk_get(dc->dev, NULL);
266 if (IS_ERR(rgb->clk)) {
267 dev_err(dc->dev, "failed to get clock\n");
268 return PTR_ERR(rgb->clk);
271 rgb->clk_parent = devm_clk_get(dc->dev, "parent");
272 if (IS_ERR(rgb->clk_parent)) {
273 dev_err(dc->dev, "failed to get parent clock\n");
274 return PTR_ERR(rgb->clk_parent);
277 err = clk_set_parent(rgb->clk, rgb->clk_parent);
279 dev_err(dc->dev, "failed to set parent clock: %d\n", err);
283 dc->rgb = &rgb->output;
288 int tegra_dc_rgb_remove(struct tegra_dc *dc)
295 err = tegra_output_remove(dc->rgb);
304 int tegra_dc_rgb_init(struct drm_device *drm, struct tegra_dc *dc)
306 struct tegra_output *output = dc->rgb;
312 drm_connector_init(drm, &output->connector, &tegra_rgb_connector_funcs,
313 DRM_MODE_CONNECTOR_LVDS);
314 drm_connector_helper_add(&output->connector,
315 &tegra_rgb_connector_helper_funcs);
316 output->connector.dpms = DRM_MODE_DPMS_OFF;
319 err = drm_panel_attach(output->panel, &output->connector);
321 dev_err(output->dev, "failed to attach panel: %d\n",
325 drm_encoder_init(drm, &output->encoder, &tegra_rgb_encoder_funcs,
326 DRM_MODE_ENCODER_LVDS);
327 drm_encoder_helper_add(&output->encoder,
328 &tegra_rgb_encoder_helper_funcs);
330 drm_mode_connector_attach_encoder(&output->connector,
332 drm_connector_register(&output->connector);
335 * Other outputs can be attached to either display controller. The RGB
336 * outputs are an exception and work only with their parent display
339 output->encoder.possible_crtcs = drm_crtc_mask(&dc->base);
344 int tegra_dc_rgb_exit(struct tegra_dc *dc)
349 return tegra_output_exit(dc->rgb);