drivers/gpu/drm/tegra/sor.c

   1 /*
   2  * Copyright (C) 2013 NVIDIA Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/debugfs.h>
  11 #include <linux/io.h>
  12 #include <linux/platform_device.h>
  13 #include <linux/reset.h>
  14 #include <linux/tegra-powergate.h>
  15
  16 #include <drm/drm_dp_helper.h>
  17
  18 #include "dc.h"
  19 #include "drm.h"
  20 #include "sor.h"
  21
  22 struct tegra_sor {
  23         struct host1x_client client;
  24         struct tegra_output output;
  25         struct device *dev;
  26
  27         void __iomem *regs;
  28
  29         struct reset_control *rst;
  30         struct clk *clk_parent;
  31         struct clk *clk_safe;
  32         struct clk *clk_dp;
  33         struct clk *clk;
  34
  35         struct tegra_dpaux *dpaux;
  36
  37         struct mutex lock;
  38         bool enabled;
  39
  40         struct dentry *debugfs;
  41 };
  42
  43 struct tegra_sor_config {
  44         u32 bits_per_pixel;
  45
  46         u32 active_polarity;
  47         u32 active_count;
  48         u32 tu_size;
  49         u32 active_frac;
  50         u32 watermark;
  51 };
  52
  53 static inline struct tegra_sor *
  54 host1x_client_to_sor(struct host1x_client *client)
  55 {
  56         return container_of(client, struct tegra_sor, client);
  57 }
  58
  59 static inline struct tegra_sor *to_sor(struct tegra_output *output)
  60 {
  61         return container_of(output, struct tegra_sor, output);
  62 }
  63
  64 static inline unsigned long tegra_sor_readl(struct tegra_sor *sor,
  65                                             unsigned long offset)
  66 {
  67         return readl(sor->regs + (offset << 2));
  68 }
  69
  70 static inline void tegra_sor_writel(struct tegra_sor *sor, unsigned long value,
  71                                     unsigned long offset)
  72 {
  73         writel(value, sor->regs + (offset << 2));
  74 }
  75
  76 static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
  77                                    struct drm_dp_link *link)
  78 {
  79         unsigned long value;
  80         unsigned int i;
  81         u8 pattern;
  82         int err;
  83
  84         /* setup lane parameters */
  85         value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) |
  86                 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) |
  87                 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) |
  88                 SOR_LANE_DRIVE_CURRENT_LANE0(0x40);
  89         tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT_0);
  90
  91         value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) |
  92                 SOR_LANE_PREEMPHASIS_LANE2(0x0f) |
  93                 SOR_LANE_PREEMPHASIS_LANE1(0x0f) |
  94                 SOR_LANE_PREEMPHASIS_LANE0(0x0f);
  95         tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS_0);
  96
  97         value = SOR_LANE_POST_CURSOR_LANE3(0x00) |
  98                 SOR_LANE_POST_CURSOR_LANE2(0x00) |
  99                 SOR_LANE_POST_CURSOR_LANE1(0x00) |
 100                 SOR_LANE_POST_CURSOR_LANE0(0x00);
 101         tegra_sor_writel(sor, value, SOR_LANE_POST_CURSOR_0);
 102
 103         /* disable LVDS mode */
 104         tegra_sor_writel(sor, 0, SOR_LVDS);
 105
 106         value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
 107         value |= SOR_DP_PADCTL_TX_PU_ENABLE;
 108         value &= ~SOR_DP_PADCTL_TX_PU_MASK;
 109         value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */
 110         tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
 111
 112         value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
 113         value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
 114                  SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0;
 115         tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
 116
 117         usleep_range(10, 100);
 118
 119         value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
 120         value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
 121                    SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
 122         tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
 123
 124         err = tegra_dpaux_prepare(sor->dpaux, DP_SET_ANSI_8B10B);
 125         if (err < 0)
 126                 return err;
 127
 128         for (i = 0, value = 0; i < link->num_lanes; i++) {
 129                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 130                                      SOR_DP_TPG_SCRAMBLER_NONE |
 131                                      SOR_DP_TPG_PATTERN_TRAIN1;
 132                 value = (value << 8) | lane;
 133         }
 134
 135         tegra_sor_writel(sor, value, SOR_DP_TPG);
 136
 137         pattern = DP_TRAINING_PATTERN_1;
 138
 139         err = tegra_dpaux_train(sor->dpaux, link, pattern);
 140         if (err < 0)
 141                 return err;
 142
 143         value = tegra_sor_readl(sor, SOR_DP_SPARE_0);
 144         value |= SOR_DP_SPARE_SEQ_ENABLE;
 145         value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
 146         value |= SOR_DP_SPARE_MACRO_SOR_CLK;
 147         tegra_sor_writel(sor, value, SOR_DP_SPARE_0);
 148
 149         for (i = 0, value = 0; i < link->num_lanes; i++) {
 150                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 151                                      SOR_DP_TPG_SCRAMBLER_NONE |
 152                                      SOR_DP_TPG_PATTERN_TRAIN2;
 153                 value = (value << 8) | lane;
 154         }
 155
 156         tegra_sor_writel(sor, value, SOR_DP_TPG);
 157
 158         pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2;
 159
 160         err = tegra_dpaux_train(sor->dpaux, link, pattern);
 161         if (err < 0)
 162                 return err;
 163
 164         for (i = 0, value = 0; i < link->num_lanes; i++) {
 165                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 166                                      SOR_DP_TPG_SCRAMBLER_GALIOS |
 167                                      SOR_DP_TPG_PATTERN_NONE;
 168                 value = (value << 8) | lane;
 169         }
 170
 171         tegra_sor_writel(sor, value, SOR_DP_TPG);
 172
 173         pattern = DP_TRAINING_PATTERN_DISABLE;
 174
 175         err = tegra_dpaux_train(sor->dpaux, link, pattern);
 176         if (err < 0)
 177                 return err;
 178
 179         return 0;
 180 }
 181
 182 static void tegra_sor_super_update(struct tegra_sor *sor)
 183 {
 184         tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0);
 185         tegra_sor_writel(sor, 1, SOR_SUPER_STATE_0);
 186         tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0);
 187 }
 188
 189 static void tegra_sor_update(struct tegra_sor *sor)
 190 {
 191         tegra_sor_writel(sor, 0, SOR_STATE_0);
 192         tegra_sor_writel(sor, 1, SOR_STATE_0);
 193         tegra_sor_writel(sor, 0, SOR_STATE_0);
 194 }
 195
 196 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
 197 {
 198         unsigned long value;
 199
 200         value = tegra_sor_readl(sor, SOR_PWM_DIV);
 201         value &= ~SOR_PWM_DIV_MASK;
 202         value |= 0x400; /* period */
 203         tegra_sor_writel(sor, value, SOR_PWM_DIV);
 204
 205         value = tegra_sor_readl(sor, SOR_PWM_CTL);
 206         value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
 207         value |= 0x400; /* duty cycle */
 208         value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
 209         value |= SOR_PWM_CTL_TRIGGER;
 210         tegra_sor_writel(sor, value, SOR_PWM_CTL);
 211
 212         timeout = jiffies + msecs_to_jiffies(timeout);
 213
 214         while (time_before(jiffies, timeout)) {
 215                 value = tegra_sor_readl(sor, SOR_PWM_CTL);
 216                 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
 217                         return 0;
 218
 219                 usleep_range(25, 100);
 220         }
 221
 222         return -ETIMEDOUT;
 223 }
 224
 225 static int tegra_sor_attach(struct tegra_sor *sor)
 226 {
 227         unsigned long value, timeout;
 228
 229         /* wake up in normal mode */
 230         value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
 231         value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
 232         value |= SOR_SUPER_STATE_MODE_NORMAL;
 233         tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
 234         tegra_sor_super_update(sor);
 235
 236         /* attach */
 237         value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
 238         value |= SOR_SUPER_STATE_ATTACHED;
 239         tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
 240         tegra_sor_super_update(sor);
 241
 242         timeout = jiffies + msecs_to_jiffies(250);
 243
 244         while (time_before(jiffies, timeout)) {
 245                 value = tegra_sor_readl(sor, SOR_TEST);
 246                 if ((value & SOR_TEST_ATTACHED) != 0)
 247                         return 0;
 248
 249                 usleep_range(25, 100);
 250         }
 251
 252         return -ETIMEDOUT;
 253 }
 254
 255 static int tegra_sor_wakeup(struct tegra_sor *sor)
 256 {
 257         struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
 258         unsigned long value, timeout;
 259
 260         /* enable display controller outputs */
 261         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
 262         value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
 263                  PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
 264         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
 265
 266         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
 267         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
 268
 269         timeout = jiffies + msecs_to_jiffies(250);
 270
 271         /* wait for head to wake up */
 272         while (time_before(jiffies, timeout)) {
 273                 value = tegra_sor_readl(sor, SOR_TEST);
 274                 value &= SOR_TEST_HEAD_MODE_MASK;
 275
 276                 if (value == SOR_TEST_HEAD_MODE_AWAKE)
 277                         return 0;
 278
 279                 usleep_range(25, 100);
 280         }
 281
 282         return -ETIMEDOUT;
 283 }
 284
 285 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
 286 {
 287         unsigned long value;
 288
 289         value = tegra_sor_readl(sor, SOR_PWR);
 290         value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
 291         tegra_sor_writel(sor, value, SOR_PWR);
 292
 293         timeout = jiffies + msecs_to_jiffies(timeout);
 294
 295         while (time_before(jiffies, timeout)) {
 296                 value = tegra_sor_readl(sor, SOR_PWR);
 297                 if ((value & SOR_PWR_TRIGGER) == 0)
 298                         return 0;
 299
 300                 usleep_range(25, 100);
 301         }
 302
 303         return -ETIMEDOUT;
 304 }
 305
 306 struct tegra_sor_params {
 307         /* number of link clocks per line */
 308         unsigned int num_clocks;
 309         /* ratio between input and output */
 310         u64 ratio;
 311         /* precision factor */
 312         u64 precision;
 313
 314         unsigned int active_polarity;
 315         unsigned int active_count;
 316         unsigned int active_frac;
 317         unsigned int tu_size;
 318         unsigned int error;
 319 };
 320
 321 static int tegra_sor_compute_params(struct tegra_sor *sor,
 322                                     struct tegra_sor_params *params,
 323                                     unsigned int tu_size)
 324 {
 325         u64 active_sym, active_count, frac, approx;
 326         u32 active_polarity, active_frac = 0;
 327         const u64 f = params->precision;
 328         s64 error;
 329
 330         active_sym = params->ratio * tu_size;
 331         active_count = div_u64(active_sym, f) * f;
 332         frac = active_sym - active_count;
 333
 334         /* fraction < 0.5 */
 335         if (frac >= (f / 2)) {
 336                 active_polarity = 1;
 337                 frac = f - frac;
 338         } else {
 339                 active_polarity = 0;
 340         }
 341
 342         if (frac != 0) {
 343                 frac = div_u64(f * f,  frac); /* 1/fraction */
 344                 if (frac <= (15 * f)) {
 345                         active_frac = div_u64(frac, f);
 346
 347                         /* round up */
 348                         if (active_polarity)
 349                                 active_frac++;
 350                 } else {
 351                         active_frac = active_polarity ? 1 : 15;
 352                 }
 353         }
 354
 355         if (active_frac == 1)
 356                 active_polarity = 0;
 357
 358         if (active_polarity == 1) {
 359                 if (active_frac) {
 360                         approx = active_count + (active_frac * (f - 1)) * f;
 361                         approx = div_u64(approx, active_frac * f);
 362                 } else {
 363                         approx = active_count + f;
 364                 }
 365         } else {
 366                 if (active_frac)
 367                         approx = active_count + div_u64(f, active_frac);
 368                 else
 369                         approx = active_count;
 370         }
 371
 372         error = div_s64(active_sym - approx, tu_size);
 373         error *= params->num_clocks;
 374
 375         if (error <= 0 && abs64(error) < params->error) {
 376                 params->active_count = div_u64(active_count, f);
 377                 params->active_polarity = active_polarity;
 378                 params->active_frac = active_frac;
 379                 params->error = abs64(error);
 380                 params->tu_size = tu_size;
 381
 382                 if (error == 0)
 383                         return true;
 384         }
 385
 386         return false;
 387 }
 388
 389 static int tegra_sor_calc_config(struct tegra_sor *sor,
 390                                  struct drm_display_mode *mode,
 391                                  struct tegra_sor_config *config,
 392                                  struct drm_dp_link *link)
 393 {
 394         const u64 f = 100000, link_rate = link->rate * 1000;
 395         const u64 pclk = mode->clock * 1000;
 396         struct tegra_sor_params params;
 397         u64 input, output, watermark;
 398         u32 num_syms_per_line;
 399         unsigned int i;
 400
 401         if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel)
 402                 return -EINVAL;
 403
 404         output = link_rate * 8 * link->num_lanes;
 405         input = pclk * config->bits_per_pixel;
 406
 407         if (input >= output)
 408                 return -ERANGE;
 409
 410         memset(&params, 0, sizeof(params));
 411         params.ratio = div64_u64(input * f, output);
 412         params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
 413         params.precision = f;
 414         params.error = 64 * f;
 415         params.tu_size = 64;
 416
 417         for (i = params.tu_size; i >= 32; i--)
 418                 if (tegra_sor_compute_params(sor, &params, i))
 419                         break;
 420
 421         if (params.active_frac == 0) {
 422                 config->active_polarity = 0;
 423                 config->active_count = params.active_count;
 424
 425                 if (!params.active_polarity)
 426                         config->active_count--;
 427
 428                 config->tu_size = params.tu_size;
 429                 config->active_frac = 1;
 430         } else {
 431                 config->active_polarity = params.active_polarity;
 432                 config->active_count = params.active_count;
 433                 config->active_frac = params.active_frac;
 434                 config->tu_size = params.tu_size;
 435         }
 436
 437         dev_dbg(sor->dev,
 438                 "polarity: %d active count: %d tu size: %d active frac: %d\n",
 439                 config->active_polarity, config->active_count,
 440                 config->tu_size, config->active_frac);
 441
 442         watermark = params.ratio * config->tu_size * (f - params.ratio);
 443         watermark = div_u64(watermark, f);
 444
 445         watermark = div_u64(watermark + params.error, f);
 446         config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
 447         num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
 448                             (link->num_lanes * 8);
 449
 450         if (config->watermark > 30) {
 451                 config->watermark = 30;
 452                 dev_err(sor->dev,
 453                         "unable to compute TU size, forcing watermark to %u\n",
 454                         config->watermark);
 455         } else if (config->watermark > num_syms_per_line) {
 456                 config->watermark = num_syms_per_line;
 457                 dev_err(sor->dev, "watermark too high, forcing to %u\n",
 458                         config->watermark);
 459         }
 460
 461         return 0;
 462 }
 463
 464 static int tegra_output_sor_enable(struct tegra_output *output)
 465 {
 466         struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
 467         struct drm_display_mode *mode = &dc->base.mode;
 468         unsigned int vbe, vse, hbe, hse, vbs, hbs, i;
 469         struct tegra_sor *sor = to_sor(output);
 470         struct tegra_sor_config config;
 471         struct drm_dp_link link;
 472         struct drm_dp_aux *aux;
 473         unsigned long value;
 474         int err = 0;
 475
 476         mutex_lock(&sor->lock);
 477
 478         if (sor->enabled)
 479                 goto unlock;
 480
 481         err = clk_prepare_enable(sor->clk);
 482         if (err < 0)
 483                 goto unlock;
 484
 485         reset_control_deassert(sor->rst);
 486
 487         /* FIXME: properly convert to struct drm_dp_aux */
 488         aux = (struct drm_dp_aux *)sor->dpaux;
 489
 490         if (sor->dpaux) {
 491                 err = tegra_dpaux_enable(sor->dpaux);
 492                 if (err < 0)
 493                         dev_err(sor->dev, "failed to enable DP: %d\n", err);
 494
 495                 err = drm_dp_link_probe(aux, &link);
 496                 if (err < 0) {
 497                         dev_err(sor->dev, "failed to probe eDP link: %d\n",
 498                                 err);
 499                         return err;
 500                 }
 501         }
 502
 503         err = clk_set_parent(sor->clk, sor->clk_safe);
 504         if (err < 0)
 505                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
 506
 507         memset(&config, 0, sizeof(config));
 508         config.bits_per_pixel = 24; /* XXX: don't hardcode? */
 509
 510         err = tegra_sor_calc_config(sor, mode, &config, &link);
 511         if (err < 0)
 512                 dev_err(sor->dev, "failed to compute link configuration: %d\n",
 513                         err);
 514
 515         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 516         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
 517         value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
 518         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 519
 520         value = tegra_sor_readl(sor, SOR_PLL_2);
 521         value &= ~SOR_PLL_2_BANDGAP_POWERDOWN;
 522         tegra_sor_writel(sor, value, SOR_PLL_2);
 523         usleep_range(20, 100);
 524
 525         value = tegra_sor_readl(sor, SOR_PLL_3);
 526         value |= SOR_PLL_3_PLL_VDD_MODE_V3_3;
 527         tegra_sor_writel(sor, value, SOR_PLL_3);
 528
 529         value = SOR_PLL_0_ICHPMP(0xf) | SOR_PLL_0_VCOCAP_RST |
 530                 SOR_PLL_0_PLLREG_LEVEL_V45 | SOR_PLL_0_RESISTOR_EXT;
 531         tegra_sor_writel(sor, value, SOR_PLL_0);
 532
 533         value = tegra_sor_readl(sor, SOR_PLL_2);
 534         value |= SOR_PLL_2_SEQ_PLLCAPPD;
 535         value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE;
 536         value |= SOR_PLL_2_LVDS_ENABLE;
 537         tegra_sor_writel(sor, value, SOR_PLL_2);
 538
 539         value = SOR_PLL_1_TERM_COMPOUT | SOR_PLL_1_TMDS_TERM;
 540         tegra_sor_writel(sor, value, SOR_PLL_1);
 541
 542         while (true) {
 543                 value = tegra_sor_readl(sor, SOR_PLL_2);
 544                 if ((value & SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE) == 0)
 545                         break;
 546
 547                 usleep_range(250, 1000);
 548         }
 549
 550         value = tegra_sor_readl(sor, SOR_PLL_2);
 551         value &= ~SOR_PLL_2_POWERDOWN_OVERRIDE;
 552         value &= ~SOR_PLL_2_PORT_POWERDOWN;
 553         tegra_sor_writel(sor, value, SOR_PLL_2);
 554
 555         /*
 556          * power up
 557          */
 558
 559         /* set safe link bandwidth (1.62 Gbps) */
 560         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 561         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
 562         value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62;
 563         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 564
 565         /* step 1 */
 566         value = tegra_sor_readl(sor, SOR_PLL_2);
 567         value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL_2_PORT_POWERDOWN |
 568                  SOR_PLL_2_BANDGAP_POWERDOWN;
 569         tegra_sor_writel(sor, value, SOR_PLL_2);
 570
 571         value = tegra_sor_readl(sor, SOR_PLL_0);
 572         value |= SOR_PLL_0_VCOPD | SOR_PLL_0_POWER_OFF;
 573         tegra_sor_writel(sor, value, SOR_PLL_0);
 574
 575         value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
 576         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
 577         tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
 578
 579         /* step 2 */
 580         err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS);
 581         if (err < 0) {
 582                 dev_err(sor->dev, "failed to power on I/O rail: %d\n", err);
 583                 goto unlock;
 584         }
 585
 586         usleep_range(5, 100);
 587
 588         /* step 3 */
 589         value = tegra_sor_readl(sor, SOR_PLL_2);
 590         value &= ~SOR_PLL_2_BANDGAP_POWERDOWN;
 591         tegra_sor_writel(sor, value, SOR_PLL_2);
 592
 593         usleep_range(20, 100);
 594
 595         /* step 4 */
 596         value = tegra_sor_readl(sor, SOR_PLL_0);
 597         value &= ~SOR_PLL_0_POWER_OFF;
 598         value &= ~SOR_PLL_0_VCOPD;
 599         tegra_sor_writel(sor, value, SOR_PLL_0);
 600
 601         value = tegra_sor_readl(sor, SOR_PLL_2);
 602         value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE;
 603         tegra_sor_writel(sor, value, SOR_PLL_2);
 604
 605         usleep_range(200, 1000);
 606
 607         /* step 5 */
 608         value = tegra_sor_readl(sor, SOR_PLL_2);
 609         value &= ~SOR_PLL_2_PORT_POWERDOWN;
 610         tegra_sor_writel(sor, value, SOR_PLL_2);
 611
 612         /* switch to DP clock */
 613         err = clk_set_parent(sor->clk, sor->clk_dp);
 614         if (err < 0)
 615                 dev_err(sor->dev, "failed to set DP parent clock: %d\n", err);
 616
 617         /* power dplanes (XXX parameterize based on link?) */
 618         value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
 619         value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
 620                  SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
 621         tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
 622
 623         value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0);
 624         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
 625         value |= SOR_DP_LINKCTL_LANE_COUNT(4);
 626         tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);
 627
 628         /* start lane sequencer */
 629         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
 630                 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
 631         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
 632
 633         while (true) {
 634                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
 635                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
 636                         break;
 637
 638                 usleep_range(250, 1000);
 639         }
 640
 641         /* set link bandwidth (2.7 GHz, XXX: parameterize based on link?) */
 642         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 643         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
 644         value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
 645         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 646
 647         /* set linkctl */
 648         value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0);
 649         value |= SOR_DP_LINKCTL_ENABLE;
 650
 651         value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
 652         value |= SOR_DP_LINKCTL_TU_SIZE(config.tu_size);
 653
 654         value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
 655         tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);
 656
 657         for (i = 0, value = 0; i < 4; i++) {
 658                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 659                                      SOR_DP_TPG_SCRAMBLER_GALIOS |
 660                                      SOR_DP_TPG_PATTERN_NONE;
 661                 value = (value << 8) | lane;
 662         }
 663
 664         tegra_sor_writel(sor, value, SOR_DP_TPG);
 665
 666         value = tegra_sor_readl(sor, SOR_DP_CONFIG_0);
 667         value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
 668         value |= SOR_DP_CONFIG_WATERMARK(config.watermark);
 669
 670         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
 671         value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config.active_count);
 672
 673         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
 674         value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config.active_frac);
 675
 676         if (config.active_polarity)
 677                 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
 678         else
 679                 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
 680
 681         value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
 682         value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; /* XXX: don't hardcode? */
 683         tegra_sor_writel(sor, value, SOR_DP_CONFIG_0);
 684
 685         value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
 686         value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
 687         value |= 137; /* XXX: don't hardcode? */
 688         tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
 689
 690         value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
 691         value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
 692         value |= 2368; /* XXX: don't hardcode? */
 693         tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
 694
 695         /* enable pad calibration logic */
 696         value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
 697         value |= SOR_DP_PADCTL_PAD_CAL_PD;
 698         tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
 699
 700         if (sor->dpaux) {
 701                 u8 rate, lanes;
 702
 703                 err = drm_dp_link_probe(aux, &link);
 704                 if (err < 0) {
 705                         dev_err(sor->dev, "failed to probe eDP link: %d\n",
 706                                 err);
 707                         goto unlock;
 708                 }
 709
 710                 err = drm_dp_link_power_up(aux, &link);
 711                 if (err < 0) {
 712                         dev_err(sor->dev, "failed to power up eDP link: %d\n",
 713                                 err);
 714                         goto unlock;
 715                 }
 716
 717                 err = drm_dp_link_configure(aux, &link);
 718                 if (err < 0) {
 719                         dev_err(sor->dev, "failed to configure eDP link: %d\n",
 720                                 err);
 721                         goto unlock;
 722                 }
 723
 724                 rate = drm_dp_link_rate_to_bw_code(link.rate);
 725                 lanes = link.num_lanes;
 726
 727                 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 728                 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
 729                 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
 730                 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 731
 732                 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0);
 733                 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
 734                 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
 735
 736                 if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
 737                         value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
 738
 739                 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);
 740
 741                 /* disable training pattern generator */
 742
 743                 for (i = 0; i < link.num_lanes; i++) {
 744                         unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 745                                              SOR_DP_TPG_SCRAMBLER_GALIOS |
 746                                              SOR_DP_TPG_PATTERN_NONE;
 747                         value = (value << 8) | lane;
 748                 }
 749
 750                 tegra_sor_writel(sor, value, SOR_DP_TPG);
 751
 752                 err = tegra_sor_dp_train_fast(sor, &link);
 753                 if (err < 0) {
 754                         dev_err(sor->dev, "DP fast link training failed: %d\n",
 755                                 err);
 756                         goto unlock;
 757                 }
 758
 759                 dev_dbg(sor->dev, "fast link training succeeded\n");
 760         }
 761
 762         err = tegra_sor_power_up(sor, 250);
 763         if (err < 0) {
 764                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
 765                 goto unlock;
 766         }
 767
 768         /* start display controller in continuous mode */
 769         value = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
 770         value |= WRITE_MUX;
 771         tegra_dc_writel(dc, value, DC_CMD_STATE_ACCESS);
 772
 773         tegra_dc_writel(dc, VSYNC_H_POSITION(1), DC_DISP_DISP_TIMING_OPTIONS);
 774         tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
 775
 776         value = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
 777         value &= ~WRITE_MUX;
 778         tegra_dc_writel(dc, value, DC_CMD_STATE_ACCESS);
 779
 780         /*
 781          * configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete
 782          * raster, associate with display controller)
 783          */
 784         value = SOR_STATE_ASY_VSYNCPOL |
 785                 SOR_STATE_ASY_HSYNCPOL |
 786                 SOR_STATE_ASY_PROTOCOL_DP_A |
 787                 SOR_STATE_ASY_CRC_MODE_COMPLETE |
 788                 SOR_STATE_ASY_OWNER(dc->pipe + 1);
 789
 790         switch (config.bits_per_pixel) {
 791         case 24:
 792                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
 793                 break;
 794
 795         case 18:
 796                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
 797                 break;
 798
 799         default:
 800                 BUG();
 801                 break;
 802         }
 803
 804         tegra_sor_writel(sor, value, SOR_STATE_1);
 805
 806         /*
 807          * TODO: The video timing programming below doesn't seem to match the
 808          * register definitions.
 809          */
 810
 811         value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
 812         tegra_sor_writel(sor, value, SOR_HEAD_STATE_1(0));
 813
 814         vse = mode->vsync_end - mode->vsync_start - 1;
 815         hse = mode->hsync_end - mode->hsync_start - 1;
 816
 817         value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
 818         tegra_sor_writel(sor, value, SOR_HEAD_STATE_2(0));
 819
 820         vbe = vse + (mode->vsync_start - mode->vdisplay);
 821         hbe = hse + (mode->hsync_start - mode->hdisplay);
 822
 823         value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
 824         tegra_sor_writel(sor, value, SOR_HEAD_STATE_3(0));
 825
 826         vbs = vbe + mode->vdisplay;
 827         hbs = hbe + mode->hdisplay;
 828
 829         value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
 830         tegra_sor_writel(sor, value, SOR_HEAD_STATE_4(0));
 831
 832         /* XXX interlaced mode */
 833         tegra_sor_writel(sor, 0x00000001, SOR_HEAD_STATE_5(0));
 834
 835         /* CSTM (LVDS, link A/B, upper) */
 836         value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
 837                 SOR_CSTM_UPPER;
 838         tegra_sor_writel(sor, value, SOR_CSTM);
 839
 840         /* PWM setup */
 841         err = tegra_sor_setup_pwm(sor, 250);
 842         if (err < 0) {
 843                 dev_err(sor->dev, "failed to setup PWM: %d\n", err);
 844                 goto unlock;
 845         }
 846
 847         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
 848         value |= SOR_ENABLE;
 849         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
 850
 851         tegra_sor_update(sor);
 852
 853         err = tegra_sor_attach(sor);
 854         if (err < 0) {
 855                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
 856                 goto unlock;
 857         }
 858
 859         err = tegra_sor_wakeup(sor);
 860         if (err < 0) {
 861                 dev_err(sor->dev, "failed to enable DC: %d\n", err);
 862                 goto unlock;
 863         }
 864
 865         sor->enabled = true;
 866
 867 unlock:
 868         mutex_unlock(&sor->lock);
 869         return err;
 870 }
 871
 872 static int tegra_sor_detach(struct tegra_sor *sor)
 873 {
 874         unsigned long value, timeout;
 875
 876         /* switch to safe mode */
 877         value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
 878         value &= ~SOR_SUPER_STATE_MODE_NORMAL;
 879         tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
 880         tegra_sor_super_update(sor);
 881
 882         timeout = jiffies + msecs_to_jiffies(250);
 883
 884         while (time_before(jiffies, timeout)) {
 885                 value = tegra_sor_readl(sor, SOR_PWR);
 886                 if (value & SOR_PWR_MODE_SAFE)
 887                         break;
 888         }
 889
 890         if ((value & SOR_PWR_MODE_SAFE) == 0)
 891                 return -ETIMEDOUT;
 892
 893         /* go to sleep */
 894         value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
 895         value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
 896         tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
 897         tegra_sor_super_update(sor);
 898
 899         /* detach */
 900         value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
 901         value &= ~SOR_SUPER_STATE_ATTACHED;
 902         tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
 903         tegra_sor_super_update(sor);
 904
 905         timeout = jiffies + msecs_to_jiffies(250);
 906
 907         while (time_before(jiffies, timeout)) {
 908                 value = tegra_sor_readl(sor, SOR_TEST);
 909                 if ((value & SOR_TEST_ATTACHED) == 0)
 910                         break;
 911
 912                 usleep_range(25, 100);
 913         }
 914
 915         if ((value & SOR_TEST_ATTACHED) != 0)
 916                 return -ETIMEDOUT;
 917
 918         return 0;
 919 }
 920
 921 static int tegra_sor_power_down(struct tegra_sor *sor)
 922 {
 923         unsigned long value, timeout;
 924         int err;
 925
 926         value = tegra_sor_readl(sor, SOR_PWR);
 927         value &= ~SOR_PWR_NORMAL_STATE_PU;
 928         value |= SOR_PWR_TRIGGER;
 929         tegra_sor_writel(sor, value, SOR_PWR);
 930
 931         timeout = jiffies + msecs_to_jiffies(250);
 932
 933         while (time_before(jiffies, timeout)) {
 934                 value = tegra_sor_readl(sor, SOR_PWR);
 935                 if ((value & SOR_PWR_TRIGGER) == 0)
 936                         return 0;
 937
 938                 usleep_range(25, 100);
 939         }
 940
 941         if ((value & SOR_PWR_TRIGGER) != 0)
 942                 return -ETIMEDOUT;
 943
 944         err = clk_set_parent(sor->clk, sor->clk_safe);
 945         if (err < 0)
 946                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
 947
 948         value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
 949         value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
 950                    SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
 951         tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
 952
 953         /* stop lane sequencer */
 954         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
 955                 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
 956         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
 957
 958         timeout = jiffies + msecs_to_jiffies(250);
 959
 960         while (time_before(jiffies, timeout)) {
 961                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
 962                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
 963                         break;
 964
 965                 usleep_range(25, 100);
 966         }
 967
 968         if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
 969                 return -ETIMEDOUT;
 970
 971         value = tegra_sor_readl(sor, SOR_PLL_2);
 972         value |= SOR_PLL_2_PORT_POWERDOWN;
 973         tegra_sor_writel(sor, value, SOR_PLL_2);
 974
 975         usleep_range(20, 100);
 976
 977         value = tegra_sor_readl(sor, SOR_PLL_0);
 978         value |= SOR_PLL_0_POWER_OFF;
 979         value |= SOR_PLL_0_VCOPD;
 980         tegra_sor_writel(sor, value, SOR_PLL_0);
 981
 982         value = tegra_sor_readl(sor, SOR_PLL_2);
 983         value |= SOR_PLL_2_SEQ_PLLCAPPD;
 984         value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE;
 985         tegra_sor_writel(sor, value, SOR_PLL_2);
 986
 987         usleep_range(20, 100);
 988
 989         return 0;
 990 }
 991
 992 static int tegra_output_sor_disable(struct tegra_output *output)
 993 {
 994         struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
 995         struct tegra_sor *sor = to_sor(output);
 996         unsigned long value;
 997         int err = 0;
 998
 999         mutex_lock(&sor->lock);
1000
1001         if (!sor->enabled)
1002                 goto unlock;
1003
1004         err = tegra_sor_detach(sor);
1005         if (err < 0) {
1006                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
1007                 goto unlock;
1008         }
1009
1010         tegra_sor_writel(sor, 0, SOR_STATE_1);
1011         tegra_sor_update(sor);
1012
1013         /*
1014          * The following accesses registers of the display controller, so make
1015          * sure it's only executed when the output is attached to one.
1016          */
1017         if (dc) {
1018                 /*
1019                  * XXX: We can't do this here because it causes the SOR to go
1020                  * into an erroneous state and the output will look scrambled
1021                  * the next time it is enabled. Presumably this is because we
1022                  * should be doing this only on the next VBLANK. A possible
1023                  * solution would be to queue a "power-off" event to trigger
1024                  * this code to be run during the next VBLANK.
1025                  */
1026                 /*
1027                 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
1028                 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
1029                            PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
1030                 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
1031                 */
1032
1033                 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
1034                 value &= ~DISP_CTRL_MODE_MASK;
1035                 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
1036
1037                 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1038                 value &= ~SOR_ENABLE;
1039                 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1040
1041                 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
1042                 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
1043         }
1044
1045         err = tegra_sor_power_down(sor);
1046         if (err < 0) {
1047                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1048                 goto unlock;
1049         }
1050
1051         if (sor->dpaux) {
1052                 err = tegra_dpaux_disable(sor->dpaux);
1053                 if (err < 0) {
1054                         dev_err(sor->dev, "failed to disable DP: %d\n", err);
1055                         goto unlock;
1056                 }
1057         }
1058
1059         err = tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS);
1060         if (err < 0) {
1061                 dev_err(sor->dev, "failed to power off I/O rail: %d\n", err);
1062                 goto unlock;
1063         }
1064
1065         reset_control_assert(sor->rst);
1066         clk_disable_unprepare(sor->clk);
1067
1068         sor->enabled = false;
1069
1070 unlock:
1071         mutex_unlock(&sor->lock);
1072         return err;
1073 }
1074
1075 static int tegra_output_sor_setup_clock(struct tegra_output *output,
1076                                         struct clk *clk, unsigned long pclk,
1077                                         unsigned int *div)
1078 {
1079         struct tegra_sor *sor = to_sor(output);
1080         int err;
1081
1082         err = clk_set_parent(clk, sor->clk_parent);
1083         if (err < 0) {
1084                 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
1085                 return err;
1086         }
1087
1088         err = clk_set_rate(sor->clk_parent, pclk);
1089         if (err < 0) {
1090                 dev_err(sor->dev, "failed to set clock rate to %lu Hz\n", pclk);
1091                 return err;
1092         }
1093
1094         *div = 0;
1095
1096         return 0;
1097 }
1098
1099 static int tegra_output_sor_check_mode(struct tegra_output *output,
1100                                        struct drm_display_mode *mode,
1101                                        enum drm_mode_status *status)
1102 {
1103         /*
1104          * FIXME: For now, always assume that the mode is okay.
1105          */
1106
1107         *status = MODE_OK;
1108
1109         return 0;
1110 }
1111
1112 static enum drm_connector_status
1113 tegra_output_sor_detect(struct tegra_output *output)
1114 {
1115         struct tegra_sor *sor = to_sor(output);
1116
1117         if (sor->dpaux)
1118                 return tegra_dpaux_detect(sor->dpaux);
1119
1120         return connector_status_unknown;
1121 }
1122
1123 static const struct tegra_output_ops sor_ops = {
1124         .enable = tegra_output_sor_enable,
1125         .disable = tegra_output_sor_disable,
1126         .setup_clock = tegra_output_sor_setup_clock,
1127         .check_mode = tegra_output_sor_check_mode,
1128         .detect = tegra_output_sor_detect,
1129 };
1130
1131 static int tegra_sor_crc_open(struct inode *inode, struct file *file)
1132 {
1133         file->private_data = inode->i_private;
1134
1135         return 0;
1136 }
1137
1138 static int tegra_sor_crc_release(struct inode *inode, struct file *file)
1139 {
1140         return 0;
1141 }
1142
1143 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
1144 {
1145         u32 value;
1146
1147         timeout = jiffies + msecs_to_jiffies(timeout);
1148
1149         while (time_before(jiffies, timeout)) {
1150                 value = tegra_sor_readl(sor, SOR_CRC_A);
1151                 if (value & SOR_CRC_A_VALID)
1152                         return 0;
1153
1154                 usleep_range(100, 200);
1155         }
1156
1157         return -ETIMEDOUT;
1158 }
1159
1160 static ssize_t tegra_sor_crc_read(struct file *file, char __user *buffer,
1161                                   size_t size, loff_t *ppos)
1162 {
1163         struct tegra_sor *sor = file->private_data;
1164         ssize_t num, err;
1165         char buf[10];
1166         u32 value;
1167
1168         mutex_lock(&sor->lock);
1169
1170         if (!sor->enabled) {
1171                 err = -EAGAIN;
1172                 goto unlock;
1173         }
1174
1175         value = tegra_sor_readl(sor, SOR_STATE_1);
1176         value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
1177         tegra_sor_writel(sor, value, SOR_STATE_1);
1178
1179         value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
1180         value |= SOR_CRC_CNTRL_ENABLE;
1181         tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
1182
1183         value = tegra_sor_readl(sor, SOR_TEST);
1184         value &= ~SOR_TEST_CRC_POST_SERIALIZE;
1185         tegra_sor_writel(sor, value, SOR_TEST);
1186
1187         err = tegra_sor_crc_wait(sor, 100);
1188         if (err < 0)
1189                 goto unlock;
1190
1191         tegra_sor_writel(sor, SOR_CRC_A_RESET, SOR_CRC_A);
1192         value = tegra_sor_readl(sor, SOR_CRC_B);
1193
1194         num = scnprintf(buf, sizeof(buf), "%08x\n", value);
1195
1196         err = simple_read_from_buffer(buffer, size, ppos, buf, num);
1197
1198 unlock:
1199         mutex_unlock(&sor->lock);
1200         return err;
1201 }
1202
1203 static const struct file_operations tegra_sor_crc_fops = {
1204         .owner = THIS_MODULE,
1205         .open = tegra_sor_crc_open,
1206         .read = tegra_sor_crc_read,
1207         .release = tegra_sor_crc_release,
1208 };
1209
1210 static int tegra_sor_debugfs_init(struct tegra_sor *sor,
1211                                   struct drm_minor *minor)
1212 {
1213         struct dentry *entry;
1214         int err = 0;
1215
1216         sor->debugfs = debugfs_create_dir("sor", minor->debugfs_root);
1217         if (!sor->debugfs)
1218                 return -ENOMEM;
1219
1220         entry = debugfs_create_file("crc", 0644, sor->debugfs, sor,
1221                                     &tegra_sor_crc_fops);
1222         if (!entry) {
1223                 dev_err(sor->dev,
1224                         "cannot create /sys/kernel/debug/dri/%s/sor/crc\n",
1225                         minor->debugfs_root->d_name.name);
1226                 err = -ENOMEM;
1227                 goto remove;
1228         }
1229
1230         return err;
1231
1232 remove:
1233         debugfs_remove(sor->debugfs);
1234         sor->debugfs = NULL;
1235         return err;
1236 }
1237
1238 static int tegra_sor_debugfs_exit(struct tegra_sor *sor)
1239 {
1240         debugfs_remove_recursive(sor->debugfs);
1241         sor->debugfs = NULL;
1242
1243         return 0;
1244 }
1245
1246 static int tegra_sor_init(struct host1x_client *client)
1247 {
1248         struct drm_device *drm = dev_get_drvdata(client->parent);
1249         struct tegra_sor *sor = host1x_client_to_sor(client);
1250         int err;
1251
1252         if (!sor->dpaux)
1253                 return -ENODEV;
1254
1255         sor->output.type = TEGRA_OUTPUT_EDP;
1256
1257         sor->output.dev = sor->dev;
1258         sor->output.ops = &sor_ops;
1259
1260         err = tegra_output_init(drm, &sor->output);
1261         if (err < 0) {
1262                 dev_err(sor->dev, "output setup failed: %d\n", err);
1263                 return err;
1264         }
1265
1266         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1267                 err = tegra_sor_debugfs_init(sor, drm->primary);
1268                 if (err < 0)
1269                         dev_err(sor->dev, "debugfs setup failed: %d\n", err);
1270         }
1271
1272         if (sor->dpaux) {
1273                 err = tegra_dpaux_attach(sor->dpaux, &sor->output);
1274                 if (err < 0) {
1275                         dev_err(sor->dev, "failed to attach DP: %d\n", err);
1276                         return err;
1277                 }
1278         }
1279
1280         return 0;
1281 }
1282
1283 static int tegra_sor_exit(struct host1x_client *client)
1284 {
1285         struct tegra_sor *sor = host1x_client_to_sor(client);
1286         int err;
1287
1288         err = tegra_output_disable(&sor->output);
1289         if (err < 0) {
1290                 dev_err(sor->dev, "output failed to disable: %d\n", err);
1291                 return err;
1292         }
1293
1294         if (sor->dpaux) {
1295                 err = tegra_dpaux_detach(sor->dpaux);
1296                 if (err < 0) {
1297                         dev_err(sor->dev, "failed to detach DP: %d\n", err);
1298                         return err;
1299                 }
1300         }
1301
1302         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1303                 err = tegra_sor_debugfs_exit(sor);
1304                 if (err < 0)
1305                         dev_err(sor->dev, "debugfs cleanup failed: %d\n", err);
1306         }
1307
1308         err = tegra_output_exit(&sor->output);
1309         if (err < 0) {
1310                 dev_err(sor->dev, "output cleanup failed: %d\n", err);
1311                 return err;
1312         }
1313
1314         return 0;
1315 }
1316
1317 static const struct host1x_client_ops sor_client_ops = {
1318         .init = tegra_sor_init,
1319         .exit = tegra_sor_exit,
1320 };
1321
1322 static int tegra_sor_probe(struct platform_device *pdev)
1323 {
1324         struct device_node *np;
1325         struct tegra_sor *sor;
1326         struct resource *regs;
1327         int err;
1328
1329         sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
1330         if (!sor)
1331                 return -ENOMEM;
1332
1333         sor->output.dev = sor->dev = &pdev->dev;
1334
1335         np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
1336         if (np) {
1337                 sor->dpaux = tegra_dpaux_find_by_of_node(np);
1338                 of_node_put(np);
1339
1340                 if (!sor->dpaux)
1341                         return -EPROBE_DEFER;
1342         }
1343
1344         err = tegra_output_probe(&sor->output);
1345         if (err < 0)
1346                 return err;
1347
1348         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1349         sor->regs = devm_ioremap_resource(&pdev->dev, regs);
1350         if (IS_ERR(sor->regs))
1351                 return PTR_ERR(sor->regs);
1352
1353         sor->rst = devm_reset_control_get(&pdev->dev, "sor");
1354         if (IS_ERR(sor->rst))
1355                 return PTR_ERR(sor->rst);
1356
1357         sor->clk = devm_clk_get(&pdev->dev, NULL);
1358         if (IS_ERR(sor->clk))
1359                 return PTR_ERR(sor->clk);
1360
1361         sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
1362         if (IS_ERR(sor->clk_parent))
1363                 return PTR_ERR(sor->clk_parent);
1364
1365         err = clk_prepare_enable(sor->clk_parent);
1366         if (err < 0)
1367                 return err;
1368
1369         sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
1370         if (IS_ERR(sor->clk_safe))
1371                 return PTR_ERR(sor->clk_safe);
1372
1373         err = clk_prepare_enable(sor->clk_safe);
1374         if (err < 0)
1375                 return err;
1376
1377         sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
1378         if (IS_ERR(sor->clk_dp))
1379                 return PTR_ERR(sor->clk_dp);
1380
1381         err = clk_prepare_enable(sor->clk_dp);
1382         if (err < 0)
1383                 return err;
1384
1385         INIT_LIST_HEAD(&sor->client.list);
1386         sor->client.ops = &sor_client_ops;
1387         sor->client.dev = &pdev->dev;
1388
1389         mutex_init(&sor->lock);
1390
1391         err = host1x_client_register(&sor->client);
1392         if (err < 0) {
1393                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1394                         err);
1395                 return err;
1396         }
1397
1398         platform_set_drvdata(pdev, sor);
1399
1400         return 0;
1401 }
1402
1403 static int tegra_sor_remove(struct platform_device *pdev)
1404 {
1405         struct tegra_sor *sor = platform_get_drvdata(pdev);
1406         int err;
1407
1408         err = host1x_client_unregister(&sor->client);
1409         if (err < 0) {
1410                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1411                         err);
1412                 return err;
1413         }
1414
1415         clk_disable_unprepare(sor->clk_parent);
1416         clk_disable_unprepare(sor->clk_safe);
1417         clk_disable_unprepare(sor->clk_dp);
1418         clk_disable_unprepare(sor->clk);
1419
1420         return 0;
1421 }
1422
1423 static const struct of_device_id tegra_sor_of_match[] = {
1424         { .compatible = "nvidia,tegra124-sor", },
1425         { },
1426 };
1427
1428 struct platform_driver tegra_sor_driver = {
1429         .driver = {
1430                 .name = "tegra-sor",
1431                 .of_match_table = tegra_sor_of_match,
1432         },
1433         .probe = tegra_sor_probe,
1434         .remove = tegra_sor_remove,
1435 };