drivers/gpu/drm/tegra/sor.c

   1 /*
   2  * Copyright (C) 2013 NVIDIA Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/debugfs.h>
  11 #include <linux/gpio.h>
  12 #include <linux/io.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/reset.h>
  15
  16 #include <soc/tegra/pmc.h>
  17
  18 #include <drm/drm_atomic_helper.h>
  19 #include <drm/drm_dp_helper.h>
  20 #include <drm/drm_panel.h>
  21
  22 #include "dc.h"
  23 #include "drm.h"
  24 #include "sor.h"
  25
  26 struct tegra_sor {
  27         struct host1x_client client;
  28         struct tegra_output output;
  29         struct device *dev;
  30
  31         void __iomem *regs;
  32
  33         struct reset_control *rst;
  34         struct clk *clk_parent;
  35         struct clk *clk_safe;
  36         struct clk *clk_dp;
  37         struct clk *clk;
  38
  39         struct tegra_dpaux *dpaux;
  40
  41         struct mutex lock;
  42         bool enabled;
  43
  44         struct dentry *debugfs;
  45 };
  46
  47 struct tegra_sor_config {
  48         u32 bits_per_pixel;
  49
  50         u32 active_polarity;
  51         u32 active_count;
  52         u32 tu_size;
  53         u32 active_frac;
  54         u32 watermark;
  55
  56         u32 hblank_symbols;
  57         u32 vblank_symbols;
  58 };
  59
  60 static inline struct tegra_sor *
  61 host1x_client_to_sor(struct host1x_client *client)
  62 {
  63         return container_of(client, struct tegra_sor, client);
  64 }
  65
  66 static inline struct tegra_sor *to_sor(struct tegra_output *output)
  67 {
  68         return container_of(output, struct tegra_sor, output);
  69 }
  70
  71 static inline unsigned long tegra_sor_readl(struct tegra_sor *sor,
  72                                             unsigned long offset)
  73 {
  74         return readl(sor->regs + (offset << 2));
  75 }
  76
  77 static inline void tegra_sor_writel(struct tegra_sor *sor, unsigned long value,
  78                                     unsigned long offset)
  79 {
  80         writel(value, sor->regs + (offset << 2));
  81 }
  82
  83 static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
  84                                    struct drm_dp_link *link)
  85 {
  86         unsigned long value;
  87         unsigned int i;
  88         u8 pattern;
  89         int err;
  90
  91         /* setup lane parameters */
  92         value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) |
  93                 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) |
  94                 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) |
  95                 SOR_LANE_DRIVE_CURRENT_LANE0(0x40);
  96         tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT_0);
  97
  98         value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) |
  99                 SOR_LANE_PREEMPHASIS_LANE2(0x0f) |
 100                 SOR_LANE_PREEMPHASIS_LANE1(0x0f) |
 101                 SOR_LANE_PREEMPHASIS_LANE0(0x0f);
 102         tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS_0);
 103
 104         value = SOR_LANE_POST_CURSOR_LANE3(0x00) |
 105                 SOR_LANE_POST_CURSOR_LANE2(0x00) |
 106                 SOR_LANE_POST_CURSOR_LANE1(0x00) |
 107                 SOR_LANE_POST_CURSOR_LANE0(0x00);
 108         tegra_sor_writel(sor, value, SOR_LANE_POST_CURSOR_0);
 109
 110         /* disable LVDS mode */
 111         tegra_sor_writel(sor, 0, SOR_LVDS);
 112
 113         value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
 114         value |= SOR_DP_PADCTL_TX_PU_ENABLE;
 115         value &= ~SOR_DP_PADCTL_TX_PU_MASK;
 116         value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */
 117         tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
 118
 119         value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
 120         value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
 121                  SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0;
 122         tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
 123
 124         usleep_range(10, 100);
 125
 126         value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
 127         value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
 128                    SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
 129         tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
 130
 131         err = tegra_dpaux_prepare(sor->dpaux, DP_SET_ANSI_8B10B);
 132         if (err < 0)
 133                 return err;
 134
 135         for (i = 0, value = 0; i < link->num_lanes; i++) {
 136                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 137                                      SOR_DP_TPG_SCRAMBLER_NONE |
 138                                      SOR_DP_TPG_PATTERN_TRAIN1;
 139                 value = (value << 8) | lane;
 140         }
 141
 142         tegra_sor_writel(sor, value, SOR_DP_TPG);
 143
 144         pattern = DP_TRAINING_PATTERN_1;
 145
 146         err = tegra_dpaux_train(sor->dpaux, link, pattern);
 147         if (err < 0)
 148                 return err;
 149
 150         value = tegra_sor_readl(sor, SOR_DP_SPARE_0);
 151         value |= SOR_DP_SPARE_SEQ_ENABLE;
 152         value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
 153         value |= SOR_DP_SPARE_MACRO_SOR_CLK;
 154         tegra_sor_writel(sor, value, SOR_DP_SPARE_0);
 155
 156         for (i = 0, value = 0; i < link->num_lanes; i++) {
 157                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 158                                      SOR_DP_TPG_SCRAMBLER_NONE |
 159                                      SOR_DP_TPG_PATTERN_TRAIN2;
 160                 value = (value << 8) | lane;
 161         }
 162
 163         tegra_sor_writel(sor, value, SOR_DP_TPG);
 164
 165         pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2;
 166
 167         err = tegra_dpaux_train(sor->dpaux, link, pattern);
 168         if (err < 0)
 169                 return err;
 170
 171         for (i = 0, value = 0; i < link->num_lanes; i++) {
 172                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 173                                      SOR_DP_TPG_SCRAMBLER_GALIOS |
 174                                      SOR_DP_TPG_PATTERN_NONE;
 175                 value = (value << 8) | lane;
 176         }
 177
 178         tegra_sor_writel(sor, value, SOR_DP_TPG);
 179
 180         pattern = DP_TRAINING_PATTERN_DISABLE;
 181
 182         err = tegra_dpaux_train(sor->dpaux, link, pattern);
 183         if (err < 0)
 184                 return err;
 185
 186         return 0;
 187 }
 188
 189 static void tegra_sor_super_update(struct tegra_sor *sor)
 190 {
 191         tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0);
 192         tegra_sor_writel(sor, 1, SOR_SUPER_STATE_0);
 193         tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0);
 194 }
 195
 196 static void tegra_sor_update(struct tegra_sor *sor)
 197 {
 198         tegra_sor_writel(sor, 0, SOR_STATE_0);
 199         tegra_sor_writel(sor, 1, SOR_STATE_0);
 200         tegra_sor_writel(sor, 0, SOR_STATE_0);
 201 }
 202
 203 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
 204 {
 205         unsigned long value;
 206
 207         value = tegra_sor_readl(sor, SOR_PWM_DIV);
 208         value &= ~SOR_PWM_DIV_MASK;
 209         value |= 0x400; /* period */
 210         tegra_sor_writel(sor, value, SOR_PWM_DIV);
 211
 212         value = tegra_sor_readl(sor, SOR_PWM_CTL);
 213         value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
 214         value |= 0x400; /* duty cycle */
 215         value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
 216         value |= SOR_PWM_CTL_TRIGGER;
 217         tegra_sor_writel(sor, value, SOR_PWM_CTL);
 218
 219         timeout = jiffies + msecs_to_jiffies(timeout);
 220
 221         while (time_before(jiffies, timeout)) {
 222                 value = tegra_sor_readl(sor, SOR_PWM_CTL);
 223                 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
 224                         return 0;
 225
 226                 usleep_range(25, 100);
 227         }
 228
 229         return -ETIMEDOUT;
 230 }
 231
 232 static int tegra_sor_attach(struct tegra_sor *sor)
 233 {
 234         unsigned long value, timeout;
 235
 236         /* wake up in normal mode */
 237         value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
 238         value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
 239         value |= SOR_SUPER_STATE_MODE_NORMAL;
 240         tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
 241         tegra_sor_super_update(sor);
 242
 243         /* attach */
 244         value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
 245         value |= SOR_SUPER_STATE_ATTACHED;
 246         tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
 247         tegra_sor_super_update(sor);
 248
 249         timeout = jiffies + msecs_to_jiffies(250);
 250
 251         while (time_before(jiffies, timeout)) {
 252                 value = tegra_sor_readl(sor, SOR_TEST);
 253                 if ((value & SOR_TEST_ATTACHED) != 0)
 254                         return 0;
 255
 256                 usleep_range(25, 100);
 257         }
 258
 259         return -ETIMEDOUT;
 260 }
 261
 262 static int tegra_sor_wakeup(struct tegra_sor *sor)
 263 {
 264         unsigned long value, timeout;
 265
 266         timeout = jiffies + msecs_to_jiffies(250);
 267
 268         /* wait for head to wake up */
 269         while (time_before(jiffies, timeout)) {
 270                 value = tegra_sor_readl(sor, SOR_TEST);
 271                 value &= SOR_TEST_HEAD_MODE_MASK;
 272
 273                 if (value == SOR_TEST_HEAD_MODE_AWAKE)
 274                         return 0;
 275
 276                 usleep_range(25, 100);
 277         }
 278
 279         return -ETIMEDOUT;
 280 }
 281
 282 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
 283 {
 284         unsigned long value;
 285
 286         value = tegra_sor_readl(sor, SOR_PWR);
 287         value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
 288         tegra_sor_writel(sor, value, SOR_PWR);
 289
 290         timeout = jiffies + msecs_to_jiffies(timeout);
 291
 292         while (time_before(jiffies, timeout)) {
 293                 value = tegra_sor_readl(sor, SOR_PWR);
 294                 if ((value & SOR_PWR_TRIGGER) == 0)
 295                         return 0;
 296
 297                 usleep_range(25, 100);
 298         }
 299
 300         return -ETIMEDOUT;
 301 }
 302
 303 struct tegra_sor_params {
 304         /* number of link clocks per line */
 305         unsigned int num_clocks;
 306         /* ratio between input and output */
 307         u64 ratio;
 308         /* precision factor */
 309         u64 precision;
 310
 311         unsigned int active_polarity;
 312         unsigned int active_count;
 313         unsigned int active_frac;
 314         unsigned int tu_size;
 315         unsigned int error;
 316 };
 317
 318 static int tegra_sor_compute_params(struct tegra_sor *sor,
 319                                     struct tegra_sor_params *params,
 320                                     unsigned int tu_size)
 321 {
 322         u64 active_sym, active_count, frac, approx;
 323         u32 active_polarity, active_frac = 0;
 324         const u64 f = params->precision;
 325         s64 error;
 326
 327         active_sym = params->ratio * tu_size;
 328         active_count = div_u64(active_sym, f) * f;
 329         frac = active_sym - active_count;
 330
 331         /* fraction < 0.5 */
 332         if (frac >= (f / 2)) {
 333                 active_polarity = 1;
 334                 frac = f - frac;
 335         } else {
 336                 active_polarity = 0;
 337         }
 338
 339         if (frac != 0) {
 340                 frac = div_u64(f * f,  frac); /* 1/fraction */
 341                 if (frac <= (15 * f)) {
 342                         active_frac = div_u64(frac, f);
 343
 344                         /* round up */
 345                         if (active_polarity)
 346                                 active_frac++;
 347                 } else {
 348                         active_frac = active_polarity ? 1 : 15;
 349                 }
 350         }
 351
 352         if (active_frac == 1)
 353                 active_polarity = 0;
 354
 355         if (active_polarity == 1) {
 356                 if (active_frac) {
 357                         approx = active_count + (active_frac * (f - 1)) * f;
 358                         approx = div_u64(approx, active_frac * f);
 359                 } else {
 360                         approx = active_count + f;
 361                 }
 362         } else {
 363                 if (active_frac)
 364                         approx = active_count + div_u64(f, active_frac);
 365                 else
 366                         approx = active_count;
 367         }
 368
 369         error = div_s64(active_sym - approx, tu_size);
 370         error *= params->num_clocks;
 371
 372         if (error <= 0 && abs64(error) < params->error) {
 373                 params->active_count = div_u64(active_count, f);
 374                 params->active_polarity = active_polarity;
 375                 params->active_frac = active_frac;
 376                 params->error = abs64(error);
 377                 params->tu_size = tu_size;
 378
 379                 if (error == 0)
 380                         return true;
 381         }
 382
 383         return false;
 384 }
 385
 386 static int tegra_sor_calc_config(struct tegra_sor *sor,
 387                                  struct drm_display_mode *mode,
 388                                  struct tegra_sor_config *config,
 389                                  struct drm_dp_link *link)
 390 {
 391         const u64 f = 100000, link_rate = link->rate * 1000;
 392         const u64 pclk = mode->clock * 1000;
 393         u64 input, output, watermark, num;
 394         struct tegra_sor_params params;
 395         u32 num_syms_per_line;
 396         unsigned int i;
 397
 398         if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel)
 399                 return -EINVAL;
 400
 401         output = link_rate * 8 * link->num_lanes;
 402         input = pclk * config->bits_per_pixel;
 403
 404         if (input >= output)
 405                 return -ERANGE;
 406
 407         memset(&params, 0, sizeof(params));
 408         params.ratio = div64_u64(input * f, output);
 409         params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
 410         params.precision = f;
 411         params.error = 64 * f;
 412         params.tu_size = 64;
 413
 414         for (i = params.tu_size; i >= 32; i--)
 415                 if (tegra_sor_compute_params(sor, &params, i))
 416                         break;
 417
 418         if (params.active_frac == 0) {
 419                 config->active_polarity = 0;
 420                 config->active_count = params.active_count;
 421
 422                 if (!params.active_polarity)
 423                         config->active_count--;
 424
 425                 config->tu_size = params.tu_size;
 426                 config->active_frac = 1;
 427         } else {
 428                 config->active_polarity = params.active_polarity;
 429                 config->active_count = params.active_count;
 430                 config->active_frac = params.active_frac;
 431                 config->tu_size = params.tu_size;
 432         }
 433
 434         dev_dbg(sor->dev,
 435                 "polarity: %d active count: %d tu size: %d active frac: %d\n",
 436                 config->active_polarity, config->active_count,
 437                 config->tu_size, config->active_frac);
 438
 439         watermark = params.ratio * config->tu_size * (f - params.ratio);
 440         watermark = div_u64(watermark, f);
 441
 442         watermark = div_u64(watermark + params.error, f);
 443         config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
 444         num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
 445                             (link->num_lanes * 8);
 446
 447         if (config->watermark > 30) {
 448                 config->watermark = 30;
 449                 dev_err(sor->dev,
 450                         "unable to compute TU size, forcing watermark to %u\n",
 451                         config->watermark);
 452         } else if (config->watermark > num_syms_per_line) {
 453                 config->watermark = num_syms_per_line;
 454                 dev_err(sor->dev, "watermark too high, forcing to %u\n",
 455                         config->watermark);
 456         }
 457
 458         /* compute the number of symbols per horizontal blanking interval */
 459         num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
 460         config->hblank_symbols = div_u64(num, pclk);
 461
 462         if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
 463                 config->hblank_symbols -= 3;
 464
 465         config->hblank_symbols -= 12 / link->num_lanes;
 466
 467         /* compute the number of symbols per vertical blanking interval */
 468         num = (mode->hdisplay - 25) * link_rate;
 469         config->vblank_symbols = div_u64(num, pclk);
 470         config->vblank_symbols -= 36 / link->num_lanes + 4;
 471
 472         dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
 473                 config->vblank_symbols);
 474
 475         return 0;
 476 }
 477
 478 static int tegra_sor_detach(struct tegra_sor *sor)
 479 {
 480         unsigned long value, timeout;
 481
 482         /* switch to safe mode */
 483         value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
 484         value &= ~SOR_SUPER_STATE_MODE_NORMAL;
 485         tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
 486         tegra_sor_super_update(sor);
 487
 488         timeout = jiffies + msecs_to_jiffies(250);
 489
 490         while (time_before(jiffies, timeout)) {
 491                 value = tegra_sor_readl(sor, SOR_PWR);
 492                 if (value & SOR_PWR_MODE_SAFE)
 493                         break;
 494         }
 495
 496         if ((value & SOR_PWR_MODE_SAFE) == 0)
 497                 return -ETIMEDOUT;
 498
 499         /* go to sleep */
 500         value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
 501         value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
 502         tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
 503         tegra_sor_super_update(sor);
 504
 505         /* detach */
 506         value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
 507         value &= ~SOR_SUPER_STATE_ATTACHED;
 508         tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
 509         tegra_sor_super_update(sor);
 510
 511         timeout = jiffies + msecs_to_jiffies(250);
 512
 513         while (time_before(jiffies, timeout)) {
 514                 value = tegra_sor_readl(sor, SOR_TEST);
 515                 if ((value & SOR_TEST_ATTACHED) == 0)
 516                         break;
 517
 518                 usleep_range(25, 100);
 519         }
 520
 521         if ((value & SOR_TEST_ATTACHED) != 0)
 522                 return -ETIMEDOUT;
 523
 524         return 0;
 525 }
 526
 527 static int tegra_sor_power_down(struct tegra_sor *sor)
 528 {
 529         unsigned long value, timeout;
 530         int err;
 531
 532         value = tegra_sor_readl(sor, SOR_PWR);
 533         value &= ~SOR_PWR_NORMAL_STATE_PU;
 534         value |= SOR_PWR_TRIGGER;
 535         tegra_sor_writel(sor, value, SOR_PWR);
 536
 537         timeout = jiffies + msecs_to_jiffies(250);
 538
 539         while (time_before(jiffies, timeout)) {
 540                 value = tegra_sor_readl(sor, SOR_PWR);
 541                 if ((value & SOR_PWR_TRIGGER) == 0)
 542                         return 0;
 543
 544                 usleep_range(25, 100);
 545         }
 546
 547         if ((value & SOR_PWR_TRIGGER) != 0)
 548                 return -ETIMEDOUT;
 549
 550         err = clk_set_parent(sor->clk, sor->clk_safe);
 551         if (err < 0)
 552                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
 553
 554         value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
 555         value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
 556                    SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
 557         tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
 558
 559         /* stop lane sequencer */
 560         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
 561                 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
 562         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
 563
 564         timeout = jiffies + msecs_to_jiffies(250);
 565
 566         while (time_before(jiffies, timeout)) {
 567                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
 568                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
 569                         break;
 570
 571                 usleep_range(25, 100);
 572         }
 573
 574         if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
 575                 return -ETIMEDOUT;
 576
 577         value = tegra_sor_readl(sor, SOR_PLL_2);
 578         value |= SOR_PLL_2_PORT_POWERDOWN;
 579         tegra_sor_writel(sor, value, SOR_PLL_2);
 580
 581         usleep_range(20, 100);
 582
 583         value = tegra_sor_readl(sor, SOR_PLL_0);
 584         value |= SOR_PLL_0_POWER_OFF;
 585         value |= SOR_PLL_0_VCOPD;
 586         tegra_sor_writel(sor, value, SOR_PLL_0);
 587
 588         value = tegra_sor_readl(sor, SOR_PLL_2);
 589         value |= SOR_PLL_2_SEQ_PLLCAPPD;
 590         value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE;
 591         tegra_sor_writel(sor, value, SOR_PLL_2);
 592
 593         usleep_range(20, 100);
 594
 595         return 0;
 596 }
 597
 598 static int tegra_sor_crc_open(struct inode *inode, struct file *file)
 599 {
 600         file->private_data = inode->i_private;
 601
 602         return 0;
 603 }
 604
 605 static int tegra_sor_crc_release(struct inode *inode, struct file *file)
 606 {
 607         return 0;
 608 }
 609
 610 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
 611 {
 612         u32 value;
 613
 614         timeout = jiffies + msecs_to_jiffies(timeout);
 615
 616         while (time_before(jiffies, timeout)) {
 617                 value = tegra_sor_readl(sor, SOR_CRC_A);
 618                 if (value & SOR_CRC_A_VALID)
 619                         return 0;
 620
 621                 usleep_range(100, 200);
 622         }
 623
 624         return -ETIMEDOUT;
 625 }
 626
 627 static ssize_t tegra_sor_crc_read(struct file *file, char __user *buffer,
 628                                   size_t size, loff_t *ppos)
 629 {
 630         struct tegra_sor *sor = file->private_data;
 631         ssize_t num, err;
 632         char buf[10];
 633         u32 value;
 634
 635         mutex_lock(&sor->lock);
 636
 637         if (!sor->enabled) {
 638                 err = -EAGAIN;
 639                 goto unlock;
 640         }
 641
 642         value = tegra_sor_readl(sor, SOR_STATE_1);
 643         value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
 644         tegra_sor_writel(sor, value, SOR_STATE_1);
 645
 646         value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
 647         value |= SOR_CRC_CNTRL_ENABLE;
 648         tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
 649
 650         value = tegra_sor_readl(sor, SOR_TEST);
 651         value &= ~SOR_TEST_CRC_POST_SERIALIZE;
 652         tegra_sor_writel(sor, value, SOR_TEST);
 653
 654         err = tegra_sor_crc_wait(sor, 100);
 655         if (err < 0)
 656                 goto unlock;
 657
 658         tegra_sor_writel(sor, SOR_CRC_A_RESET, SOR_CRC_A);
 659         value = tegra_sor_readl(sor, SOR_CRC_B);
 660
 661         num = scnprintf(buf, sizeof(buf), "%08x\n", value);
 662
 663         err = simple_read_from_buffer(buffer, size, ppos, buf, num);
 664
 665 unlock:
 666         mutex_unlock(&sor->lock);
 667         return err;
 668 }
 669
 670 static const struct file_operations tegra_sor_crc_fops = {
 671         .owner = THIS_MODULE,
 672         .open = tegra_sor_crc_open,
 673         .read = tegra_sor_crc_read,
 674         .release = tegra_sor_crc_release,
 675 };
 676
 677 static int tegra_sor_debugfs_init(struct tegra_sor *sor,
 678                                   struct drm_minor *minor)
 679 {
 680         struct dentry *entry;
 681         int err = 0;
 682
 683         sor->debugfs = debugfs_create_dir("sor", minor->debugfs_root);
 684         if (!sor->debugfs)
 685                 return -ENOMEM;
 686
 687         entry = debugfs_create_file("crc", 0644, sor->debugfs, sor,
 688                                     &tegra_sor_crc_fops);
 689         if (!entry) {
 690                 dev_err(sor->dev,
 691                         "cannot create /sys/kernel/debug/dri/%s/sor/crc\n",
 692                         minor->debugfs_root->d_name.name);
 693                 err = -ENOMEM;
 694                 goto remove;
 695         }
 696
 697         return err;
 698
 699 remove:
 700         debugfs_remove(sor->debugfs);
 701         sor->debugfs = NULL;
 702         return err;
 703 }
 704
 705 static void tegra_sor_debugfs_exit(struct tegra_sor *sor)
 706 {
 707         debugfs_remove_recursive(sor->debugfs);
 708         sor->debugfs = NULL;
 709 }
 710
 711 static void tegra_sor_connector_dpms(struct drm_connector *connector, int mode)
 712 {
 713 }
 714
 715 static enum drm_connector_status
 716 tegra_sor_connector_detect(struct drm_connector *connector, bool force)
 717 {
 718         struct tegra_output *output = connector_to_output(connector);
 719         struct tegra_sor *sor = to_sor(output);
 720
 721         if (sor->dpaux)
 722                 return tegra_dpaux_detect(sor->dpaux);
 723
 724         return connector_status_unknown;
 725 }
 726
 727 static const struct drm_connector_funcs tegra_sor_connector_funcs = {
 728         .dpms = tegra_sor_connector_dpms,
 729         .reset = drm_atomic_helper_connector_reset,
 730         .detect = tegra_sor_connector_detect,
 731         .fill_modes = drm_helper_probe_single_connector_modes,
 732         .destroy = tegra_output_connector_destroy,
 733         .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
 734         .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
 735 };
 736
 737 static int tegra_sor_connector_get_modes(struct drm_connector *connector)
 738 {
 739         struct tegra_output *output = connector_to_output(connector);
 740         struct tegra_sor *sor = to_sor(output);
 741         int err;
 742
 743         if (sor->dpaux)
 744                 tegra_dpaux_enable(sor->dpaux);
 745
 746         err = tegra_output_connector_get_modes(connector);
 747
 748         if (sor->dpaux)
 749                 tegra_dpaux_disable(sor->dpaux);
 750
 751         return err;
 752 }
 753
 754 static enum drm_mode_status
 755 tegra_sor_connector_mode_valid(struct drm_connector *connector,
 756                                struct drm_display_mode *mode)
 757 {
 758         return MODE_OK;
 759 }
 760
 761 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
 762         .get_modes = tegra_sor_connector_get_modes,
 763         .mode_valid = tegra_sor_connector_mode_valid,
 764         .best_encoder = tegra_output_connector_best_encoder,
 765 };
 766
 767 static const struct drm_encoder_funcs tegra_sor_encoder_funcs = {
 768         .destroy = tegra_output_encoder_destroy,
 769 };
 770
 771 static void tegra_sor_encoder_dpms(struct drm_encoder *encoder, int mode)
 772 {
 773 }
 774
 775 static void tegra_sor_encoder_prepare(struct drm_encoder *encoder)
 776 {
 777 }
 778
 779 static void tegra_sor_encoder_commit(struct drm_encoder *encoder)
 780 {
 781 }
 782
 783 static void tegra_sor_encoder_mode_set(struct drm_encoder *encoder,
 784                                        struct drm_display_mode *mode,
 785                                        struct drm_display_mode *adjusted)
 786 {
 787         struct tegra_output *output = encoder_to_output(encoder);
 788         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
 789         unsigned int vbe, vse, hbe, hse, vbs, hbs, i;
 790         struct tegra_sor *sor = to_sor(output);
 791         struct tegra_sor_config config;
 792         struct drm_dp_link link;
 793         struct drm_dp_aux *aux;
 794         unsigned long value;
 795         int err = 0;
 796
 797         mutex_lock(&sor->lock);
 798
 799         if (sor->enabled)
 800                 goto unlock;
 801
 802         err = clk_prepare_enable(sor->clk);
 803         if (err < 0)
 804                 goto unlock;
 805
 806         reset_control_deassert(sor->rst);
 807
 808         if (output->panel)
 809                 drm_panel_prepare(output->panel);
 810
 811         /* FIXME: properly convert to struct drm_dp_aux */
 812         aux = (struct drm_dp_aux *)sor->dpaux;
 813
 814         if (sor->dpaux) {
 815                 err = tegra_dpaux_enable(sor->dpaux);
 816                 if (err < 0)
 817                         dev_err(sor->dev, "failed to enable DP: %d\n", err);
 818
 819                 err = drm_dp_link_probe(aux, &link);
 820                 if (err < 0) {
 821                         dev_err(sor->dev, "failed to probe eDP link: %d\n",
 822                                 err);
 823                         goto unlock;
 824                 }
 825         }
 826
 827         err = clk_set_parent(sor->clk, sor->clk_safe);
 828         if (err < 0)
 829                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
 830
 831         memset(&config, 0, sizeof(config));
 832         config.bits_per_pixel = output->connector.display_info.bpc * 3;
 833
 834         err = tegra_sor_calc_config(sor, mode, &config, &link);
 835         if (err < 0)
 836                 dev_err(sor->dev, "failed to compute link configuration: %d\n",
 837                         err);
 838
 839         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 840         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
 841         value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
 842         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 843
 844         value = tegra_sor_readl(sor, SOR_PLL_2);
 845         value &= ~SOR_PLL_2_BANDGAP_POWERDOWN;
 846         tegra_sor_writel(sor, value, SOR_PLL_2);
 847         usleep_range(20, 100);
 848
 849         value = tegra_sor_readl(sor, SOR_PLL_3);
 850         value |= SOR_PLL_3_PLL_VDD_MODE_V3_3;
 851         tegra_sor_writel(sor, value, SOR_PLL_3);
 852
 853         value = SOR_PLL_0_ICHPMP(0xf) | SOR_PLL_0_VCOCAP_RST |
 854                 SOR_PLL_0_PLLREG_LEVEL_V45 | SOR_PLL_0_RESISTOR_EXT;
 855         tegra_sor_writel(sor, value, SOR_PLL_0);
 856
 857         value = tegra_sor_readl(sor, SOR_PLL_2);
 858         value |= SOR_PLL_2_SEQ_PLLCAPPD;
 859         value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE;
 860         value |= SOR_PLL_2_LVDS_ENABLE;
 861         tegra_sor_writel(sor, value, SOR_PLL_2);
 862
 863         value = SOR_PLL_1_TERM_COMPOUT | SOR_PLL_1_TMDS_TERM;
 864         tegra_sor_writel(sor, value, SOR_PLL_1);
 865
 866         while (true) {
 867                 value = tegra_sor_readl(sor, SOR_PLL_2);
 868                 if ((value & SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE) == 0)
 869                         break;
 870
 871                 usleep_range(250, 1000);
 872         }
 873
 874         value = tegra_sor_readl(sor, SOR_PLL_2);
 875         value &= ~SOR_PLL_2_POWERDOWN_OVERRIDE;
 876         value &= ~SOR_PLL_2_PORT_POWERDOWN;
 877         tegra_sor_writel(sor, value, SOR_PLL_2);
 878
 879         /*
 880          * power up
 881          */
 882
 883         /* set safe link bandwidth (1.62 Gbps) */
 884         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 885         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
 886         value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62;
 887         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 888
 889         /* step 1 */
 890         value = tegra_sor_readl(sor, SOR_PLL_2);
 891         value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL_2_PORT_POWERDOWN |
 892                  SOR_PLL_2_BANDGAP_POWERDOWN;
 893         tegra_sor_writel(sor, value, SOR_PLL_2);
 894
 895         value = tegra_sor_readl(sor, SOR_PLL_0);
 896         value |= SOR_PLL_0_VCOPD | SOR_PLL_0_POWER_OFF;
 897         tegra_sor_writel(sor, value, SOR_PLL_0);
 898
 899         value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
 900         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
 901         tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
 902
 903         /* step 2 */
 904         err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS);
 905         if (err < 0) {
 906                 dev_err(sor->dev, "failed to power on I/O rail: %d\n", err);
 907                 goto unlock;
 908         }
 909
 910         usleep_range(5, 100);
 911
 912         /* step 3 */
 913         value = tegra_sor_readl(sor, SOR_PLL_2);
 914         value &= ~SOR_PLL_2_BANDGAP_POWERDOWN;
 915         tegra_sor_writel(sor, value, SOR_PLL_2);
 916
 917         usleep_range(20, 100);
 918
 919         /* step 4 */
 920         value = tegra_sor_readl(sor, SOR_PLL_0);
 921         value &= ~SOR_PLL_0_POWER_OFF;
 922         value &= ~SOR_PLL_0_VCOPD;
 923         tegra_sor_writel(sor, value, SOR_PLL_0);
 924
 925         value = tegra_sor_readl(sor, SOR_PLL_2);
 926         value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE;
 927         tegra_sor_writel(sor, value, SOR_PLL_2);
 928
 929         usleep_range(200, 1000);
 930
 931         /* step 5 */
 932         value = tegra_sor_readl(sor, SOR_PLL_2);
 933         value &= ~SOR_PLL_2_PORT_POWERDOWN;
 934         tegra_sor_writel(sor, value, SOR_PLL_2);
 935
 936         /* switch to DP clock */
 937         err = clk_set_parent(sor->clk, sor->clk_dp);
 938         if (err < 0)
 939                 dev_err(sor->dev, "failed to set DP parent clock: %d\n", err);
 940
 941         /* power DP lanes */
 942         value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
 943
 944         if (link.num_lanes <= 2)
 945                 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2);
 946         else
 947                 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2;
 948
 949         if (link.num_lanes <= 1)
 950                 value &= ~SOR_DP_PADCTL_PD_TXD_1;
 951         else
 952                 value |= SOR_DP_PADCTL_PD_TXD_1;
 953
 954         if (link.num_lanes == 0)
 955                 value &= ~SOR_DP_PADCTL_PD_TXD_0;
 956         else
 957                 value |= SOR_DP_PADCTL_PD_TXD_0;
 958
 959         tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
 960
 961         value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0);
 962         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
 963         value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes);
 964         tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);
 965
 966         /* start lane sequencer */
 967         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
 968                 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
 969         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
 970
 971         while (true) {
 972                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
 973                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
 974                         break;
 975
 976                 usleep_range(250, 1000);
 977         }
 978
 979         /* set link bandwidth */
 980         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 981         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
 982         value |= drm_dp_link_rate_to_bw_code(link.rate) << 2;
 983         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 984
 985         /* set linkctl */
 986         value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0);
 987         value |= SOR_DP_LINKCTL_ENABLE;
 988
 989         value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
 990         value |= SOR_DP_LINKCTL_TU_SIZE(config.tu_size);
 991
 992         value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
 993         tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);
 994
 995         for (i = 0, value = 0; i < 4; i++) {
 996                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 997                                      SOR_DP_TPG_SCRAMBLER_GALIOS |
 998                                      SOR_DP_TPG_PATTERN_NONE;
 999                 value = (value << 8) | lane;
1000         }
1001
1002         tegra_sor_writel(sor, value, SOR_DP_TPG);
1003
1004         value = tegra_sor_readl(sor, SOR_DP_CONFIG_0);
1005         value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
1006         value |= SOR_DP_CONFIG_WATERMARK(config.watermark);
1007
1008         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
1009         value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config.active_count);
1010
1011         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
1012         value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config.active_frac);
1013
1014         if (config.active_polarity)
1015                 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1016         else
1017                 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1018
1019         value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
1020         value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
1021         tegra_sor_writel(sor, value, SOR_DP_CONFIG_0);
1022
1023         value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1024         value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
1025         value |= config.hblank_symbols & 0xffff;
1026         tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1027
1028         value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1029         value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
1030         value |= config.vblank_symbols & 0xffff;
1031         tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1032
1033         /* enable pad calibration logic */
1034         value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
1035         value |= SOR_DP_PADCTL_PAD_CAL_PD;
1036         tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
1037
1038         if (sor->dpaux) {
1039                 u8 rate, lanes;
1040
1041                 err = drm_dp_link_probe(aux, &link);
1042                 if (err < 0) {
1043                         dev_err(sor->dev, "failed to probe eDP link: %d\n",
1044                                 err);
1045                         goto unlock;
1046                 }
1047
1048                 err = drm_dp_link_power_up(aux, &link);
1049                 if (err < 0) {
1050                         dev_err(sor->dev, "failed to power up eDP link: %d\n",
1051                                 err);
1052                         goto unlock;
1053                 }
1054
1055                 err = drm_dp_link_configure(aux, &link);
1056                 if (err < 0) {
1057                         dev_err(sor->dev, "failed to configure eDP link: %d\n",
1058                                 err);
1059                         goto unlock;
1060                 }
1061
1062                 rate = drm_dp_link_rate_to_bw_code(link.rate);
1063                 lanes = link.num_lanes;
1064
1065                 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1066                 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1067                 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
1068                 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1069
1070                 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0);
1071                 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1072                 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
1073
1074                 if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1075                         value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1076
1077                 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);
1078
1079                 /* disable training pattern generator */
1080
1081                 for (i = 0; i < link.num_lanes; i++) {
1082                         unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1083                                              SOR_DP_TPG_SCRAMBLER_GALIOS |
1084                                              SOR_DP_TPG_PATTERN_NONE;
1085                         value = (value << 8) | lane;
1086                 }
1087
1088                 tegra_sor_writel(sor, value, SOR_DP_TPG);
1089
1090                 err = tegra_sor_dp_train_fast(sor, &link);
1091                 if (err < 0) {
1092                         dev_err(sor->dev, "DP fast link training failed: %d\n",
1093                                 err);
1094                         goto unlock;
1095                 }
1096
1097                 dev_dbg(sor->dev, "fast link training succeeded\n");
1098         }
1099
1100         err = tegra_sor_power_up(sor, 250);
1101         if (err < 0) {
1102                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
1103                 goto unlock;
1104         }
1105
1106         /*
1107          * configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete
1108          * raster, associate with display controller)
1109          */
1110         value = SOR_STATE_ASY_PROTOCOL_DP_A |
1111                 SOR_STATE_ASY_CRC_MODE_COMPLETE |
1112                 SOR_STATE_ASY_OWNER(dc->pipe + 1);
1113
1114         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1115                 value &= ~SOR_STATE_ASY_HSYNCPOL;
1116
1117         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1118                 value |= SOR_STATE_ASY_HSYNCPOL;
1119
1120         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1121                 value &= ~SOR_STATE_ASY_VSYNCPOL;
1122
1123         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1124                 value |= SOR_STATE_ASY_VSYNCPOL;
1125
1126         switch (config.bits_per_pixel) {
1127         case 24:
1128                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1129                 break;
1130
1131         case 18:
1132                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
1133                 break;
1134
1135         default:
1136                 BUG();
1137                 break;
1138         }
1139
1140         tegra_sor_writel(sor, value, SOR_STATE_1);
1141
1142         /*
1143          * TODO: The video timing programming below doesn't seem to match the
1144          * register definitions.
1145          */
1146
1147         value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
1148         tegra_sor_writel(sor, value, SOR_HEAD_STATE_1(0));
1149
1150         vse = mode->vsync_end - mode->vsync_start - 1;
1151         hse = mode->hsync_end - mode->hsync_start - 1;
1152
1153         value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
1154         tegra_sor_writel(sor, value, SOR_HEAD_STATE_2(0));
1155
1156         vbe = vse + (mode->vsync_start - mode->vdisplay);
1157         hbe = hse + (mode->hsync_start - mode->hdisplay);
1158
1159         value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
1160         tegra_sor_writel(sor, value, SOR_HEAD_STATE_3(0));
1161
1162         vbs = vbe + mode->vdisplay;
1163         hbs = hbe + mode->hdisplay;
1164
1165         value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
1166         tegra_sor_writel(sor, value, SOR_HEAD_STATE_4(0));
1167
1168         /* CSTM (LVDS, link A/B, upper) */
1169         value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
1170                 SOR_CSTM_UPPER;
1171         tegra_sor_writel(sor, value, SOR_CSTM);
1172
1173         /* PWM setup */
1174         err = tegra_sor_setup_pwm(sor, 250);
1175         if (err < 0) {
1176                 dev_err(sor->dev, "failed to setup PWM: %d\n", err);
1177                 goto unlock;
1178         }
1179
1180         tegra_sor_update(sor);
1181
1182         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1183         value |= SOR_ENABLE;
1184         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1185
1186         tegra_dc_commit(dc);
1187
1188         err = tegra_sor_attach(sor);
1189         if (err < 0) {
1190                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
1191                 goto unlock;
1192         }
1193
1194         err = tegra_sor_wakeup(sor);
1195         if (err < 0) {
1196                 dev_err(sor->dev, "failed to enable DC: %d\n", err);
1197                 goto unlock;
1198         }
1199
1200         if (output->panel)
1201                 drm_panel_enable(output->panel);
1202
1203         sor->enabled = true;
1204
1205 unlock:
1206         mutex_unlock(&sor->lock);
1207 }
1208
1209 static void tegra_sor_encoder_disable(struct drm_encoder *encoder)
1210 {
1211         struct tegra_output *output = encoder_to_output(encoder);
1212         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1213         struct tegra_sor *sor = to_sor(output);
1214         u32 value;
1215         int err;
1216
1217         mutex_lock(&sor->lock);
1218
1219         if (!sor->enabled)
1220                 goto unlock;
1221
1222         if (output->panel)
1223                 drm_panel_disable(output->panel);
1224
1225         err = tegra_sor_detach(sor);
1226         if (err < 0) {
1227                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
1228                 goto unlock;
1229         }
1230
1231         tegra_sor_writel(sor, 0, SOR_STATE_1);
1232         tegra_sor_update(sor);
1233
1234         /*
1235          * The following accesses registers of the display controller, so make
1236          * sure it's only executed when the output is attached to one.
1237          */
1238         if (dc) {
1239                 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1240                 value &= ~SOR_ENABLE;
1241                 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1242
1243                 tegra_dc_commit(dc);
1244         }
1245
1246         err = tegra_sor_power_down(sor);
1247         if (err < 0) {
1248                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1249                 goto unlock;
1250         }
1251
1252         if (sor->dpaux) {
1253                 err = tegra_dpaux_disable(sor->dpaux);
1254                 if (err < 0) {
1255                         dev_err(sor->dev, "failed to disable DP: %d\n", err);
1256                         goto unlock;
1257                 }
1258         }
1259
1260         err = tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS);
1261         if (err < 0) {
1262                 dev_err(sor->dev, "failed to power off I/O rail: %d\n", err);
1263                 goto unlock;
1264         }
1265
1266         if (output->panel)
1267                 drm_panel_unprepare(output->panel);
1268
1269         clk_disable_unprepare(sor->clk);
1270         reset_control_assert(sor->rst);
1271
1272         sor->enabled = false;
1273
1274 unlock:
1275         mutex_unlock(&sor->lock);
1276 }
1277
1278 static int
1279 tegra_sor_encoder_atomic_check(struct drm_encoder *encoder,
1280                                struct drm_crtc_state *crtc_state,
1281                                struct drm_connector_state *conn_state)
1282 {
1283         struct tegra_output *output = encoder_to_output(encoder);
1284         struct tegra_dc *dc = to_tegra_dc(conn_state->crtc);
1285         unsigned long pclk = crtc_state->mode.clock * 1000;
1286         struct tegra_sor *sor = to_sor(output);
1287         int err;
1288
1289         err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent,
1290                                          pclk, 0);
1291         if (err < 0) {
1292                 dev_err(output->dev, "failed to setup CRTC state: %d\n", err);
1293                 return err;
1294         }
1295
1296         return 0;
1297 }
1298
1299 static const struct drm_encoder_helper_funcs tegra_sor_encoder_helper_funcs = {
1300         .dpms = tegra_sor_encoder_dpms,
1301         .prepare = tegra_sor_encoder_prepare,
1302         .commit = tegra_sor_encoder_commit,
1303         .mode_set = tegra_sor_encoder_mode_set,
1304         .disable = tegra_sor_encoder_disable,
1305         .atomic_check = tegra_sor_encoder_atomic_check,
1306 };
1307
1308 static int tegra_sor_init(struct host1x_client *client)
1309 {
1310         struct drm_device *drm = dev_get_drvdata(client->parent);
1311         struct tegra_sor *sor = host1x_client_to_sor(client);
1312         int err;
1313
1314         if (!sor->dpaux)
1315                 return -ENODEV;
1316
1317         sor->output.dev = sor->dev;
1318
1319         drm_connector_init(drm, &sor->output.connector,
1320                            &tegra_sor_connector_funcs,
1321                            DRM_MODE_CONNECTOR_eDP);
1322         drm_connector_helper_add(&sor->output.connector,
1323                                  &tegra_sor_connector_helper_funcs);
1324         sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
1325
1326         drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs,
1327                          DRM_MODE_ENCODER_TMDS);
1328         drm_encoder_helper_add(&sor->output.encoder,
1329                                &tegra_sor_encoder_helper_funcs);
1330
1331         drm_mode_connector_attach_encoder(&sor->output.connector,
1332                                           &sor->output.encoder);
1333         drm_connector_register(&sor->output.connector);
1334
1335         err = tegra_output_init(drm, &sor->output);
1336         if (err < 0) {
1337                 dev_err(client->dev, "failed to initialize output: %d\n", err);
1338                 return err;
1339         }
1340
1341         sor->output.encoder.possible_crtcs = 0x3;
1342
1343         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1344                 err = tegra_sor_debugfs_init(sor, drm->primary);
1345                 if (err < 0)
1346                         dev_err(sor->dev, "debugfs setup failed: %d\n", err);
1347         }
1348
1349         if (sor->dpaux) {
1350                 err = tegra_dpaux_attach(sor->dpaux, &sor->output);
1351                 if (err < 0) {
1352                         dev_err(sor->dev, "failed to attach DP: %d\n", err);
1353                         return err;
1354                 }
1355         }
1356
1357         err = clk_prepare_enable(sor->clk);
1358         if (err < 0) {
1359                 dev_err(sor->dev, "failed to enable clock: %d\n", err);
1360                 return err;
1361         }
1362
1363         err = clk_prepare_enable(sor->clk_safe);
1364         if (err < 0)
1365                 return err;
1366
1367         err = clk_prepare_enable(sor->clk_dp);
1368         if (err < 0)
1369                 return err;
1370
1371         return 0;
1372 }
1373
1374 static int tegra_sor_exit(struct host1x_client *client)
1375 {
1376         struct tegra_sor *sor = host1x_client_to_sor(client);
1377         int err;
1378
1379         tegra_output_exit(&sor->output);
1380
1381         if (sor->dpaux) {
1382                 err = tegra_dpaux_detach(sor->dpaux);
1383                 if (err < 0) {
1384                         dev_err(sor->dev, "failed to detach DP: %d\n", err);
1385                         return err;
1386                 }
1387         }
1388
1389         clk_disable_unprepare(sor->clk_safe);
1390         clk_disable_unprepare(sor->clk_dp);
1391         clk_disable_unprepare(sor->clk);
1392
1393         if (IS_ENABLED(CONFIG_DEBUG_FS))
1394                 tegra_sor_debugfs_exit(sor);
1395
1396         return 0;
1397 }
1398
1399 static const struct host1x_client_ops sor_client_ops = {
1400         .init = tegra_sor_init,
1401         .exit = tegra_sor_exit,
1402 };
1403
1404 static int tegra_sor_probe(struct platform_device *pdev)
1405 {
1406         struct device_node *np;
1407         struct tegra_sor *sor;
1408         struct resource *regs;
1409         int err;
1410
1411         sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
1412         if (!sor)
1413                 return -ENOMEM;
1414
1415         sor->output.dev = sor->dev = &pdev->dev;
1416
1417         np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
1418         if (np) {
1419                 sor->dpaux = tegra_dpaux_find_by_of_node(np);
1420                 of_node_put(np);
1421
1422                 if (!sor->dpaux)
1423                         return -EPROBE_DEFER;
1424         }
1425
1426         err = tegra_output_probe(&sor->output);
1427         if (err < 0)
1428                 return err;
1429
1430         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1431         sor->regs = devm_ioremap_resource(&pdev->dev, regs);
1432         if (IS_ERR(sor->regs))
1433                 return PTR_ERR(sor->regs);
1434
1435         sor->rst = devm_reset_control_get(&pdev->dev, "sor");
1436         if (IS_ERR(sor->rst))
1437                 return PTR_ERR(sor->rst);
1438
1439         sor->clk = devm_clk_get(&pdev->dev, NULL);
1440         if (IS_ERR(sor->clk))
1441                 return PTR_ERR(sor->clk);
1442
1443         sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
1444         if (IS_ERR(sor->clk_parent))
1445                 return PTR_ERR(sor->clk_parent);
1446
1447         sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
1448         if (IS_ERR(sor->clk_safe))
1449                 return PTR_ERR(sor->clk_safe);
1450
1451         sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
1452         if (IS_ERR(sor->clk_dp))
1453                 return PTR_ERR(sor->clk_dp);
1454
1455         INIT_LIST_HEAD(&sor->client.list);
1456         sor->client.ops = &sor_client_ops;
1457         sor->client.dev = &pdev->dev;
1458
1459         mutex_init(&sor->lock);
1460
1461         err = host1x_client_register(&sor->client);
1462         if (err < 0) {
1463                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1464                         err);
1465                 return err;
1466         }
1467
1468         platform_set_drvdata(pdev, sor);
1469
1470         return 0;
1471 }
1472
1473 static int tegra_sor_remove(struct platform_device *pdev)
1474 {
1475         struct tegra_sor *sor = platform_get_drvdata(pdev);
1476         int err;
1477
1478         err = host1x_client_unregister(&sor->client);
1479         if (err < 0) {
1480                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1481                         err);
1482                 return err;
1483         }
1484
1485         tegra_output_remove(&sor->output);
1486
1487         return 0;
1488 }
1489
1490 static const struct of_device_id tegra_sor_of_match[] = {
1491         { .compatible = "nvidia,tegra124-sor", },
1492         { },
1493 };
1494 MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
1495
1496 struct platform_driver tegra_sor_driver = {
1497         .driver = {
1498                 .name = "tegra-sor",
1499                 .of_match_table = tegra_sor_of_match,
1500         },
1501         .probe = tegra_sor_probe,
1502         .remove = tegra_sor_remove,
1503 };