2 * Copyright (C) 2013 NVIDIA Corporation
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
11 #include <linux/platform_device.h>
12 #include <linux/reset.h>
13 #include <linux/tegra-powergate.h>
15 #include <drm/drm_dp_helper.h>
22 struct host1x_client client;
23 struct tegra_output output;
28 struct reset_control *rst;
29 struct clk *clk_parent;
34 struct tegra_dpaux *dpaux;
39 static inline struct tegra_sor *
40 host1x_client_to_sor(struct host1x_client *client)
42 return container_of(client, struct tegra_sor, client);
45 static inline struct tegra_sor *to_sor(struct tegra_output *output)
47 return container_of(output, struct tegra_sor, output);
50 static inline unsigned long tegra_sor_readl(struct tegra_sor *sor,
53 return readl(sor->regs + (offset << 2));
56 static inline void tegra_sor_writel(struct tegra_sor *sor, unsigned long value,
59 writel(value, sor->regs + (offset << 2));
62 static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
63 struct drm_dp_link *link)
70 /* setup lane parameters */
71 value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) |
72 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) |
73 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) |
74 SOR_LANE_DRIVE_CURRENT_LANE0(0x40);
75 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT_0);
77 value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) |
78 SOR_LANE_PREEMPHASIS_LANE2(0x0f) |
79 SOR_LANE_PREEMPHASIS_LANE1(0x0f) |
80 SOR_LANE_PREEMPHASIS_LANE0(0x0f);
81 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS_0);
83 value = SOR_LANE_POST_CURSOR_LANE3(0x00) |
84 SOR_LANE_POST_CURSOR_LANE2(0x00) |
85 SOR_LANE_POST_CURSOR_LANE1(0x00) |
86 SOR_LANE_POST_CURSOR_LANE0(0x00);
87 tegra_sor_writel(sor, value, SOR_LANE_POST_CURSOR_0);
89 /* disable LVDS mode */
90 tegra_sor_writel(sor, 0, SOR_LVDS);
92 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
93 value |= SOR_DP_PADCTL_TX_PU_ENABLE;
94 value &= ~SOR_DP_PADCTL_TX_PU_MASK;
95 value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */
96 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
98 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
99 value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
100 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0;
101 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
103 usleep_range(10, 100);
105 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
106 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
107 SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
108 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
110 err = tegra_dpaux_prepare(sor->dpaux, DP_SET_ANSI_8B10B);
114 for (i = 0, value = 0; i < link->num_lanes; i++) {
115 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
116 SOR_DP_TPG_SCRAMBLER_NONE |
117 SOR_DP_TPG_PATTERN_TRAIN1;
118 value = (value << 8) | lane;
121 tegra_sor_writel(sor, value, SOR_DP_TPG);
123 pattern = DP_TRAINING_PATTERN_1;
125 err = tegra_dpaux_train(sor->dpaux, link, pattern);
129 value = tegra_sor_readl(sor, SOR_DP_SPARE_0);
130 value |= SOR_DP_SPARE_SEQ_ENABLE;
131 value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
132 value |= SOR_DP_SPARE_MACRO_SOR_CLK;
133 tegra_sor_writel(sor, value, SOR_DP_SPARE_0);
135 for (i = 0, value = 0; i < link->num_lanes; i++) {
136 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
137 SOR_DP_TPG_SCRAMBLER_NONE |
138 SOR_DP_TPG_PATTERN_TRAIN2;
139 value = (value << 8) | lane;
142 tegra_sor_writel(sor, value, SOR_DP_TPG);
144 pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2;
146 err = tegra_dpaux_train(sor->dpaux, link, pattern);
150 for (i = 0, value = 0; i < link->num_lanes; i++) {
151 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
152 SOR_DP_TPG_SCRAMBLER_GALIOS |
153 SOR_DP_TPG_PATTERN_NONE;
154 value = (value << 8) | lane;
157 tegra_sor_writel(sor, value, SOR_DP_TPG);
159 pattern = DP_TRAINING_PATTERN_DISABLE;
161 err = tegra_dpaux_train(sor->dpaux, link, pattern);
168 static void tegra_sor_super_update(struct tegra_sor *sor)
170 tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0);
171 tegra_sor_writel(sor, 1, SOR_SUPER_STATE_0);
172 tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0);
175 static void tegra_sor_update(struct tegra_sor *sor)
177 tegra_sor_writel(sor, 0, SOR_STATE_0);
178 tegra_sor_writel(sor, 1, SOR_STATE_0);
179 tegra_sor_writel(sor, 0, SOR_STATE_0);
182 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
186 value = tegra_sor_readl(sor, SOR_PWM_DIV);
187 value &= ~SOR_PWM_DIV_MASK;
188 value |= 0x400; /* period */
189 tegra_sor_writel(sor, value, SOR_PWM_DIV);
191 value = tegra_sor_readl(sor, SOR_PWM_CTL);
192 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
193 value |= 0x400; /* duty cycle */
194 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
195 value |= SOR_PWM_CTL_TRIGGER;
196 tegra_sor_writel(sor, value, SOR_PWM_CTL);
198 timeout = jiffies + msecs_to_jiffies(timeout);
200 while (time_before(jiffies, timeout)) {
201 value = tegra_sor_readl(sor, SOR_PWM_CTL);
202 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
205 usleep_range(25, 100);
211 static int tegra_sor_attach(struct tegra_sor *sor)
213 unsigned long value, timeout;
215 /* wake up in normal mode */
216 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
217 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
218 value |= SOR_SUPER_STATE_MODE_NORMAL;
219 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
220 tegra_sor_super_update(sor);
223 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
224 value |= SOR_SUPER_STATE_ATTACHED;
225 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
226 tegra_sor_super_update(sor);
228 timeout = jiffies + msecs_to_jiffies(250);
230 while (time_before(jiffies, timeout)) {
231 value = tegra_sor_readl(sor, SOR_TEST);
232 if ((value & SOR_TEST_ATTACHED) != 0)
235 usleep_range(25, 100);
241 static int tegra_sor_wakeup(struct tegra_sor *sor)
243 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
244 unsigned long value, timeout;
246 /* enable display controller outputs */
247 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
248 value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
249 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
250 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
252 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
253 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
255 timeout = jiffies + msecs_to_jiffies(250);
257 /* wait for head to wake up */
258 while (time_before(jiffies, timeout)) {
259 value = tegra_sor_readl(sor, SOR_TEST);
260 value &= SOR_TEST_HEAD_MODE_MASK;
262 if (value == SOR_TEST_HEAD_MODE_AWAKE)
265 usleep_range(25, 100);
271 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
275 value = tegra_sor_readl(sor, SOR_PWR);
276 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
277 tegra_sor_writel(sor, value, SOR_PWR);
279 timeout = jiffies + msecs_to_jiffies(timeout);
281 while (time_before(jiffies, timeout)) {
282 value = tegra_sor_readl(sor, SOR_PWR);
283 if ((value & SOR_PWR_TRIGGER) == 0)
286 usleep_range(25, 100);
292 static int tegra_output_sor_enable(struct tegra_output *output)
294 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
295 struct drm_display_mode *mode = &dc->base.mode;
296 unsigned int vbe, vse, hbe, hse, vbs, hbs, i;
297 struct tegra_sor *sor = to_sor(output);
304 err = clk_prepare_enable(sor->clk);
308 reset_control_deassert(sor->rst);
311 err = tegra_dpaux_enable(sor->dpaux);
313 dev_err(sor->dev, "failed to enable DP: %d\n", err);
316 err = clk_set_parent(sor->clk, sor->clk_safe);
318 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
320 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
321 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
322 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
323 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
325 value = tegra_sor_readl(sor, SOR_PLL_2);
326 value &= ~SOR_PLL_2_BANDGAP_POWERDOWN;
327 tegra_sor_writel(sor, value, SOR_PLL_2);
328 usleep_range(20, 100);
330 value = tegra_sor_readl(sor, SOR_PLL_3);
331 value |= SOR_PLL_3_PLL_VDD_MODE_V3_3;
332 tegra_sor_writel(sor, value, SOR_PLL_3);
334 value = SOR_PLL_0_ICHPMP(0xf) | SOR_PLL_0_VCOCAP_RST |
335 SOR_PLL_0_PLLREG_LEVEL_V45 | SOR_PLL_0_RESISTOR_EXT;
336 tegra_sor_writel(sor, value, SOR_PLL_0);
338 value = tegra_sor_readl(sor, SOR_PLL_2);
339 value |= SOR_PLL_2_SEQ_PLLCAPPD;
340 value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE;
341 value |= SOR_PLL_2_LVDS_ENABLE;
342 tegra_sor_writel(sor, value, SOR_PLL_2);
344 value = SOR_PLL_1_TERM_COMPOUT | SOR_PLL_1_TMDS_TERM;
345 tegra_sor_writel(sor, value, SOR_PLL_1);
348 value = tegra_sor_readl(sor, SOR_PLL_2);
349 if ((value & SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE) == 0)
352 usleep_range(250, 1000);
355 value = tegra_sor_readl(sor, SOR_PLL_2);
356 value &= ~SOR_PLL_2_POWERDOWN_OVERRIDE;
357 value &= ~SOR_PLL_2_PORT_POWERDOWN;
358 tegra_sor_writel(sor, value, SOR_PLL_2);
364 /* set safe link bandwidth (1.62 Gbps) */
365 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
366 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
367 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62;
368 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
371 value = tegra_sor_readl(sor, SOR_PLL_2);
372 value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL_2_PORT_POWERDOWN |
373 SOR_PLL_2_BANDGAP_POWERDOWN;
374 tegra_sor_writel(sor, value, SOR_PLL_2);
376 value = tegra_sor_readl(sor, SOR_PLL_0);
377 value |= SOR_PLL_0_VCOPD | SOR_PLL_0_POWER_OFF;
378 tegra_sor_writel(sor, value, SOR_PLL_0);
380 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
381 value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
382 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
385 err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS);
387 dev_err(sor->dev, "failed to power on I/O rail: %d\n", err);
391 usleep_range(5, 100);
394 value = tegra_sor_readl(sor, SOR_PLL_2);
395 value &= ~SOR_PLL_2_BANDGAP_POWERDOWN;
396 tegra_sor_writel(sor, value, SOR_PLL_2);
398 usleep_range(20, 100);
401 value = tegra_sor_readl(sor, SOR_PLL_0);
402 value &= ~SOR_PLL_0_POWER_OFF;
403 value &= ~SOR_PLL_0_VCOPD;
404 tegra_sor_writel(sor, value, SOR_PLL_0);
406 value = tegra_sor_readl(sor, SOR_PLL_2);
407 value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE;
408 tegra_sor_writel(sor, value, SOR_PLL_2);
410 usleep_range(200, 1000);
413 value = tegra_sor_readl(sor, SOR_PLL_2);
414 value &= ~SOR_PLL_2_PORT_POWERDOWN;
415 tegra_sor_writel(sor, value, SOR_PLL_2);
417 /* switch to DP clock */
418 err = clk_set_parent(sor->clk, sor->clk_dp);
420 dev_err(sor->dev, "failed to set DP parent clock: %d\n", err);
422 /* power dplanes (XXX parameterize based on link?) */
423 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
424 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
425 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2;
426 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
428 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0);
429 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
430 value |= SOR_DP_LINKCTL_LANE_COUNT(4);
431 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);
433 /* start lane sequencer */
434 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
435 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
436 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
439 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
440 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
443 usleep_range(250, 1000);
446 /* set link bandwidth (2.7 GHz, XXX: parameterize based on link?) */
447 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
448 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
449 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70;
450 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
453 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0);
454 value |= SOR_DP_LINKCTL_ENABLE;
456 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
457 value |= SOR_DP_LINKCTL_TU_SIZE(59); /* XXX: don't hardcode? */
459 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
460 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);
462 for (i = 0, value = 0; i < 4; i++) {
463 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
464 SOR_DP_TPG_SCRAMBLER_GALIOS |
465 SOR_DP_TPG_PATTERN_NONE;
466 value = (value << 8) | lane;
469 tegra_sor_writel(sor, value, SOR_DP_TPG);
471 value = tegra_sor_readl(sor, SOR_DP_CONFIG_0);
472 value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
473 value |= SOR_DP_CONFIG_WATERMARK(14); /* XXX: don't hardcode? */
475 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
476 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(47); /* XXX: don't hardcode? */
478 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
479 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(9); /* XXX: don't hardcode? */
481 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; /* XXX: don't hardcode? */
483 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
484 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; /* XXX: don't hardcode? */
485 tegra_sor_writel(sor, value, SOR_DP_CONFIG_0);
487 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
488 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
489 value |= 137; /* XXX: don't hardcode? */
490 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
492 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
493 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
494 value |= 2368; /* XXX: don't hardcode? */
495 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
497 /* enable pad calibration logic */
498 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
499 value |= SOR_DP_PADCTL_PAD_CAL_PD;
500 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
503 /* FIXME: properly convert to struct drm_dp_aux */
504 struct drm_dp_aux *aux = (struct drm_dp_aux *)sor->dpaux;
505 struct drm_dp_link link;
508 err = drm_dp_link_probe(aux, &link);
510 dev_err(sor->dev, "failed to probe eDP link: %d\n",
515 err = drm_dp_link_power_up(aux, &link);
517 dev_err(sor->dev, "failed to power up eDP link: %d\n",
522 err = drm_dp_link_configure(aux, &link);
524 dev_err(sor->dev, "failed to configure eDP link: %d\n",
529 rate = drm_dp_link_rate_to_bw_code(link.rate);
530 lanes = link.num_lanes;
532 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
533 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
534 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
535 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
537 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0);
538 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
539 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
541 if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
542 value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
544 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);
546 /* disable training pattern generator */
548 for (i = 0; i < link.num_lanes; i++) {
549 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
550 SOR_DP_TPG_SCRAMBLER_GALIOS |
551 SOR_DP_TPG_PATTERN_NONE;
552 value = (value << 8) | lane;
555 tegra_sor_writel(sor, value, SOR_DP_TPG);
557 err = tegra_sor_dp_train_fast(sor, &link);
559 dev_err(sor->dev, "DP fast link training failed: %d\n",
564 dev_dbg(sor->dev, "fast link training succeeded\n");
567 err = tegra_sor_power_up(sor, 250);
569 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
573 /* start display controller in continuous mode */
574 value = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
576 tegra_dc_writel(dc, value, DC_CMD_STATE_ACCESS);
578 tegra_dc_writel(dc, VSYNC_H_POSITION(1), DC_DISP_DISP_TIMING_OPTIONS);
579 tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
581 value = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
583 tegra_dc_writel(dc, value, DC_CMD_STATE_ACCESS);
586 * configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete
587 * raster, associate with display controller)
589 value = SOR_STATE_ASY_PIXELDEPTH_BPP_24_444 |
590 SOR_STATE_ASY_VSYNCPOL |
591 SOR_STATE_ASY_HSYNCPOL |
592 SOR_STATE_ASY_PROTOCOL_DP_A |
593 SOR_STATE_ASY_CRC_MODE_COMPLETE |
594 SOR_STATE_ASY_OWNER(dc->pipe + 1);
595 tegra_sor_writel(sor, value, SOR_STATE_1);
598 * TODO: The video timing programming below doesn't seem to match the
599 * register definitions.
602 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
603 tegra_sor_writel(sor, value, SOR_HEAD_STATE_1(0));
605 vse = mode->vsync_end - mode->vsync_start - 1;
606 hse = mode->hsync_end - mode->hsync_start - 1;
608 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
609 tegra_sor_writel(sor, value, SOR_HEAD_STATE_2(0));
611 vbe = vse + (mode->vsync_start - mode->vdisplay);
612 hbe = hse + (mode->hsync_start - mode->hdisplay);
614 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
615 tegra_sor_writel(sor, value, SOR_HEAD_STATE_3(0));
617 vbs = vbe + mode->vdisplay;
618 hbs = hbe + mode->hdisplay;
620 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
621 tegra_sor_writel(sor, value, SOR_HEAD_STATE_4(0));
623 /* XXX interlaced mode */
624 tegra_sor_writel(sor, 0x00000001, SOR_HEAD_STATE_5(0));
626 /* CSTM (LVDS, link A/B, upper) */
627 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_B | SOR_CSTM_LINK_ACT_B |
629 tegra_sor_writel(sor, value, SOR_CSTM);
632 err = tegra_sor_setup_pwm(sor, 250);
634 dev_err(sor->dev, "failed to setup PWM: %d\n", err);
638 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
640 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
642 tegra_sor_update(sor);
644 err = tegra_sor_attach(sor);
646 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
650 err = tegra_sor_wakeup(sor);
652 dev_err(sor->dev, "failed to enable DC: %d\n", err);
661 static int tegra_sor_detach(struct tegra_sor *sor)
663 unsigned long value, timeout;
665 /* switch to safe mode */
666 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
667 value &= ~SOR_SUPER_STATE_MODE_NORMAL;
668 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
669 tegra_sor_super_update(sor);
671 timeout = jiffies + msecs_to_jiffies(250);
673 while (time_before(jiffies, timeout)) {
674 value = tegra_sor_readl(sor, SOR_PWR);
675 if (value & SOR_PWR_MODE_SAFE)
679 if ((value & SOR_PWR_MODE_SAFE) == 0)
683 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
684 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
685 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
686 tegra_sor_super_update(sor);
689 value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
690 value &= ~SOR_SUPER_STATE_ATTACHED;
691 tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
692 tegra_sor_super_update(sor);
694 timeout = jiffies + msecs_to_jiffies(250);
696 while (time_before(jiffies, timeout)) {
697 value = tegra_sor_readl(sor, SOR_TEST);
698 if ((value & SOR_TEST_ATTACHED) == 0)
701 usleep_range(25, 100);
704 if ((value & SOR_TEST_ATTACHED) != 0)
710 static int tegra_sor_power_down(struct tegra_sor *sor)
712 unsigned long value, timeout;
715 value = tegra_sor_readl(sor, SOR_PWR);
716 value &= ~SOR_PWR_NORMAL_STATE_PU;
717 value |= SOR_PWR_TRIGGER;
718 tegra_sor_writel(sor, value, SOR_PWR);
720 timeout = jiffies + msecs_to_jiffies(250);
722 while (time_before(jiffies, timeout)) {
723 value = tegra_sor_readl(sor, SOR_PWR);
724 if ((value & SOR_PWR_TRIGGER) == 0)
727 usleep_range(25, 100);
730 if ((value & SOR_PWR_TRIGGER) != 0)
733 err = clk_set_parent(sor->clk, sor->clk_safe);
735 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
737 value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
738 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
739 SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
740 tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
742 /* stop lane sequencer */
743 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
744 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
745 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
747 timeout = jiffies + msecs_to_jiffies(250);
749 while (time_before(jiffies, timeout)) {
750 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
751 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
754 usleep_range(25, 100);
757 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
760 value = tegra_sor_readl(sor, SOR_PLL_2);
761 value |= SOR_PLL_2_PORT_POWERDOWN;
762 tegra_sor_writel(sor, value, SOR_PLL_2);
764 usleep_range(20, 100);
766 value = tegra_sor_readl(sor, SOR_PLL_0);
767 value |= SOR_PLL_0_POWER_OFF;
768 value |= SOR_PLL_0_VCOPD;
769 tegra_sor_writel(sor, value, SOR_PLL_0);
771 value = tegra_sor_readl(sor, SOR_PLL_2);
772 value |= SOR_PLL_2_SEQ_PLLCAPPD;
773 value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE;
774 tegra_sor_writel(sor, value, SOR_PLL_2);
776 usleep_range(20, 100);
781 static int tegra_output_sor_disable(struct tegra_output *output)
783 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
784 struct tegra_sor *sor = to_sor(output);
791 err = tegra_sor_detach(sor);
793 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
797 tegra_sor_writel(sor, 0, SOR_STATE_1);
798 tegra_sor_update(sor);
801 * The following accesses registers of the display controller, so make
802 * sure it's only executed when the output is attached to one.
806 * XXX: We can't do this here because it causes the SOR to go
807 * into an erroneous state and the output will look scrambled
808 * the next time it is enabled. Presumably this is because we
809 * should be doing this only on the next VBLANK. A possible
810 * solution would be to queue a "power-off" event to trigger
811 * this code to be run during the next VBLANK.
814 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
815 value &= ~(PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
816 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE);
817 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
820 value = tegra_dc_readl(dc, DC_CMD_DISPLAY_COMMAND);
821 value &= ~DISP_CTRL_MODE_MASK;
822 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
824 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
825 value &= ~SOR_ENABLE;
826 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
828 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
829 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
832 err = tegra_sor_power_down(sor);
834 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
839 err = tegra_dpaux_disable(sor->dpaux);
841 dev_err(sor->dev, "failed to disable DP: %d\n", err);
846 err = tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS);
848 dev_err(sor->dev, "failed to power off I/O rail: %d\n", err);
852 reset_control_assert(sor->rst);
853 clk_disable_unprepare(sor->clk);
855 sor->enabled = false;
860 static int tegra_output_sor_setup_clock(struct tegra_output *output,
861 struct clk *clk, unsigned long pclk)
863 struct tegra_sor *sor = to_sor(output);
866 /* round to next MHz */
867 pclk = DIV_ROUND_UP(pclk / 2, 1000000) * 1000000;
869 err = clk_set_parent(clk, sor->clk_parent);
871 dev_err(sor->dev, "failed to set parent clock: %d\n", err);
875 err = clk_set_rate(sor->clk_parent, pclk);
877 dev_err(sor->dev, "failed to set base clock rate to %lu Hz\n",
885 static int tegra_output_sor_check_mode(struct tegra_output *output,
886 struct drm_display_mode *mode,
887 enum drm_mode_status *status)
890 * FIXME: For now, always assume that the mode is okay.
898 static enum drm_connector_status
899 tegra_output_sor_detect(struct tegra_output *output)
901 struct tegra_sor *sor = to_sor(output);
904 return tegra_dpaux_detect(sor->dpaux);
906 return connector_status_unknown;
909 static const struct tegra_output_ops sor_ops = {
910 .enable = tegra_output_sor_enable,
911 .disable = tegra_output_sor_disable,
912 .setup_clock = tegra_output_sor_setup_clock,
913 .check_mode = tegra_output_sor_check_mode,
914 .detect = tegra_output_sor_detect,
917 static int tegra_sor_init(struct host1x_client *client)
919 struct tegra_drm *tegra = dev_get_drvdata(client->parent);
920 struct tegra_sor *sor = host1x_client_to_sor(client);
926 sor->output.type = TEGRA_OUTPUT_EDP;
928 sor->output.dev = sor->dev;
929 sor->output.ops = &sor_ops;
931 err = tegra_output_init(tegra->drm, &sor->output);
933 dev_err(sor->dev, "output setup failed: %d\n", err);
938 err = tegra_dpaux_attach(sor->dpaux, &sor->output);
940 dev_err(sor->dev, "failed to attach DP: %d\n", err);
948 static int tegra_sor_exit(struct host1x_client *client)
950 struct tegra_sor *sor = host1x_client_to_sor(client);
953 err = tegra_output_disable(&sor->output);
955 dev_err(sor->dev, "output failed to disable: %d\n", err);
960 err = tegra_dpaux_detach(sor->dpaux);
962 dev_err(sor->dev, "failed to detach DP: %d\n", err);
967 err = tegra_output_exit(&sor->output);
969 dev_err(sor->dev, "output cleanup failed: %d\n", err);
976 static const struct host1x_client_ops sor_client_ops = {
977 .init = tegra_sor_init,
978 .exit = tegra_sor_exit,
981 static int tegra_sor_probe(struct platform_device *pdev)
983 struct device_node *np;
984 struct tegra_sor *sor;
985 struct resource *regs;
988 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
992 sor->output.dev = sor->dev = &pdev->dev;
994 np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
996 sor->dpaux = tegra_dpaux_find_by_of_node(np);
1000 return -EPROBE_DEFER;
1003 err = tegra_output_probe(&sor->output);
1007 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1008 sor->regs = devm_ioremap_resource(&pdev->dev, regs);
1009 if (IS_ERR(sor->regs))
1010 return PTR_ERR(sor->regs);
1012 sor->rst = devm_reset_control_get(&pdev->dev, "sor");
1013 if (IS_ERR(sor->rst))
1014 return PTR_ERR(sor->rst);
1016 sor->clk = devm_clk_get(&pdev->dev, NULL);
1017 if (IS_ERR(sor->clk))
1018 return PTR_ERR(sor->clk);
1020 sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
1021 if (IS_ERR(sor->clk_parent))
1022 return PTR_ERR(sor->clk_parent);
1024 err = clk_prepare_enable(sor->clk_parent);
1028 sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
1029 if (IS_ERR(sor->clk_safe))
1030 return PTR_ERR(sor->clk_safe);
1032 err = clk_prepare_enable(sor->clk_safe);
1036 sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
1037 if (IS_ERR(sor->clk_dp))
1038 return PTR_ERR(sor->clk_dp);
1040 err = clk_prepare_enable(sor->clk_dp);
1044 INIT_LIST_HEAD(&sor->client.list);
1045 sor->client.ops = &sor_client_ops;
1046 sor->client.dev = &pdev->dev;
1048 err = host1x_client_register(&sor->client);
1050 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1055 platform_set_drvdata(pdev, sor);
1060 static int tegra_sor_remove(struct platform_device *pdev)
1062 struct tegra_sor *sor = platform_get_drvdata(pdev);
1065 err = host1x_client_unregister(&sor->client);
1067 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1072 clk_disable_unprepare(sor->clk_parent);
1073 clk_disable_unprepare(sor->clk_safe);
1074 clk_disable_unprepare(sor->clk_dp);
1075 clk_disable_unprepare(sor->clk);
1080 static const struct of_device_id tegra_sor_of_match[] = {
1081 { .compatible = "nvidia,tegra124-sor", },
1085 struct platform_driver tegra_sor_driver = {
1087 .name = "tegra-sor",
1088 .of_match_table = tegra_sor_of_match,
1090 .probe = tegra_sor_probe,
1091 .remove = tegra_sor_remove,