drivers/gpu/drm/tegra/sor.c

   1 /*
   2  * Copyright (C) 2013 NVIDIA Corporation
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License version 2 as
   6  * published by the Free Software Foundation.
   7  */
   8
   9 #include <linux/clk.h>
  10 #include <linux/debugfs.h>
  11 #include <linux/gpio.h>
  12 #include <linux/io.h>
  13 #include <linux/platform_device.h>
  14 #include <linux/reset.h>
  15
  16 #include <soc/tegra/pmc.h>
  17
  18 #include <drm/drm_dp_helper.h>
  19 #include <drm/drm_panel.h>
  20
  21 #include "dc.h"
  22 #include "drm.h"
  23 #include "sor.h"
  24
  25 struct tegra_sor {
  26         struct host1x_client client;
  27         struct tegra_output output;
  28         struct device *dev;
  29
  30         void __iomem *regs;
  31
  32         struct reset_control *rst;
  33         struct clk *clk_parent;
  34         struct clk *clk_safe;
  35         struct clk *clk_dp;
  36         struct clk *clk;
  37
  38         struct tegra_dpaux *dpaux;
  39
  40         struct mutex lock;
  41         bool enabled;
  42
  43         struct dentry *debugfs;
  44 };
  45
  46 struct tegra_sor_config {
  47         u32 bits_per_pixel;
  48
  49         u32 active_polarity;
  50         u32 active_count;
  51         u32 tu_size;
  52         u32 active_frac;
  53         u32 watermark;
  54
  55         u32 hblank_symbols;
  56         u32 vblank_symbols;
  57 };
  58
  59 static inline struct tegra_sor *
  60 host1x_client_to_sor(struct host1x_client *client)
  61 {
  62         return container_of(client, struct tegra_sor, client);
  63 }
  64
  65 static inline struct tegra_sor *to_sor(struct tegra_output *output)
  66 {
  67         return container_of(output, struct tegra_sor, output);
  68 }
  69
  70 static inline unsigned long tegra_sor_readl(struct tegra_sor *sor,
  71                                             unsigned long offset)
  72 {
  73         return readl(sor->regs + (offset << 2));
  74 }
  75
  76 static inline void tegra_sor_writel(struct tegra_sor *sor, unsigned long value,
  77                                     unsigned long offset)
  78 {
  79         writel(value, sor->regs + (offset << 2));
  80 }
  81
  82 static int tegra_sor_dp_train_fast(struct tegra_sor *sor,
  83                                    struct drm_dp_link *link)
  84 {
  85         unsigned long value;
  86         unsigned int i;
  87         u8 pattern;
  88         int err;
  89
  90         /* setup lane parameters */
  91         value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) |
  92                 SOR_LANE_DRIVE_CURRENT_LANE2(0x40) |
  93                 SOR_LANE_DRIVE_CURRENT_LANE1(0x40) |
  94                 SOR_LANE_DRIVE_CURRENT_LANE0(0x40);
  95         tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT_0);
  96
  97         value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) |
  98                 SOR_LANE_PREEMPHASIS_LANE2(0x0f) |
  99                 SOR_LANE_PREEMPHASIS_LANE1(0x0f) |
 100                 SOR_LANE_PREEMPHASIS_LANE0(0x0f);
 101         tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS_0);
 102
 103         value = SOR_LANE_POST_CURSOR_LANE3(0x00) |
 104                 SOR_LANE_POST_CURSOR_LANE2(0x00) |
 105                 SOR_LANE_POST_CURSOR_LANE1(0x00) |
 106                 SOR_LANE_POST_CURSOR_LANE0(0x00);
 107         tegra_sor_writel(sor, value, SOR_LANE_POST_CURSOR_0);
 108
 109         /* disable LVDS mode */
 110         tegra_sor_writel(sor, 0, SOR_LVDS);
 111
 112         value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
 113         value |= SOR_DP_PADCTL_TX_PU_ENABLE;
 114         value &= ~SOR_DP_PADCTL_TX_PU_MASK;
 115         value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */
 116         tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
 117
 118         value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
 119         value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
 120                  SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0;
 121         tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
 122
 123         usleep_range(10, 100);
 124
 125         value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
 126         value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 |
 127                    SOR_DP_PADCTL_CM_TXD_1 | SOR_DP_PADCTL_CM_TXD_0);
 128         tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
 129
 130         err = tegra_dpaux_prepare(sor->dpaux, DP_SET_ANSI_8B10B);
 131         if (err < 0)
 132                 return err;
 133
 134         for (i = 0, value = 0; i < link->num_lanes; i++) {
 135                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 136                                      SOR_DP_TPG_SCRAMBLER_NONE |
 137                                      SOR_DP_TPG_PATTERN_TRAIN1;
 138                 value = (value << 8) | lane;
 139         }
 140
 141         tegra_sor_writel(sor, value, SOR_DP_TPG);
 142
 143         pattern = DP_TRAINING_PATTERN_1;
 144
 145         err = tegra_dpaux_train(sor->dpaux, link, pattern);
 146         if (err < 0)
 147                 return err;
 148
 149         value = tegra_sor_readl(sor, SOR_DP_SPARE_0);
 150         value |= SOR_DP_SPARE_SEQ_ENABLE;
 151         value &= ~SOR_DP_SPARE_PANEL_INTERNAL;
 152         value |= SOR_DP_SPARE_MACRO_SOR_CLK;
 153         tegra_sor_writel(sor, value, SOR_DP_SPARE_0);
 154
 155         for (i = 0, value = 0; i < link->num_lanes; i++) {
 156                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 157                                      SOR_DP_TPG_SCRAMBLER_NONE |
 158                                      SOR_DP_TPG_PATTERN_TRAIN2;
 159                 value = (value << 8) | lane;
 160         }
 161
 162         tegra_sor_writel(sor, value, SOR_DP_TPG);
 163
 164         pattern = DP_LINK_SCRAMBLING_DISABLE | DP_TRAINING_PATTERN_2;
 165
 166         err = tegra_dpaux_train(sor->dpaux, link, pattern);
 167         if (err < 0)
 168                 return err;
 169
 170         for (i = 0, value = 0; i < link->num_lanes; i++) {
 171                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
 172                                      SOR_DP_TPG_SCRAMBLER_GALIOS |
 173                                      SOR_DP_TPG_PATTERN_NONE;
 174                 value = (value << 8) | lane;
 175         }
 176
 177         tegra_sor_writel(sor, value, SOR_DP_TPG);
 178
 179         pattern = DP_TRAINING_PATTERN_DISABLE;
 180
 181         err = tegra_dpaux_train(sor->dpaux, link, pattern);
 182         if (err < 0)
 183                 return err;
 184
 185         return 0;
 186 }
 187
 188 static void tegra_sor_super_update(struct tegra_sor *sor)
 189 {
 190         tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0);
 191         tegra_sor_writel(sor, 1, SOR_SUPER_STATE_0);
 192         tegra_sor_writel(sor, 0, SOR_SUPER_STATE_0);
 193 }
 194
 195 static void tegra_sor_update(struct tegra_sor *sor)
 196 {
 197         tegra_sor_writel(sor, 0, SOR_STATE_0);
 198         tegra_sor_writel(sor, 1, SOR_STATE_0);
 199         tegra_sor_writel(sor, 0, SOR_STATE_0);
 200 }
 201
 202 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout)
 203 {
 204         unsigned long value;
 205
 206         value = tegra_sor_readl(sor, SOR_PWM_DIV);
 207         value &= ~SOR_PWM_DIV_MASK;
 208         value |= 0x400; /* period */
 209         tegra_sor_writel(sor, value, SOR_PWM_DIV);
 210
 211         value = tegra_sor_readl(sor, SOR_PWM_CTL);
 212         value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK;
 213         value |= 0x400; /* duty cycle */
 214         value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */
 215         value |= SOR_PWM_CTL_TRIGGER;
 216         tegra_sor_writel(sor, value, SOR_PWM_CTL);
 217
 218         timeout = jiffies + msecs_to_jiffies(timeout);
 219
 220         while (time_before(jiffies, timeout)) {
 221                 value = tegra_sor_readl(sor, SOR_PWM_CTL);
 222                 if ((value & SOR_PWM_CTL_TRIGGER) == 0)
 223                         return 0;
 224
 225                 usleep_range(25, 100);
 226         }
 227
 228         return -ETIMEDOUT;
 229 }
 230
 231 static int tegra_sor_attach(struct tegra_sor *sor)
 232 {
 233         unsigned long value, timeout;
 234
 235         /* wake up in normal mode */
 236         value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
 237         value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE;
 238         value |= SOR_SUPER_STATE_MODE_NORMAL;
 239         tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
 240         tegra_sor_super_update(sor);
 241
 242         /* attach */
 243         value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
 244         value |= SOR_SUPER_STATE_ATTACHED;
 245         tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
 246         tegra_sor_super_update(sor);
 247
 248         timeout = jiffies + msecs_to_jiffies(250);
 249
 250         while (time_before(jiffies, timeout)) {
 251                 value = tegra_sor_readl(sor, SOR_TEST);
 252                 if ((value & SOR_TEST_ATTACHED) != 0)
 253                         return 0;
 254
 255                 usleep_range(25, 100);
 256         }
 257
 258         return -ETIMEDOUT;
 259 }
 260
 261 static int tegra_sor_wakeup(struct tegra_sor *sor)
 262 {
 263         struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc);
 264         unsigned long value, timeout;
 265
 266         /* enable display controller outputs */
 267         value = tegra_dc_readl(dc, DC_CMD_DISPLAY_POWER_CONTROL);
 268         value |= PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
 269                  PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
 270         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
 271
 272         tegra_dc_commit(dc);
 273
 274         timeout = jiffies + msecs_to_jiffies(250);
 275
 276         /* wait for head to wake up */
 277         while (time_before(jiffies, timeout)) {
 278                 value = tegra_sor_readl(sor, SOR_TEST);
 279                 value &= SOR_TEST_HEAD_MODE_MASK;
 280
 281                 if (value == SOR_TEST_HEAD_MODE_AWAKE)
 282                         return 0;
 283
 284                 usleep_range(25, 100);
 285         }
 286
 287         return -ETIMEDOUT;
 288 }
 289
 290 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout)
 291 {
 292         unsigned long value;
 293
 294         value = tegra_sor_readl(sor, SOR_PWR);
 295         value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU;
 296         tegra_sor_writel(sor, value, SOR_PWR);
 297
 298         timeout = jiffies + msecs_to_jiffies(timeout);
 299
 300         while (time_before(jiffies, timeout)) {
 301                 value = tegra_sor_readl(sor, SOR_PWR);
 302                 if ((value & SOR_PWR_TRIGGER) == 0)
 303                         return 0;
 304
 305                 usleep_range(25, 100);
 306         }
 307
 308         return -ETIMEDOUT;
 309 }
 310
 311 struct tegra_sor_params {
 312         /* number of link clocks per line */
 313         unsigned int num_clocks;
 314         /* ratio between input and output */
 315         u64 ratio;
 316         /* precision factor */
 317         u64 precision;
 318
 319         unsigned int active_polarity;
 320         unsigned int active_count;
 321         unsigned int active_frac;
 322         unsigned int tu_size;
 323         unsigned int error;
 324 };
 325
 326 static int tegra_sor_compute_params(struct tegra_sor *sor,
 327                                     struct tegra_sor_params *params,
 328                                     unsigned int tu_size)
 329 {
 330         u64 active_sym, active_count, frac, approx;
 331         u32 active_polarity, active_frac = 0;
 332         const u64 f = params->precision;
 333         s64 error;
 334
 335         active_sym = params->ratio * tu_size;
 336         active_count = div_u64(active_sym, f) * f;
 337         frac = active_sym - active_count;
 338
 339         /* fraction < 0.5 */
 340         if (frac >= (f / 2)) {
 341                 active_polarity = 1;
 342                 frac = f - frac;
 343         } else {
 344                 active_polarity = 0;
 345         }
 346
 347         if (frac != 0) {
 348                 frac = div_u64(f * f,  frac); /* 1/fraction */
 349                 if (frac <= (15 * f)) {
 350                         active_frac = div_u64(frac, f);
 351
 352                         /* round up */
 353                         if (active_polarity)
 354                                 active_frac++;
 355                 } else {
 356                         active_frac = active_polarity ? 1 : 15;
 357                 }
 358         }
 359
 360         if (active_frac == 1)
 361                 active_polarity = 0;
 362
 363         if (active_polarity == 1) {
 364                 if (active_frac) {
 365                         approx = active_count + (active_frac * (f - 1)) * f;
 366                         approx = div_u64(approx, active_frac * f);
 367                 } else {
 368                         approx = active_count + f;
 369                 }
 370         } else {
 371                 if (active_frac)
 372                         approx = active_count + div_u64(f, active_frac);
 373                 else
 374                         approx = active_count;
 375         }
 376
 377         error = div_s64(active_sym - approx, tu_size);
 378         error *= params->num_clocks;
 379
 380         if (error <= 0 && abs64(error) < params->error) {
 381                 params->active_count = div_u64(active_count, f);
 382                 params->active_polarity = active_polarity;
 383                 params->active_frac = active_frac;
 384                 params->error = abs64(error);
 385                 params->tu_size = tu_size;
 386
 387                 if (error == 0)
 388                         return true;
 389         }
 390
 391         return false;
 392 }
 393
 394 static int tegra_sor_calc_config(struct tegra_sor *sor,
 395                                  struct drm_display_mode *mode,
 396                                  struct tegra_sor_config *config,
 397                                  struct drm_dp_link *link)
 398 {
 399         const u64 f = 100000, link_rate = link->rate * 1000;
 400         const u64 pclk = mode->clock * 1000;
 401         u64 input, output, watermark, num;
 402         struct tegra_sor_params params;
 403         u32 num_syms_per_line;
 404         unsigned int i;
 405
 406         if (!link_rate || !link->num_lanes || !pclk || !config->bits_per_pixel)
 407                 return -EINVAL;
 408
 409         output = link_rate * 8 * link->num_lanes;
 410         input = pclk * config->bits_per_pixel;
 411
 412         if (input >= output)
 413                 return -ERANGE;
 414
 415         memset(&params, 0, sizeof(params));
 416         params.ratio = div64_u64(input * f, output);
 417         params.num_clocks = div_u64(link_rate * mode->hdisplay, pclk);
 418         params.precision = f;
 419         params.error = 64 * f;
 420         params.tu_size = 64;
 421
 422         for (i = params.tu_size; i >= 32; i--)
 423                 if (tegra_sor_compute_params(sor, &params, i))
 424                         break;
 425
 426         if (params.active_frac == 0) {
 427                 config->active_polarity = 0;
 428                 config->active_count = params.active_count;
 429
 430                 if (!params.active_polarity)
 431                         config->active_count--;
 432
 433                 config->tu_size = params.tu_size;
 434                 config->active_frac = 1;
 435         } else {
 436                 config->active_polarity = params.active_polarity;
 437                 config->active_count = params.active_count;
 438                 config->active_frac = params.active_frac;
 439                 config->tu_size = params.tu_size;
 440         }
 441
 442         dev_dbg(sor->dev,
 443                 "polarity: %d active count: %d tu size: %d active frac: %d\n",
 444                 config->active_polarity, config->active_count,
 445                 config->tu_size, config->active_frac);
 446
 447         watermark = params.ratio * config->tu_size * (f - params.ratio);
 448         watermark = div_u64(watermark, f);
 449
 450         watermark = div_u64(watermark + params.error, f);
 451         config->watermark = watermark + (config->bits_per_pixel / 8) + 2;
 452         num_syms_per_line = (mode->hdisplay * config->bits_per_pixel) *
 453                             (link->num_lanes * 8);
 454
 455         if (config->watermark > 30) {
 456                 config->watermark = 30;
 457                 dev_err(sor->dev,
 458                         "unable to compute TU size, forcing watermark to %u\n",
 459                         config->watermark);
 460         } else if (config->watermark > num_syms_per_line) {
 461                 config->watermark = num_syms_per_line;
 462                 dev_err(sor->dev, "watermark too high, forcing to %u\n",
 463                         config->watermark);
 464         }
 465
 466         /* compute the number of symbols per horizontal blanking interval */
 467         num = ((mode->htotal - mode->hdisplay) - 7) * link_rate;
 468         config->hblank_symbols = div_u64(num, pclk);
 469
 470         if (link->capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
 471                 config->hblank_symbols -= 3;
 472
 473         config->hblank_symbols -= 12 / link->num_lanes;
 474
 475         /* compute the number of symbols per vertical blanking interval */
 476         num = (mode->hdisplay - 25) * link_rate;
 477         config->vblank_symbols = div_u64(num, pclk);
 478         config->vblank_symbols -= 36 / link->num_lanes + 4;
 479
 480         dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols,
 481                 config->vblank_symbols);
 482
 483         return 0;
 484 }
 485
 486 static int tegra_sor_detach(struct tegra_sor *sor)
 487 {
 488         unsigned long value, timeout;
 489
 490         /* switch to safe mode */
 491         value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
 492         value &= ~SOR_SUPER_STATE_MODE_NORMAL;
 493         tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
 494         tegra_sor_super_update(sor);
 495
 496         timeout = jiffies + msecs_to_jiffies(250);
 497
 498         while (time_before(jiffies, timeout)) {
 499                 value = tegra_sor_readl(sor, SOR_PWR);
 500                 if (value & SOR_PWR_MODE_SAFE)
 501                         break;
 502         }
 503
 504         if ((value & SOR_PWR_MODE_SAFE) == 0)
 505                 return -ETIMEDOUT;
 506
 507         /* go to sleep */
 508         value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
 509         value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK;
 510         tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
 511         tegra_sor_super_update(sor);
 512
 513         /* detach */
 514         value = tegra_sor_readl(sor, SOR_SUPER_STATE_1);
 515         value &= ~SOR_SUPER_STATE_ATTACHED;
 516         tegra_sor_writel(sor, value, SOR_SUPER_STATE_1);
 517         tegra_sor_super_update(sor);
 518
 519         timeout = jiffies + msecs_to_jiffies(250);
 520
 521         while (time_before(jiffies, timeout)) {
 522                 value = tegra_sor_readl(sor, SOR_TEST);
 523                 if ((value & SOR_TEST_ATTACHED) == 0)
 524                         break;
 525
 526                 usleep_range(25, 100);
 527         }
 528
 529         if ((value & SOR_TEST_ATTACHED) != 0)
 530                 return -ETIMEDOUT;
 531
 532         return 0;
 533 }
 534
 535 static int tegra_sor_power_down(struct tegra_sor *sor)
 536 {
 537         unsigned long value, timeout;
 538         int err;
 539
 540         value = tegra_sor_readl(sor, SOR_PWR);
 541         value &= ~SOR_PWR_NORMAL_STATE_PU;
 542         value |= SOR_PWR_TRIGGER;
 543         tegra_sor_writel(sor, value, SOR_PWR);
 544
 545         timeout = jiffies + msecs_to_jiffies(250);
 546
 547         while (time_before(jiffies, timeout)) {
 548                 value = tegra_sor_readl(sor, SOR_PWR);
 549                 if ((value & SOR_PWR_TRIGGER) == 0)
 550                         return 0;
 551
 552                 usleep_range(25, 100);
 553         }
 554
 555         if ((value & SOR_PWR_TRIGGER) != 0)
 556                 return -ETIMEDOUT;
 557
 558         err = clk_set_parent(sor->clk, sor->clk_safe);
 559         if (err < 0)
 560                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
 561
 562         value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
 563         value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 |
 564                    SOR_DP_PADCTL_PD_TXD_1 | SOR_DP_PADCTL_PD_TXD_2);
 565         tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
 566
 567         /* stop lane sequencer */
 568         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP |
 569                 SOR_LANE_SEQ_CTL_POWER_STATE_DOWN;
 570         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
 571
 572         timeout = jiffies + msecs_to_jiffies(250);
 573
 574         while (time_before(jiffies, timeout)) {
 575                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
 576                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
 577                         break;
 578
 579                 usleep_range(25, 100);
 580         }
 581
 582         if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0)
 583                 return -ETIMEDOUT;
 584
 585         value = tegra_sor_readl(sor, SOR_PLL_2);
 586         value |= SOR_PLL_2_PORT_POWERDOWN;
 587         tegra_sor_writel(sor, value, SOR_PLL_2);
 588
 589         usleep_range(20, 100);
 590
 591         value = tegra_sor_readl(sor, SOR_PLL_0);
 592         value |= SOR_PLL_0_POWER_OFF;
 593         value |= SOR_PLL_0_VCOPD;
 594         tegra_sor_writel(sor, value, SOR_PLL_0);
 595
 596         value = tegra_sor_readl(sor, SOR_PLL_2);
 597         value |= SOR_PLL_2_SEQ_PLLCAPPD;
 598         value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE;
 599         tegra_sor_writel(sor, value, SOR_PLL_2);
 600
 601         usleep_range(20, 100);
 602
 603         return 0;
 604 }
 605
 606 static int tegra_sor_crc_open(struct inode *inode, struct file *file)
 607 {
 608         file->private_data = inode->i_private;
 609
 610         return 0;
 611 }
 612
 613 static int tegra_sor_crc_release(struct inode *inode, struct file *file)
 614 {
 615         return 0;
 616 }
 617
 618 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout)
 619 {
 620         u32 value;
 621
 622         timeout = jiffies + msecs_to_jiffies(timeout);
 623
 624         while (time_before(jiffies, timeout)) {
 625                 value = tegra_sor_readl(sor, SOR_CRC_A);
 626                 if (value & SOR_CRC_A_VALID)
 627                         return 0;
 628
 629                 usleep_range(100, 200);
 630         }
 631
 632         return -ETIMEDOUT;
 633 }
 634
 635 static ssize_t tegra_sor_crc_read(struct file *file, char __user *buffer,
 636                                   size_t size, loff_t *ppos)
 637 {
 638         struct tegra_sor *sor = file->private_data;
 639         ssize_t num, err;
 640         char buf[10];
 641         u32 value;
 642
 643         mutex_lock(&sor->lock);
 644
 645         if (!sor->enabled) {
 646                 err = -EAGAIN;
 647                 goto unlock;
 648         }
 649
 650         value = tegra_sor_readl(sor, SOR_STATE_1);
 651         value &= ~SOR_STATE_ASY_CRC_MODE_MASK;
 652         tegra_sor_writel(sor, value, SOR_STATE_1);
 653
 654         value = tegra_sor_readl(sor, SOR_CRC_CNTRL);
 655         value |= SOR_CRC_CNTRL_ENABLE;
 656         tegra_sor_writel(sor, value, SOR_CRC_CNTRL);
 657
 658         value = tegra_sor_readl(sor, SOR_TEST);
 659         value &= ~SOR_TEST_CRC_POST_SERIALIZE;
 660         tegra_sor_writel(sor, value, SOR_TEST);
 661
 662         err = tegra_sor_crc_wait(sor, 100);
 663         if (err < 0)
 664                 goto unlock;
 665
 666         tegra_sor_writel(sor, SOR_CRC_A_RESET, SOR_CRC_A);
 667         value = tegra_sor_readl(sor, SOR_CRC_B);
 668
 669         num = scnprintf(buf, sizeof(buf), "%08x\n", value);
 670
 671         err = simple_read_from_buffer(buffer, size, ppos, buf, num);
 672
 673 unlock:
 674         mutex_unlock(&sor->lock);
 675         return err;
 676 }
 677
 678 static const struct file_operations tegra_sor_crc_fops = {
 679         .owner = THIS_MODULE,
 680         .open = tegra_sor_crc_open,
 681         .read = tegra_sor_crc_read,
 682         .release = tegra_sor_crc_release,
 683 };
 684
 685 static int tegra_sor_debugfs_init(struct tegra_sor *sor,
 686                                   struct drm_minor *minor)
 687 {
 688         struct dentry *entry;
 689         int err = 0;
 690
 691         sor->debugfs = debugfs_create_dir("sor", minor->debugfs_root);
 692         if (!sor->debugfs)
 693                 return -ENOMEM;
 694
 695         entry = debugfs_create_file("crc", 0644, sor->debugfs, sor,
 696                                     &tegra_sor_crc_fops);
 697         if (!entry) {
 698                 dev_err(sor->dev,
 699                         "cannot create /sys/kernel/debug/dri/%s/sor/crc\n",
 700                         minor->debugfs_root->d_name.name);
 701                 err = -ENOMEM;
 702                 goto remove;
 703         }
 704
 705         return err;
 706
 707 remove:
 708         debugfs_remove(sor->debugfs);
 709         sor->debugfs = NULL;
 710         return err;
 711 }
 712
 713 static void tegra_sor_debugfs_exit(struct tegra_sor *sor)
 714 {
 715         debugfs_remove_recursive(sor->debugfs);
 716         sor->debugfs = NULL;
 717 }
 718
 719 static void tegra_sor_connector_dpms(struct drm_connector *connector, int mode)
 720 {
 721 }
 722
 723 static enum drm_connector_status
 724 tegra_sor_connector_detect(struct drm_connector *connector, bool force)
 725 {
 726         struct tegra_output *output = connector_to_output(connector);
 727         struct tegra_sor *sor = to_sor(output);
 728
 729         if (sor->dpaux)
 730                 return tegra_dpaux_detect(sor->dpaux);
 731
 732         return connector_status_unknown;
 733 }
 734
 735 static const struct drm_connector_funcs tegra_sor_connector_funcs = {
 736         .dpms = tegra_sor_connector_dpms,
 737         .detect = tegra_sor_connector_detect,
 738         .fill_modes = drm_helper_probe_single_connector_modes,
 739         .destroy = tegra_output_connector_destroy,
 740 };
 741
 742 static int tegra_sor_connector_get_modes(struct drm_connector *connector)
 743 {
 744         struct tegra_output *output = connector_to_output(connector);
 745         struct tegra_sor *sor = to_sor(output);
 746         int err;
 747
 748         if (sor->dpaux)
 749                 tegra_dpaux_enable(sor->dpaux);
 750
 751         err = tegra_output_connector_get_modes(connector);
 752
 753         if (sor->dpaux)
 754                 tegra_dpaux_disable(sor->dpaux);
 755
 756         return err;
 757 }
 758
 759 static enum drm_mode_status
 760 tegra_sor_connector_mode_valid(struct drm_connector *connector,
 761                                struct drm_display_mode *mode)
 762 {
 763         return MODE_OK;
 764 }
 765
 766 static const struct drm_connector_helper_funcs tegra_sor_connector_helper_funcs = {
 767         .get_modes = tegra_sor_connector_get_modes,
 768         .mode_valid = tegra_sor_connector_mode_valid,
 769         .best_encoder = tegra_output_connector_best_encoder,
 770 };
 771
 772 static const struct drm_encoder_funcs tegra_sor_encoder_funcs = {
 773         .destroy = tegra_output_encoder_destroy,
 774 };
 775
 776 static void tegra_sor_encoder_dpms(struct drm_encoder *encoder, int mode)
 777 {
 778 }
 779
 780 static bool tegra_sor_encoder_mode_fixup(struct drm_encoder *encoder,
 781                                          const struct drm_display_mode *mode,
 782                                          struct drm_display_mode *adjusted)
 783 {
 784         struct tegra_output *output = encoder_to_output(encoder);
 785         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
 786         unsigned long pclk = mode->clock * 1000;
 787         struct tegra_sor *sor = to_sor(output);
 788         int err;
 789
 790         err = tegra_dc_setup_clock(dc, sor->clk_parent, pclk, 0);
 791         if (err < 0) {
 792                 dev_err(output->dev, "failed to setup DC clock: %d\n", err);
 793                 return false;
 794         }
 795
 796         err = clk_set_rate(sor->clk_parent, pclk);
 797         if (err < 0) {
 798                 dev_err(output->dev, "failed to set clock rate to %lu Hz\n",
 799                         pclk);
 800                 return false;
 801         }
 802
 803         return true;
 804 }
 805
 806 static void tegra_sor_encoder_prepare(struct drm_encoder *encoder)
 807 {
 808 }
 809
 810 static void tegra_sor_encoder_commit(struct drm_encoder *encoder)
 811 {
 812 }
 813
 814 static void tegra_sor_encoder_mode_set(struct drm_encoder *encoder,
 815                                        struct drm_display_mode *mode,
 816                                        struct drm_display_mode *adjusted)
 817 {
 818         struct tegra_output *output = encoder_to_output(encoder);
 819         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
 820         unsigned int vbe, vse, hbe, hse, vbs, hbs, i;
 821         struct tegra_sor *sor = to_sor(output);
 822         struct tegra_sor_config config;
 823         struct drm_dp_link link;
 824         struct drm_dp_aux *aux;
 825         unsigned long value;
 826         int err = 0;
 827
 828         mutex_lock(&sor->lock);
 829
 830         if (sor->enabled)
 831                 goto unlock;
 832
 833         err = clk_prepare_enable(sor->clk);
 834         if (err < 0)
 835                 goto unlock;
 836
 837         reset_control_deassert(sor->rst);
 838
 839         if (output->panel)
 840                 drm_panel_prepare(output->panel);
 841
 842         /* FIXME: properly convert to struct drm_dp_aux */
 843         aux = (struct drm_dp_aux *)sor->dpaux;
 844
 845         if (sor->dpaux) {
 846                 err = tegra_dpaux_enable(sor->dpaux);
 847                 if (err < 0)
 848                         dev_err(sor->dev, "failed to enable DP: %d\n", err);
 849
 850                 err = drm_dp_link_probe(aux, &link);
 851                 if (err < 0) {
 852                         dev_err(sor->dev, "failed to probe eDP link: %d\n",
 853                                 err);
 854                         goto unlock;
 855                 }
 856         }
 857
 858         err = clk_set_parent(sor->clk, sor->clk_safe);
 859         if (err < 0)
 860                 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err);
 861
 862         memset(&config, 0, sizeof(config));
 863         config.bits_per_pixel = output->connector.display_info.bpc * 3;
 864
 865         err = tegra_sor_calc_config(sor, mode, &config, &link);
 866         if (err < 0)
 867                 dev_err(sor->dev, "failed to compute link configuration: %d\n",
 868                         err);
 869
 870         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 871         value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK;
 872         value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK;
 873         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 874
 875         value = tegra_sor_readl(sor, SOR_PLL_2);
 876         value &= ~SOR_PLL_2_BANDGAP_POWERDOWN;
 877         tegra_sor_writel(sor, value, SOR_PLL_2);
 878         usleep_range(20, 100);
 879
 880         value = tegra_sor_readl(sor, SOR_PLL_3);
 881         value |= SOR_PLL_3_PLL_VDD_MODE_V3_3;
 882         tegra_sor_writel(sor, value, SOR_PLL_3);
 883
 884         value = SOR_PLL_0_ICHPMP(0xf) | SOR_PLL_0_VCOCAP_RST |
 885                 SOR_PLL_0_PLLREG_LEVEL_V45 | SOR_PLL_0_RESISTOR_EXT;
 886         tegra_sor_writel(sor, value, SOR_PLL_0);
 887
 888         value = tegra_sor_readl(sor, SOR_PLL_2);
 889         value |= SOR_PLL_2_SEQ_PLLCAPPD;
 890         value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE;
 891         value |= SOR_PLL_2_LVDS_ENABLE;
 892         tegra_sor_writel(sor, value, SOR_PLL_2);
 893
 894         value = SOR_PLL_1_TERM_COMPOUT | SOR_PLL_1_TMDS_TERM;
 895         tegra_sor_writel(sor, value, SOR_PLL_1);
 896
 897         while (true) {
 898                 value = tegra_sor_readl(sor, SOR_PLL_2);
 899                 if ((value & SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE) == 0)
 900                         break;
 901
 902                 usleep_range(250, 1000);
 903         }
 904
 905         value = tegra_sor_readl(sor, SOR_PLL_2);
 906         value &= ~SOR_PLL_2_POWERDOWN_OVERRIDE;
 907         value &= ~SOR_PLL_2_PORT_POWERDOWN;
 908         tegra_sor_writel(sor, value, SOR_PLL_2);
 909
 910         /*
 911          * power up
 912          */
 913
 914         /* set safe link bandwidth (1.62 Gbps) */
 915         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
 916         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
 917         value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62;
 918         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
 919
 920         /* step 1 */
 921         value = tegra_sor_readl(sor, SOR_PLL_2);
 922         value |= SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL_2_PORT_POWERDOWN |
 923                  SOR_PLL_2_BANDGAP_POWERDOWN;
 924         tegra_sor_writel(sor, value, SOR_PLL_2);
 925
 926         value = tegra_sor_readl(sor, SOR_PLL_0);
 927         value |= SOR_PLL_0_VCOPD | SOR_PLL_0_POWER_OFF;
 928         tegra_sor_writel(sor, value, SOR_PLL_0);
 929
 930         value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
 931         value &= ~SOR_DP_PADCTL_PAD_CAL_PD;
 932         tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
 933
 934         /* step 2 */
 935         err = tegra_io_rail_power_on(TEGRA_IO_RAIL_LVDS);
 936         if (err < 0) {
 937                 dev_err(sor->dev, "failed to power on I/O rail: %d\n", err);
 938                 goto unlock;
 939         }
 940
 941         usleep_range(5, 100);
 942
 943         /* step 3 */
 944         value = tegra_sor_readl(sor, SOR_PLL_2);
 945         value &= ~SOR_PLL_2_BANDGAP_POWERDOWN;
 946         tegra_sor_writel(sor, value, SOR_PLL_2);
 947
 948         usleep_range(20, 100);
 949
 950         /* step 4 */
 951         value = tegra_sor_readl(sor, SOR_PLL_0);
 952         value &= ~SOR_PLL_0_POWER_OFF;
 953         value &= ~SOR_PLL_0_VCOPD;
 954         tegra_sor_writel(sor, value, SOR_PLL_0);
 955
 956         value = tegra_sor_readl(sor, SOR_PLL_2);
 957         value &= ~SOR_PLL_2_SEQ_PLLCAPPD_ENFORCE;
 958         tegra_sor_writel(sor, value, SOR_PLL_2);
 959
 960         usleep_range(200, 1000);
 961
 962         /* step 5 */
 963         value = tegra_sor_readl(sor, SOR_PLL_2);
 964         value &= ~SOR_PLL_2_PORT_POWERDOWN;
 965         tegra_sor_writel(sor, value, SOR_PLL_2);
 966
 967         /* switch to DP clock */
 968         err = clk_set_parent(sor->clk, sor->clk_dp);
 969         if (err < 0)
 970                 dev_err(sor->dev, "failed to set DP parent clock: %d\n", err);
 971
 972         /* power DP lanes */
 973         value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
 974
 975         if (link.num_lanes <= 2)
 976                 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2);
 977         else
 978                 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2;
 979
 980         if (link.num_lanes <= 1)
 981                 value &= ~SOR_DP_PADCTL_PD_TXD_1;
 982         else
 983                 value |= SOR_DP_PADCTL_PD_TXD_1;
 984
 985         if (link.num_lanes == 0)
 986                 value &= ~SOR_DP_PADCTL_PD_TXD_0;
 987         else
 988                 value |= SOR_DP_PADCTL_PD_TXD_0;
 989
 990         tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
 991
 992         value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0);
 993         value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
 994         value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes);
 995         tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);
 996
 997         /* start lane sequencer */
 998         value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN |
 999                 SOR_LANE_SEQ_CTL_POWER_STATE_UP;
1000         tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL);
1001
1002         while (true) {
1003                 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL);
1004                 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0)
1005                         break;
1006
1007                 usleep_range(250, 1000);
1008         }
1009
1010         /* set link bandwidth */
1011         value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1012         value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1013         value |= drm_dp_link_rate_to_bw_code(link.rate) << 2;
1014         tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1015
1016         /* set linkctl */
1017         value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0);
1018         value |= SOR_DP_LINKCTL_ENABLE;
1019
1020         value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK;
1021         value |= SOR_DP_LINKCTL_TU_SIZE(config.tu_size);
1022
1023         value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1024         tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);
1025
1026         for (i = 0, value = 0; i < 4; i++) {
1027                 unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1028                                      SOR_DP_TPG_SCRAMBLER_GALIOS |
1029                                      SOR_DP_TPG_PATTERN_NONE;
1030                 value = (value << 8) | lane;
1031         }
1032
1033         tegra_sor_writel(sor, value, SOR_DP_TPG);
1034
1035         value = tegra_sor_readl(sor, SOR_DP_CONFIG_0);
1036         value &= ~SOR_DP_CONFIG_WATERMARK_MASK;
1037         value |= SOR_DP_CONFIG_WATERMARK(config.watermark);
1038
1039         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK;
1040         value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config.active_count);
1041
1042         value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK;
1043         value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config.active_frac);
1044
1045         if (config.active_polarity)
1046                 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1047         else
1048                 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY;
1049
1050         value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE;
1051         value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE;
1052         tegra_sor_writel(sor, value, SOR_DP_CONFIG_0);
1053
1054         value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1055         value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK;
1056         value |= config.hblank_symbols & 0xffff;
1057         tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS);
1058
1059         value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1060         value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK;
1061         value |= config.vblank_symbols & 0xffff;
1062         tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS);
1063
1064         /* enable pad calibration logic */
1065         value = tegra_sor_readl(sor, SOR_DP_PADCTL_0);
1066         value |= SOR_DP_PADCTL_PAD_CAL_PD;
1067         tegra_sor_writel(sor, value, SOR_DP_PADCTL_0);
1068
1069         if (sor->dpaux) {
1070                 u8 rate, lanes;
1071
1072                 err = drm_dp_link_probe(aux, &link);
1073                 if (err < 0) {
1074                         dev_err(sor->dev, "failed to probe eDP link: %d\n",
1075                                 err);
1076                         goto unlock;
1077                 }
1078
1079                 err = drm_dp_link_power_up(aux, &link);
1080                 if (err < 0) {
1081                         dev_err(sor->dev, "failed to power up eDP link: %d\n",
1082                                 err);
1083                         goto unlock;
1084                 }
1085
1086                 err = drm_dp_link_configure(aux, &link);
1087                 if (err < 0) {
1088                         dev_err(sor->dev, "failed to configure eDP link: %d\n",
1089                                 err);
1090                         goto unlock;
1091                 }
1092
1093                 rate = drm_dp_link_rate_to_bw_code(link.rate);
1094                 lanes = link.num_lanes;
1095
1096                 value = tegra_sor_readl(sor, SOR_CLK_CNTRL);
1097                 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK;
1098                 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate);
1099                 tegra_sor_writel(sor, value, SOR_CLK_CNTRL);
1100
1101                 value = tegra_sor_readl(sor, SOR_DP_LINKCTL_0);
1102                 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK;
1103                 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes);
1104
1105                 if (link.capabilities & DP_LINK_CAP_ENHANCED_FRAMING)
1106                         value |= SOR_DP_LINKCTL_ENHANCED_FRAME;
1107
1108                 tegra_sor_writel(sor, value, SOR_DP_LINKCTL_0);
1109
1110                 /* disable training pattern generator */
1111
1112                 for (i = 0; i < link.num_lanes; i++) {
1113                         unsigned long lane = SOR_DP_TPG_CHANNEL_CODING |
1114                                              SOR_DP_TPG_SCRAMBLER_GALIOS |
1115                                              SOR_DP_TPG_PATTERN_NONE;
1116                         value = (value << 8) | lane;
1117                 }
1118
1119                 tegra_sor_writel(sor, value, SOR_DP_TPG);
1120
1121                 err = tegra_sor_dp_train_fast(sor, &link);
1122                 if (err < 0) {
1123                         dev_err(sor->dev, "DP fast link training failed: %d\n",
1124                                 err);
1125                         goto unlock;
1126                 }
1127
1128                 dev_dbg(sor->dev, "fast link training succeeded\n");
1129         }
1130
1131         err = tegra_sor_power_up(sor, 250);
1132         if (err < 0) {
1133                 dev_err(sor->dev, "failed to power up SOR: %d\n", err);
1134                 goto unlock;
1135         }
1136
1137         /* start display controller in continuous mode */
1138         value = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1139         value |= WRITE_MUX;
1140         tegra_dc_writel(dc, value, DC_CMD_STATE_ACCESS);
1141
1142         tegra_dc_writel(dc, VSYNC_H_POSITION(1), DC_DISP_DISP_TIMING_OPTIONS);
1143         tegra_dc_writel(dc, DISP_CTRL_MODE_C_DISPLAY, DC_CMD_DISPLAY_COMMAND);
1144
1145         value = tegra_dc_readl(dc, DC_CMD_STATE_ACCESS);
1146         value &= ~WRITE_MUX;
1147         tegra_dc_writel(dc, value, DC_CMD_STATE_ACCESS);
1148
1149         /*
1150          * configure panel (24bpp, vsync-, hsync-, DP-A protocol, complete
1151          * raster, associate with display controller)
1152          */
1153         value = SOR_STATE_ASY_PROTOCOL_DP_A |
1154                 SOR_STATE_ASY_CRC_MODE_COMPLETE |
1155                 SOR_STATE_ASY_OWNER(dc->pipe + 1);
1156
1157         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
1158                 value &= ~SOR_STATE_ASY_HSYNCPOL;
1159
1160         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
1161                 value |= SOR_STATE_ASY_HSYNCPOL;
1162
1163         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
1164                 value &= ~SOR_STATE_ASY_VSYNCPOL;
1165
1166         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
1167                 value |= SOR_STATE_ASY_VSYNCPOL;
1168
1169         switch (config.bits_per_pixel) {
1170         case 24:
1171                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444;
1172                 break;
1173
1174         case 18:
1175                 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444;
1176                 break;
1177
1178         default:
1179                 BUG();
1180                 break;
1181         }
1182
1183         tegra_sor_writel(sor, value, SOR_STATE_1);
1184
1185         /*
1186          * TODO: The video timing programming below doesn't seem to match the
1187          * register definitions.
1188          */
1189
1190         value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff);
1191         tegra_sor_writel(sor, value, SOR_HEAD_STATE_1(0));
1192
1193         vse = mode->vsync_end - mode->vsync_start - 1;
1194         hse = mode->hsync_end - mode->hsync_start - 1;
1195
1196         value = ((vse & 0x7fff) << 16) | (hse & 0x7fff);
1197         tegra_sor_writel(sor, value, SOR_HEAD_STATE_2(0));
1198
1199         vbe = vse + (mode->vsync_start - mode->vdisplay);
1200         hbe = hse + (mode->hsync_start - mode->hdisplay);
1201
1202         value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff);
1203         tegra_sor_writel(sor, value, SOR_HEAD_STATE_3(0));
1204
1205         vbs = vbe + mode->vdisplay;
1206         hbs = hbe + mode->hdisplay;
1207
1208         value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff);
1209         tegra_sor_writel(sor, value, SOR_HEAD_STATE_4(0));
1210
1211         /* CSTM (LVDS, link A/B, upper) */
1212         value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B |
1213                 SOR_CSTM_UPPER;
1214         tegra_sor_writel(sor, value, SOR_CSTM);
1215
1216         /* PWM setup */
1217         err = tegra_sor_setup_pwm(sor, 250);
1218         if (err < 0) {
1219                 dev_err(sor->dev, "failed to setup PWM: %d\n", err);
1220                 goto unlock;
1221         }
1222
1223         value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1224         value |= SOR_ENABLE;
1225         tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1226
1227         tegra_sor_update(sor);
1228
1229         err = tegra_sor_attach(sor);
1230         if (err < 0) {
1231                 dev_err(sor->dev, "failed to attach SOR: %d\n", err);
1232                 goto unlock;
1233         }
1234
1235         err = tegra_sor_wakeup(sor);
1236         if (err < 0) {
1237                 dev_err(sor->dev, "failed to enable DC: %d\n", err);
1238                 goto unlock;
1239         }
1240
1241         if (output->panel)
1242                 drm_panel_enable(output->panel);
1243
1244         sor->enabled = true;
1245
1246 unlock:
1247         mutex_unlock(&sor->lock);
1248 }
1249
1250 static void tegra_sor_encoder_disable(struct drm_encoder *encoder)
1251 {
1252         struct tegra_output *output = encoder_to_output(encoder);
1253         struct tegra_dc *dc = to_tegra_dc(encoder->crtc);
1254         struct tegra_sor *sor = to_sor(output);
1255         u32 value;
1256         int err;
1257
1258         mutex_lock(&sor->lock);
1259
1260         if (!sor->enabled)
1261                 goto unlock;
1262
1263         if (output->panel)
1264                 drm_panel_disable(output->panel);
1265
1266         err = tegra_sor_detach(sor);
1267         if (err < 0) {
1268                 dev_err(sor->dev, "failed to detach SOR: %d\n", err);
1269                 goto unlock;
1270         }
1271
1272         tegra_sor_writel(sor, 0, SOR_STATE_1);
1273         tegra_sor_update(sor);
1274
1275         /*
1276          * The following accesses registers of the display controller, so make
1277          * sure it's only executed when the output is attached to one.
1278          */
1279         if (dc) {
1280                 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS);
1281                 value &= ~SOR_ENABLE;
1282                 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS);
1283
1284                 tegra_dc_commit(dc);
1285         }
1286
1287         err = tegra_sor_power_down(sor);
1288         if (err < 0) {
1289                 dev_err(sor->dev, "failed to power down SOR: %d\n", err);
1290                 goto unlock;
1291         }
1292
1293         if (sor->dpaux) {
1294                 err = tegra_dpaux_disable(sor->dpaux);
1295                 if (err < 0) {
1296                         dev_err(sor->dev, "failed to disable DP: %d\n", err);
1297                         goto unlock;
1298                 }
1299         }
1300
1301         err = tegra_io_rail_power_off(TEGRA_IO_RAIL_LVDS);
1302         if (err < 0) {
1303                 dev_err(sor->dev, "failed to power off I/O rail: %d\n", err);
1304                 goto unlock;
1305         }
1306
1307         if (output->panel)
1308                 drm_panel_unprepare(output->panel);
1309
1310         clk_disable_unprepare(sor->clk);
1311         reset_control_assert(sor->rst);
1312
1313         sor->enabled = false;
1314
1315 unlock:
1316         mutex_unlock(&sor->lock);
1317 }
1318
1319 static const struct drm_encoder_helper_funcs tegra_sor_encoder_helper_funcs = {
1320         .dpms = tegra_sor_encoder_dpms,
1321         .mode_fixup = tegra_sor_encoder_mode_fixup,
1322         .prepare = tegra_sor_encoder_prepare,
1323         .commit = tegra_sor_encoder_commit,
1324         .mode_set = tegra_sor_encoder_mode_set,
1325         .disable = tegra_sor_encoder_disable,
1326 };
1327
1328 static int tegra_sor_init(struct host1x_client *client)
1329 {
1330         struct drm_device *drm = dev_get_drvdata(client->parent);
1331         struct tegra_sor *sor = host1x_client_to_sor(client);
1332         int err;
1333
1334         if (!sor->dpaux)
1335                 return -ENODEV;
1336
1337         sor->output.dev = sor->dev;
1338
1339         drm_connector_init(drm, &sor->output.connector,
1340                            &tegra_sor_connector_funcs,
1341                            DRM_MODE_CONNECTOR_eDP);
1342         drm_connector_helper_add(&sor->output.connector,
1343                                  &tegra_sor_connector_helper_funcs);
1344         sor->output.connector.dpms = DRM_MODE_DPMS_OFF;
1345
1346         drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs,
1347                          DRM_MODE_ENCODER_TMDS);
1348         drm_encoder_helper_add(&sor->output.encoder,
1349                                &tegra_sor_encoder_helper_funcs);
1350
1351         drm_mode_connector_attach_encoder(&sor->output.connector,
1352                                           &sor->output.encoder);
1353         drm_connector_register(&sor->output.connector);
1354
1355         err = tegra_output_init(drm, &sor->output);
1356         if (err < 0) {
1357                 dev_err(client->dev, "failed to initialize output: %d\n", err);
1358                 return err;
1359         }
1360
1361         sor->output.encoder.possible_crtcs = 0x3;
1362
1363         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1364                 err = tegra_sor_debugfs_init(sor, drm->primary);
1365                 if (err < 0)
1366                         dev_err(sor->dev, "debugfs setup failed: %d\n", err);
1367         }
1368
1369         if (sor->dpaux) {
1370                 err = tegra_dpaux_attach(sor->dpaux, &sor->output);
1371                 if (err < 0) {
1372                         dev_err(sor->dev, "failed to attach DP: %d\n", err);
1373                         return err;
1374                 }
1375         }
1376
1377         err = clk_prepare_enable(sor->clk);
1378         if (err < 0) {
1379                 dev_err(sor->dev, "failed to enable clock: %d\n", err);
1380                 return err;
1381         }
1382
1383         err = clk_prepare_enable(sor->clk_safe);
1384         if (err < 0)
1385                 return err;
1386
1387         err = clk_prepare_enable(sor->clk_dp);
1388         if (err < 0)
1389                 return err;
1390
1391         return 0;
1392 }
1393
1394 static int tegra_sor_exit(struct host1x_client *client)
1395 {
1396         struct tegra_sor *sor = host1x_client_to_sor(client);
1397         int err;
1398
1399         if (sor->dpaux) {
1400                 err = tegra_dpaux_detach(sor->dpaux);
1401                 if (err < 0) {
1402                         dev_err(sor->dev, "failed to detach DP: %d\n", err);
1403                         return err;
1404                 }
1405         }
1406
1407         clk_disable_unprepare(sor->clk_safe);
1408         clk_disable_unprepare(sor->clk_dp);
1409         clk_disable_unprepare(sor->clk);
1410
1411         if (IS_ENABLED(CONFIG_DEBUG_FS))
1412                 tegra_sor_debugfs_exit(sor);
1413
1414         return 0;
1415 }
1416
1417 static const struct host1x_client_ops sor_client_ops = {
1418         .init = tegra_sor_init,
1419         .exit = tegra_sor_exit,
1420 };
1421
1422 static int tegra_sor_probe(struct platform_device *pdev)
1423 {
1424         struct device_node *np;
1425         struct tegra_sor *sor;
1426         struct resource *regs;
1427         int err;
1428
1429         sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL);
1430         if (!sor)
1431                 return -ENOMEM;
1432
1433         sor->output.dev = sor->dev = &pdev->dev;
1434
1435         np = of_parse_phandle(pdev->dev.of_node, "nvidia,dpaux", 0);
1436         if (np) {
1437                 sor->dpaux = tegra_dpaux_find_by_of_node(np);
1438                 of_node_put(np);
1439
1440                 if (!sor->dpaux)
1441                         return -EPROBE_DEFER;
1442         }
1443
1444         err = tegra_output_probe(&sor->output);
1445         if (err < 0)
1446                 return err;
1447
1448         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1449         sor->regs = devm_ioremap_resource(&pdev->dev, regs);
1450         if (IS_ERR(sor->regs))
1451                 return PTR_ERR(sor->regs);
1452
1453         sor->rst = devm_reset_control_get(&pdev->dev, "sor");
1454         if (IS_ERR(sor->rst))
1455                 return PTR_ERR(sor->rst);
1456
1457         sor->clk = devm_clk_get(&pdev->dev, NULL);
1458         if (IS_ERR(sor->clk))
1459                 return PTR_ERR(sor->clk);
1460
1461         sor->clk_parent = devm_clk_get(&pdev->dev, "parent");
1462         if (IS_ERR(sor->clk_parent))
1463                 return PTR_ERR(sor->clk_parent);
1464
1465         sor->clk_safe = devm_clk_get(&pdev->dev, "safe");
1466         if (IS_ERR(sor->clk_safe))
1467                 return PTR_ERR(sor->clk_safe);
1468
1469         sor->clk_dp = devm_clk_get(&pdev->dev, "dp");
1470         if (IS_ERR(sor->clk_dp))
1471                 return PTR_ERR(sor->clk_dp);
1472
1473         INIT_LIST_HEAD(&sor->client.list);
1474         sor->client.ops = &sor_client_ops;
1475         sor->client.dev = &pdev->dev;
1476
1477         mutex_init(&sor->lock);
1478
1479         err = host1x_client_register(&sor->client);
1480         if (err < 0) {
1481                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1482                         err);
1483                 return err;
1484         }
1485
1486         platform_set_drvdata(pdev, sor);
1487
1488         return 0;
1489 }
1490
1491 static int tegra_sor_remove(struct platform_device *pdev)
1492 {
1493         struct tegra_sor *sor = platform_get_drvdata(pdev);
1494         int err;
1495
1496         err = host1x_client_unregister(&sor->client);
1497         if (err < 0) {
1498                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1499                         err);
1500                 return err;
1501         }
1502
1503         err = tegra_output_remove(&sor->output);
1504         if (err < 0) {
1505                 dev_err(&pdev->dev, "failed to remove output: %d\n", err);
1506                 return err;
1507         }
1508
1509         return 0;
1510 }
1511
1512 static const struct of_device_id tegra_sor_of_match[] = {
1513         { .compatible = "nvidia,tegra124-sor", },
1514         { },
1515 };
1516 MODULE_DEVICE_TABLE(of, tegra_sor_of_match);
1517
1518 struct platform_driver tegra_sor_driver = {
1519         .driver = {
1520                 .name = "tegra-sor",
1521                 .of_match_table = tegra_sor_of_match,
1522         },
1523         .probe = tegra_sor_probe,
1524         .remove = tegra_sor_remove,
1525 };