2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/kfifo.h>
20 #include "tilcdc_drv.h"
21 #include "tilcdc_regs.h"
26 const struct tilcdc_panel_info *info;
28 dma_addr_t start, end;
29 struct drm_pending_vblank_event *event;
31 wait_queue_head_t frame_done_wq;
34 /* fb currently set to scanout 0/1: */
35 struct drm_framebuffer *scanout[2];
37 /* for deferred fb unref's: */
38 DECLARE_KFIFO_PTR(unref_fifo, struct drm_framebuffer *);
39 struct work_struct work;
41 #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base)
43 static void unref_worker(struct work_struct *work)
45 struct tilcdc_crtc *tilcdc_crtc = container_of(work, struct tilcdc_crtc, work);
46 struct drm_device *dev = tilcdc_crtc->base.dev;
47 struct drm_framebuffer *fb;
49 mutex_lock(&dev->mode_config.mutex);
50 while (kfifo_get(&tilcdc_crtc->unref_fifo, &fb))
51 drm_framebuffer_unreference(fb);
52 mutex_unlock(&dev->mode_config.mutex);
55 static void set_scanout(struct drm_crtc *crtc, int n)
57 static const uint32_t base_reg[] = {
58 LCDC_DMA_FB_BASE_ADDR_0_REG, LCDC_DMA_FB_BASE_ADDR_1_REG,
60 static const uint32_t ceil_reg[] = {
61 LCDC_DMA_FB_CEILING_ADDR_0_REG, LCDC_DMA_FB_CEILING_ADDR_1_REG,
63 static const uint32_t stat[] = {
64 LCDC_END_OF_FRAME0, LCDC_END_OF_FRAME1,
66 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
67 struct drm_device *dev = crtc->dev;
69 pm_runtime_get_sync(dev->dev);
70 tilcdc_write(dev, base_reg[n], tilcdc_crtc->start);
71 tilcdc_write(dev, ceil_reg[n], tilcdc_crtc->end);
72 if (tilcdc_crtc->scanout[n]) {
73 if (kfifo_put(&tilcdc_crtc->unref_fifo,
74 (const struct drm_framebuffer **)&tilcdc_crtc->scanout[n])) {
75 struct tilcdc_drm_private *priv = dev->dev_private;
76 queue_work(priv->wq, &tilcdc_crtc->work);
78 dev_err(dev->dev, "unref fifo full!\n");
79 drm_framebuffer_unreference(tilcdc_crtc->scanout[n]);
82 tilcdc_crtc->scanout[n] = crtc->fb;
83 drm_framebuffer_reference(tilcdc_crtc->scanout[n]);
84 tilcdc_crtc->dirty &= ~stat[n];
85 pm_runtime_put_sync(dev->dev);
88 static void update_scanout(struct drm_crtc *crtc)
90 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
91 struct drm_device *dev = crtc->dev;
92 struct drm_framebuffer *fb = crtc->fb;
93 struct drm_gem_cma_object *gem;
94 unsigned int depth, bpp;
96 drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
97 gem = drm_fb_cma_get_gem_obj(fb, 0);
99 tilcdc_crtc->start = gem->paddr + fb->offsets[0] +
100 (crtc->y * fb->pitches[0]) + (crtc->x * bpp/8);
102 tilcdc_crtc->end = tilcdc_crtc->start +
103 (crtc->mode.vdisplay * fb->pitches[0]);
105 if (tilcdc_crtc->dpms == DRM_MODE_DPMS_ON) {
106 /* already enabled, so just mark the frames that need
107 * updating and they will be updated on vblank:
109 tilcdc_crtc->dirty |= LCDC_END_OF_FRAME0 | LCDC_END_OF_FRAME1;
110 drm_vblank_get(dev, 0);
112 /* not enabled yet, so update registers immediately: */
113 set_scanout(crtc, 0);
114 set_scanout(crtc, 1);
118 static void start(struct drm_crtc *crtc)
120 struct drm_device *dev = crtc->dev;
121 struct tilcdc_drm_private *priv = dev->dev_private;
123 if (priv->rev == 2) {
124 tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
126 tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
130 tilcdc_set(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE);
131 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_PALETTE_LOAD_MODE(DATA_ONLY));
132 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
135 static void stop(struct drm_crtc *crtc)
137 struct drm_device *dev = crtc->dev;
139 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
142 static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
144 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
146 WARN_ON(tilcdc_crtc->dpms == DRM_MODE_DPMS_ON);
148 drm_crtc_cleanup(crtc);
149 WARN_ON(!kfifo_is_empty(&tilcdc_crtc->unref_fifo));
150 kfifo_free(&tilcdc_crtc->unref_fifo);
154 static int tilcdc_crtc_page_flip(struct drm_crtc *crtc,
155 struct drm_framebuffer *fb,
156 struct drm_pending_vblank_event *event)
158 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
159 struct drm_device *dev = crtc->dev;
161 if (tilcdc_crtc->event) {
162 dev_err(dev->dev, "already pending page flip!\n");
167 tilcdc_crtc->event = event;
168 update_scanout(crtc);
173 static void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode)
175 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
176 struct drm_device *dev = crtc->dev;
177 struct tilcdc_drm_private *priv = dev->dev_private;
179 /* we really only care about on or off: */
180 if (mode != DRM_MODE_DPMS_ON)
181 mode = DRM_MODE_DPMS_OFF;
183 if (tilcdc_crtc->dpms == mode)
186 tilcdc_crtc->dpms = mode;
188 pm_runtime_get_sync(dev->dev);
190 if (mode == DRM_MODE_DPMS_ON) {
191 pm_runtime_forbid(dev->dev);
194 tilcdc_crtc->frame_done = false;
197 /* if necessary wait for framedone irq which will still come
198 * before putting things to sleep..
200 if (priv->rev == 2) {
201 int ret = wait_event_timeout(
202 tilcdc_crtc->frame_done_wq,
203 tilcdc_crtc->frame_done,
204 msecs_to_jiffies(50));
206 dev_err(dev->dev, "timeout waiting for framedone\n");
208 pm_runtime_allow(dev->dev);
211 pm_runtime_put_sync(dev->dev);
214 static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc,
215 const struct drm_display_mode *mode,
216 struct drm_display_mode *adjusted_mode)
221 static void tilcdc_crtc_prepare(struct drm_crtc *crtc)
223 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
226 static void tilcdc_crtc_commit(struct drm_crtc *crtc)
228 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
231 static int tilcdc_crtc_mode_set(struct drm_crtc *crtc,
232 struct drm_display_mode *mode,
233 struct drm_display_mode *adjusted_mode,
235 struct drm_framebuffer *old_fb)
237 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
238 struct drm_device *dev = crtc->dev;
239 struct tilcdc_drm_private *priv = dev->dev_private;
240 const struct tilcdc_panel_info *info = tilcdc_crtc->info;
241 uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw;
244 ret = tilcdc_crtc_mode_valid(crtc, mode);
251 pm_runtime_get_sync(dev->dev);
253 /* Configure the Burst Size and fifo threshold of DMA: */
254 reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770;
255 switch (info->dma_burst_sz) {
257 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1);
260 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2);
263 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4);
266 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8);
269 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16);
274 reg |= (info->fifo_th << 8);
275 tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg);
277 /* Configure timings: */
278 hbp = mode->htotal - mode->hsync_end;
279 hfp = mode->hsync_start - mode->hdisplay;
280 hsw = mode->hsync_end - mode->hsync_start;
281 vbp = mode->vtotal - mode->vsync_end;
282 vfp = mode->vsync_start - mode->vdisplay;
283 vsw = mode->vsync_end - mode->vsync_start;
285 DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u",
286 mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw);
288 /* Configure the AC Bias Period and Number of Transitions per Interrupt: */
289 reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
290 reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) |
291 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt);
292 if (priv->rev == 2) {
293 reg |= (hfp & 0x300) >> 8;
294 reg |= (hbp & 0x300) >> 4;
295 reg |= (hsw & 0x3c0) << 21;
297 tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);
299 reg = (((mode->hdisplay >> 4) - 1) << 4) |
300 ((hbp & 0xff) << 24) |
301 ((hfp & 0xff) << 16) |
302 ((hsw & 0x3f) << 10);
304 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3;
305 tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg);
307 reg = ((mode->vdisplay - 1) & 0x3ff) |
308 ((vbp & 0xff) << 24) |
309 ((vfp & 0xff) << 16) |
310 ((vsw & 0x3f) << 10);
311 tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
314 * be sure to set Bit 10 for the V2 LCDC controller,
315 * otherwise limited to 1024 pixels width, stopping
316 * 1920x1080 being suppoted.
318 if (priv->rev == 2) {
319 if ((mode->vdisplay - 1) & 0x400) {
320 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
323 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,
328 /* Configure display type: */
329 reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
330 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE |
331 LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK | 0x000ff000);
332 reg |= LCDC_TFT_MODE; /* no monochrome/passive support */
333 if (info->tft_alt_mode)
334 reg |= LCDC_TFT_ALT_ENABLE;
335 if (priv->rev == 2) {
336 unsigned int depth, bpp;
338 drm_fb_get_bpp_depth(crtc->fb->pixel_format, &depth, &bpp);
343 reg |= LCDC_V2_TFT_24BPP_UNPACK;
346 reg |= LCDC_V2_TFT_24BPP_MODE;
349 dev_err(dev->dev, "invalid pixel format\n");
353 reg |= info->fdd < 12;
354 tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);
356 if (info->invert_pxl_clk)
357 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
359 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
362 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
364 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
367 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
369 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
371 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
372 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
374 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
376 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
377 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
379 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
381 if (info->raster_order)
382 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
384 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
387 update_scanout(crtc);
388 tilcdc_crtc_update_clk(crtc);
390 pm_runtime_put_sync(dev->dev);
395 static int tilcdc_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
396 struct drm_framebuffer *old_fb)
398 update_scanout(crtc);
402 static const struct drm_crtc_funcs tilcdc_crtc_funcs = {
403 .destroy = tilcdc_crtc_destroy,
404 .set_config = drm_crtc_helper_set_config,
405 .page_flip = tilcdc_crtc_page_flip,
408 static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = {
409 .dpms = tilcdc_crtc_dpms,
410 .mode_fixup = tilcdc_crtc_mode_fixup,
411 .prepare = tilcdc_crtc_prepare,
412 .commit = tilcdc_crtc_commit,
413 .mode_set = tilcdc_crtc_mode_set,
414 .mode_set_base = tilcdc_crtc_mode_set_base,
417 int tilcdc_crtc_max_width(struct drm_crtc *crtc)
419 struct drm_device *dev = crtc->dev;
420 struct tilcdc_drm_private *priv = dev->dev_private;
425 else if (priv->rev == 2)
431 int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode)
433 struct tilcdc_drm_private *priv = crtc->dev->dev_private;
434 unsigned int bandwidth;
436 if (mode->hdisplay > tilcdc_crtc_max_width(crtc))
437 return MODE_VIRTUAL_X;
439 /* width must be multiple of 16 */
440 if (mode->hdisplay & 0xf)
441 return MODE_VIRTUAL_X;
443 if (mode->vdisplay > 2048)
444 return MODE_VIRTUAL_Y;
447 * some devices have a maximum allowed pixel clock
448 * configured from the DT
450 if (mode->clock > priv->max_pixelclock) {
451 DBG("Pruning mode, pixel clock too high");
452 return MODE_CLOCK_HIGH;
456 * some devices further limit the max horizontal resolution
457 * configured from the DT
459 if (mode->hdisplay > priv->max_width)
460 return MODE_BAD_WIDTH;
462 /* filter out modes that would require too much memory bandwidth: */
463 bandwidth = mode->hdisplay * mode->vdisplay *
464 drm_mode_vrefresh(mode);
465 if (bandwidth > priv->max_bandwidth) {
466 DBG("Pruning mode, exceeds defined bandwidth limit");
473 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
474 const struct tilcdc_panel_info *info)
476 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
477 tilcdc_crtc->info = info;
480 void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
482 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
483 struct drm_device *dev = crtc->dev;
484 struct tilcdc_drm_private *priv = dev->dev_private;
485 int dpms = tilcdc_crtc->dpms;
486 unsigned int lcd_clk, div;
489 pm_runtime_get_sync(dev->dev);
491 if (dpms == DRM_MODE_DPMS_ON)
492 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
494 /* in raster mode, minimum divisor is 2: */
495 ret = clk_set_rate(priv->disp_clk, crtc->mode.clock * 1000 * 2);
497 dev_err(dev->dev, "failed to set display clock rate to: %d\n",
502 lcd_clk = clk_get_rate(priv->clk);
503 div = lcd_clk / (crtc->mode.clock * 1000);
505 DBG("lcd_clk=%u, mode clock=%d, div=%u", lcd_clk, crtc->mode.clock, div);
506 DBG("fck=%lu, dpll_disp_ck=%lu", clk_get_rate(priv->clk), clk_get_rate(priv->disp_clk));
508 /* Configure the LCD clock divisor. */
509 tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(div) |
513 tilcdc_set(dev, LCDC_CLK_ENABLE_REG,
514 LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN |
515 LCDC_V2_CORE_CLK_EN);
517 if (dpms == DRM_MODE_DPMS_ON)
518 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
521 pm_runtime_put_sync(dev->dev);
524 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
526 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
527 struct drm_device *dev = crtc->dev;
528 struct tilcdc_drm_private *priv = dev->dev_private;
529 uint32_t stat = tilcdc_read_irqstatus(dev);
531 if ((stat & LCDC_SYNC_LOST) && (stat & LCDC_FIFO_UNDERFLOW)) {
533 dev_err(dev->dev, "error: %08x\n", stat);
534 tilcdc_clear_irqstatus(dev, stat);
536 } else if (stat & LCDC_PL_LOAD_DONE) {
537 tilcdc_clear_irqstatus(dev, stat);
539 struct drm_pending_vblank_event *event;
541 uint32_t dirty = tilcdc_crtc->dirty & stat;
543 tilcdc_clear_irqstatus(dev, stat);
545 if (dirty & LCDC_END_OF_FRAME0)
546 set_scanout(crtc, 0);
548 if (dirty & LCDC_END_OF_FRAME1)
549 set_scanout(crtc, 1);
551 drm_handle_vblank(dev, 0);
553 spin_lock_irqsave(&dev->event_lock, flags);
554 event = tilcdc_crtc->event;
555 tilcdc_crtc->event = NULL;
557 drm_send_vblank_event(dev, 0, event);
558 spin_unlock_irqrestore(&dev->event_lock, flags);
560 if (dirty && !tilcdc_crtc->dirty)
561 drm_vblank_put(dev, 0);
564 if (priv->rev == 2) {
565 if (stat & LCDC_FRAME_DONE) {
566 tilcdc_crtc->frame_done = true;
567 wake_up(&tilcdc_crtc->frame_done_wq);
569 tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0);
575 void tilcdc_crtc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
577 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
578 struct drm_pending_vblank_event *event;
579 struct drm_device *dev = crtc->dev;
582 /* Destroy the pending vertical blanking event associated with the
583 * pending page flip, if any, and disable vertical blanking interrupts.
585 spin_lock_irqsave(&dev->event_lock, flags);
586 event = tilcdc_crtc->event;
587 if (event && event->base.file_priv == file) {
588 tilcdc_crtc->event = NULL;
589 event->base.destroy(&event->base);
590 drm_vblank_put(dev, 0);
592 spin_unlock_irqrestore(&dev->event_lock, flags);
595 struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev)
597 struct tilcdc_crtc *tilcdc_crtc;
598 struct drm_crtc *crtc;
601 tilcdc_crtc = kzalloc(sizeof(*tilcdc_crtc), GFP_KERNEL);
603 dev_err(dev->dev, "allocation failed\n");
607 crtc = &tilcdc_crtc->base;
609 tilcdc_crtc->dpms = DRM_MODE_DPMS_OFF;
610 init_waitqueue_head(&tilcdc_crtc->frame_done_wq);
612 ret = kfifo_alloc(&tilcdc_crtc->unref_fifo, 16, GFP_KERNEL);
614 dev_err(dev->dev, "could not allocate unref FIFO\n");
618 INIT_WORK(&tilcdc_crtc->work, unref_worker);
620 ret = drm_crtc_init(dev, crtc, &tilcdc_crtc_funcs);
624 drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs);
629 tilcdc_crtc_destroy(crtc);