drivers/gpu/drm/tilcdc/tilcdc_crtc.c

   1 /*
   2  * Copyright (C) 2012 Texas Instruments
   3  * Author: Rob Clark <robdclark@gmail.com>
   4  *
   5  * This program is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 as published by
   7  * the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  12  * more details.
  13  *
  14  * You should have received a copy of the GNU General Public License along with
  15  * this program.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <linux/kfifo.h>
  19
  20 #include "tilcdc_drv.h"
  21 #include "tilcdc_regs.h"
  22
  23 struct tilcdc_crtc {
  24         struct drm_crtc base;
  25
  26         const struct tilcdc_panel_info *info;
  27         uint32_t dirty;
  28         dma_addr_t start, end;
  29         struct drm_pending_vblank_event *event;
  30         int dpms;
  31         wait_queue_head_t frame_done_wq;
  32         bool frame_done;
  33
  34         /* fb currently set to scanout 0/1: */
  35         struct drm_framebuffer *scanout[2];
  36
  37         /* for deferred fb unref's: */
  38         DECLARE_KFIFO_PTR(unref_fifo, struct drm_framebuffer *);
  39         struct work_struct work;
  40 };
  41 #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base)
  42
  43 static void unref_worker(struct work_struct *work)
  44 {
  45         struct tilcdc_crtc *tilcdc_crtc =
  46                 container_of(work, struct tilcdc_crtc, work);
  47         struct drm_device *dev = tilcdc_crtc->base.dev;
  48         struct drm_framebuffer *fb;
  49
  50         mutex_lock(&dev->mode_config.mutex);
  51         while (kfifo_get(&tilcdc_crtc->unref_fifo, &fb))
  52                 drm_framebuffer_unreference(fb);
  53         mutex_unlock(&dev->mode_config.mutex);
  54 }
  55
  56 static void set_scanout(struct drm_crtc *crtc, int n)
  57 {
  58         static const uint32_t base_reg[] = {
  59                         LCDC_DMA_FB_BASE_ADDR_0_REG,
  60                         LCDC_DMA_FB_BASE_ADDR_1_REG,
  61         };
  62         static const uint32_t ceil_reg[] = {
  63                         LCDC_DMA_FB_CEILING_ADDR_0_REG,
  64                         LCDC_DMA_FB_CEILING_ADDR_1_REG,
  65         };
  66         static const uint32_t stat[] = {
  67                         LCDC_END_OF_FRAME0, LCDC_END_OF_FRAME1,
  68         };
  69         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
  70         struct drm_device *dev = crtc->dev;
  71
  72         pm_runtime_get_sync(dev->dev);
  73         tilcdc_write(dev, base_reg[n], tilcdc_crtc->start);
  74         tilcdc_write(dev, ceil_reg[n], tilcdc_crtc->end);
  75         if (tilcdc_crtc->scanout[n]) {
  76                 if (kfifo_put(&tilcdc_crtc->unref_fifo,
  77                                 (const struct drm_framebuffer **)&tilcdc_crtc->scanout[n])) {
  78                         struct tilcdc_drm_private *priv = dev->dev_private;
  79                         queue_work(priv->wq, &tilcdc_crtc->work);
  80                 } else {
  81                         dev_err(dev->dev, "unref fifo full!\n");
  82                         drm_framebuffer_unreference(tilcdc_crtc->scanout[n]);
  83                 }
  84         }
  85         tilcdc_crtc->scanout[n] = crtc->fb;
  86         drm_framebuffer_reference(tilcdc_crtc->scanout[n]);
  87         tilcdc_crtc->dirty &= ~stat[n];
  88         pm_runtime_put_sync(dev->dev);
  89 }
  90
  91 static void update_scanout(struct drm_crtc *crtc)
  92 {
  93         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
  94         struct drm_device *dev = crtc->dev;
  95         struct drm_framebuffer *fb = crtc->fb;
  96         struct drm_gem_cma_object *gem;
  97         unsigned int depth, bpp;
  98
  99         drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
 100         gem = drm_fb_cma_get_gem_obj(fb, 0);
 101
 102         tilcdc_crtc->start = gem->paddr + fb->offsets[0] +
 103                         (crtc->y * fb->pitches[0]) + (crtc->x * bpp/8);
 104
 105         tilcdc_crtc->end = tilcdc_crtc->start +
 106                         (crtc->mode.vdisplay * fb->pitches[0]);
 107
 108         if (tilcdc_crtc->dpms == DRM_MODE_DPMS_ON) {
 109                 /* already enabled, so just mark the frames that need
 110                  * updating and they will be updated on vblank:
 111                  */
 112                 tilcdc_crtc->dirty |= LCDC_END_OF_FRAME0 | LCDC_END_OF_FRAME1;
 113                 drm_vblank_get(dev, 0);
 114         } else {
 115                 /* not enabled yet, so update registers immediately: */
 116                 set_scanout(crtc, 0);
 117                 set_scanout(crtc, 1);
 118         }
 119 }
 120
 121 static void start(struct drm_crtc *crtc)
 122 {
 123         struct drm_device *dev = crtc->dev;
 124         struct tilcdc_drm_private *priv = dev->dev_private;
 125
 126         if (priv->rev == 2) {
 127                 tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
 128                 msleep(1);
 129                 tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
 130                 msleep(1);
 131         }
 132
 133         tilcdc_set(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE);
 134         tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_PALETTE_LOAD_MODE(DATA_ONLY));
 135         tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 136 }
 137
 138 static void stop(struct drm_crtc *crtc)
 139 {
 140         struct drm_device *dev = crtc->dev;
 141
 142         tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
 143 }
 144
 145 static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
 146 {
 147         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 148
 149         WARN_ON(tilcdc_crtc->dpms == DRM_MODE_DPMS_ON);
 150
 151         drm_crtc_cleanup(crtc);
 152         WARN_ON(!kfifo_is_empty(&tilcdc_crtc->unref_fifo));
 153         kfifo_free(&tilcdc_crtc->unref_fifo);
 154         kfree(tilcdc_crtc);
 155 }
 156
 157 static int tilcdc_crtc_page_flip(struct drm_crtc *crtc,
 158                 struct drm_framebuffer *fb,
 159                 struct drm_pending_vblank_event *event)
 160 {
 161         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 162         struct drm_device *dev = crtc->dev;
 163
 164         if (tilcdc_crtc->event) {
 165                 dev_err(dev->dev, "already pending page flip!\n");
 166                 return -EBUSY;
 167         }
 168
 169         crtc->fb = fb;
 170         tilcdc_crtc->event = event;
 171         update_scanout(crtc);
 172
 173         return 0;
 174 }
 175
 176 static void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode)
 177 {
 178         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 179         struct drm_device *dev = crtc->dev;
 180         struct tilcdc_drm_private *priv = dev->dev_private;
 181
 182         /* we really only care about on or off: */
 183         if (mode != DRM_MODE_DPMS_ON)
 184                 mode = DRM_MODE_DPMS_OFF;
 185
 186         if (tilcdc_crtc->dpms == mode)
 187                 return;
 188
 189         tilcdc_crtc->dpms = mode;
 190
 191         pm_runtime_get_sync(dev->dev);
 192
 193         if (mode == DRM_MODE_DPMS_ON) {
 194                 pm_runtime_forbid(dev->dev);
 195                 start(crtc);
 196         } else {
 197                 tilcdc_crtc->frame_done = false;
 198                 stop(crtc);
 199
 200                 /*
 201                  * if necessary wait for framedone irq which will still come
 202                  * before putting things to sleep..
 203                  */
 204                 if (priv->rev == 2) {
 205                         int ret = wait_event_timeout(
 206                                         tilcdc_crtc->frame_done_wq,
 207                                         tilcdc_crtc->frame_done,
 208                                         msecs_to_jiffies(50));
 209                         if (ret == 0)
 210                                 dev_err(dev->dev, "timeout waiting for framedone\n");
 211                 }
 212                 pm_runtime_allow(dev->dev);
 213         }
 214
 215         pm_runtime_put_sync(dev->dev);
 216 }
 217
 218 static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc,
 219                 const struct drm_display_mode *mode,
 220                 struct drm_display_mode *adjusted_mode)
 221 {
 222         return true;
 223 }
 224
 225 static void tilcdc_crtc_prepare(struct drm_crtc *crtc)
 226 {
 227         tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 228 }
 229
 230 static void tilcdc_crtc_commit(struct drm_crtc *crtc)
 231 {
 232         tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 233 }
 234
 235 static int tilcdc_crtc_mode_set(struct drm_crtc *crtc,
 236                 struct drm_display_mode *mode,
 237                 struct drm_display_mode *adjusted_mode,
 238                 int x, int y,
 239                 struct drm_framebuffer *old_fb)
 240 {
 241         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 242         struct drm_device *dev = crtc->dev;
 243         struct tilcdc_drm_private *priv = dev->dev_private;
 244         const struct tilcdc_panel_info *info = tilcdc_crtc->info;
 245         uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw;
 246         int ret;
 247
 248         ret = tilcdc_crtc_mode_valid(crtc, mode);
 249         if (WARN_ON(ret))
 250                 return ret;
 251
 252         if (WARN_ON(!info))
 253                 return -EINVAL;
 254
 255         pm_runtime_get_sync(dev->dev);
 256
 257         /* Configure the Burst Size and fifo threshold of DMA: */
 258         reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770;
 259         switch (info->dma_burst_sz) {
 260         case 1:
 261                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1);
 262                 break;
 263         case 2:
 264                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2);
 265                 break;
 266         case 4:
 267                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4);
 268                 break;
 269         case 8:
 270                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8);
 271                 break;
 272         case 16:
 273                 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16);
 274                 break;
 275         default:
 276                 return -EINVAL;
 277         }
 278         reg |= (info->fifo_th << 8);
 279         tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg);
 280
 281         /* Configure timings: */
 282         hbp = mode->htotal - mode->hsync_end;
 283         hfp = mode->hsync_start - mode->hdisplay;
 284         hsw = mode->hsync_end - mode->hsync_start;
 285         vbp = mode->vtotal - mode->vsync_end;
 286         vfp = mode->vsync_start - mode->vdisplay;
 287         vsw = mode->vsync_end - mode->vsync_start;
 288
 289         DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u",
 290                         mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw);
 291
 292         /* Configure the AC Bias Period and Number of Transitions per Interrupt: */
 293         reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
 294         reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) |
 295                 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt);
 296
 297         /*
 298          * subtract one from hfp, hbp, hsw because the hardware uses
 299          * a value of 0 as 1
 300          */
 301         if (priv->rev == 2) {
 302                 /* clear bits we're going to set */
 303                 reg &= ~0x78000033;
 304                 reg |= ((hfp-1) & 0x300) >> 8;
 305                 reg |= ((hbp-1) & 0x300) >> 4;
 306                 reg |= ((hsw-1) & 0x3c0) << 21;
 307         }
 308         tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);
 309
 310         reg = (((mode->hdisplay >> 4) - 1) << 4) |
 311                 (((hbp-1) & 0xff) << 24) |
 312                 (((hfp-1) & 0xff) << 16) |
 313                 (((hsw-1) & 0x3f) << 10);
 314         if (priv->rev == 2)
 315                 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3;
 316         tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg);
 317
 318         reg = ((mode->vdisplay - 1) & 0x3ff) |
 319                 ((vbp & 0xff) << 24) |
 320                 ((vfp & 0xff) << 16) |
 321                 (((vsw-1) & 0x3f) << 10);
 322         tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
 323
 324         /*
 325          * be sure to set Bit 10 for the V2 LCDC controller,
 326          * otherwise limited to 1024 pixels width, stopping
 327          * 1920x1080 being suppoted.
 328          */
 329         if (priv->rev == 2) {
 330                 if ((mode->vdisplay - 1) & 0x400) {
 331                         tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
 332                                 LCDC_LPP_B10);
 333                 } else {
 334                         tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,
 335                                 LCDC_LPP_B10);
 336                 }
 337         }
 338
 339         /* Configure display type: */
 340         reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
 341                 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE |
 342                         LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK | 0x000ff000);
 343         reg |= LCDC_TFT_MODE; /* no monochrome/passive support */
 344         if (info->tft_alt_mode)
 345                 reg |= LCDC_TFT_ALT_ENABLE;
 346         if (priv->rev == 2) {
 347                 unsigned int depth, bpp;
 348
 349                 drm_fb_get_bpp_depth(crtc->fb->pixel_format, &depth, &bpp);
 350                 switch (bpp) {
 351                 case 16:
 352                         break;
 353                 case 32:
 354                         reg |= LCDC_V2_TFT_24BPP_UNPACK;
 355                         /* fallthrough */
 356                 case 24:
 357                         reg |= LCDC_V2_TFT_24BPP_MODE;
 358                         break;
 359                 default:
 360                         dev_err(dev->dev, "invalid pixel format\n");
 361                         return -EINVAL;
 362                 }
 363         }
 364         reg |= info->fdd < 12;
 365         tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);
 366
 367         if (info->invert_pxl_clk)
 368                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
 369         else
 370                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
 371
 372         if (info->sync_ctrl)
 373                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
 374         else
 375                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
 376
 377         if (info->sync_edge)
 378                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
 379         else
 380                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
 381
 382         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
 383                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
 384         else
 385                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
 386
 387         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
 388                 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
 389         else
 390                 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
 391
 392         if (info->raster_order)
 393                 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
 394         else
 395                 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
 396
 397
 398         update_scanout(crtc);
 399         tilcdc_crtc_update_clk(crtc);
 400
 401         pm_runtime_put_sync(dev->dev);
 402
 403         return 0;
 404 }
 405
 406 static int tilcdc_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
 407                 struct drm_framebuffer *old_fb)
 408 {
 409         update_scanout(crtc);
 410         return 0;
 411 }
 412
 413 static const struct drm_crtc_funcs tilcdc_crtc_funcs = {
 414                 .destroy        = tilcdc_crtc_destroy,
 415                 .set_config     = drm_crtc_helper_set_config,
 416                 .page_flip      = tilcdc_crtc_page_flip,
 417 };
 418
 419 static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = {
 420                 .dpms           = tilcdc_crtc_dpms,
 421                 .mode_fixup     = tilcdc_crtc_mode_fixup,
 422                 .prepare        = tilcdc_crtc_prepare,
 423                 .commit         = tilcdc_crtc_commit,
 424                 .mode_set       = tilcdc_crtc_mode_set,
 425                 .mode_set_base  = tilcdc_crtc_mode_set_base,
 426 };
 427
 428 int tilcdc_crtc_max_width(struct drm_crtc *crtc)
 429 {
 430         struct drm_device *dev = crtc->dev;
 431         struct tilcdc_drm_private *priv = dev->dev_private;
 432         int max_width = 0;
 433
 434         if (priv->rev == 1)
 435                 max_width = 1024;
 436         else if (priv->rev == 2)
 437                 max_width = 2048;
 438
 439         return max_width;
 440 }
 441
 442 int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode)
 443 {
 444         struct tilcdc_drm_private *priv = crtc->dev->dev_private;
 445         unsigned int bandwidth;
 446         uint32_t hbp, hfp, hsw, vbp, vfp, vsw;
 447
 448         /*
 449          * check to see if the width is within the range that
 450          * the LCD Controller physically supports
 451          */
 452         if (mode->hdisplay > tilcdc_crtc_max_width(crtc))
 453                 return MODE_VIRTUAL_X;
 454
 455         /* width must be multiple of 16 */
 456         if (mode->hdisplay & 0xf)
 457                 return MODE_VIRTUAL_X;
 458
 459         if (mode->vdisplay > 2048)
 460                 return MODE_VIRTUAL_Y;
 461
 462         DBG("Processing mode %dx%d@%d with pixel clock %d",
 463                 mode->hdisplay, mode->vdisplay,
 464                 drm_mode_vrefresh(mode), mode->clock);
 465
 466         hbp = mode->htotal - mode->hsync_end;
 467         hfp = mode->hsync_start - mode->hdisplay;
 468         hsw = mode->hsync_end - mode->hsync_start;
 469         vbp = mode->vtotal - mode->vsync_end;
 470         vfp = mode->vsync_start - mode->vdisplay;
 471         vsw = mode->vsync_end - mode->vsync_start;
 472
 473         if ((hbp-1) & ~0x3ff) {
 474                 DBG("Pruning mode: Horizontal Back Porch out of range");
 475                 return MODE_HBLANK_WIDE;
 476         }
 477
 478         if ((hfp-1) & ~0x3ff) {
 479                 DBG("Pruning mode: Horizontal Front Porch out of range");
 480                 return MODE_HBLANK_WIDE;
 481         }
 482
 483         if ((hsw-1) & ~0x3ff) {
 484                 DBG("Pruning mode: Horizontal Sync Width out of range");
 485                 return MODE_HSYNC_WIDE;
 486         }
 487
 488         if (vbp & ~0xff) {
 489                 DBG("Pruning mode: Vertical Back Porch out of range");
 490                 return MODE_VBLANK_WIDE;
 491         }
 492
 493         if (vfp & ~0xff) {
 494                 DBG("Pruning mode: Vertical Front Porch out of range");
 495                 return MODE_VBLANK_WIDE;
 496         }
 497
 498         if ((vsw-1) & ~0x3f) {
 499                 DBG("Pruning mode: Vertical Sync Width out of range");
 500                 return MODE_VSYNC_WIDE;
 501         }
 502
 503         /*
 504          * some devices have a maximum allowed pixel clock
 505          * configured from the DT
 506          */
 507         if (mode->clock > priv->max_pixelclock) {
 508                 DBG("Pruning mode: pixel clock too high");
 509                 return MODE_CLOCK_HIGH;
 510         }
 511
 512         /*
 513          * some devices further limit the max horizontal resolution
 514          * configured from the DT
 515          */
 516         if (mode->hdisplay > priv->max_width)
 517                 return MODE_BAD_WIDTH;
 518
 519         /* filter out modes that would require too much memory bandwidth: */
 520         bandwidth = mode->hdisplay * mode->vdisplay *
 521                 drm_mode_vrefresh(mode);
 522         if (bandwidth > priv->max_bandwidth) {
 523                 DBG("Pruning mode: exceeds defined bandwidth limit");
 524                 return MODE_BAD;
 525         }
 526
 527         return MODE_OK;
 528 }
 529
 530 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
 531                 const struct tilcdc_panel_info *info)
 532 {
 533         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 534         tilcdc_crtc->info = info;
 535 }
 536
 537 void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
 538 {
 539         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 540         struct drm_device *dev = crtc->dev;
 541         struct tilcdc_drm_private *priv = dev->dev_private;
 542         int dpms = tilcdc_crtc->dpms;
 543         unsigned int lcd_clk, div;
 544         int ret;
 545
 546         pm_runtime_get_sync(dev->dev);
 547
 548         if (dpms == DRM_MODE_DPMS_ON)
 549                 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
 550
 551         /* in raster mode, minimum divisor is 2: */
 552         ret = clk_set_rate(priv->disp_clk, crtc->mode.clock * 1000 * 2);
 553         if (ret) {
 554                 dev_err(dev->dev, "failed to set display clock rate to: %d\n",
 555                                 crtc->mode.clock);
 556                 goto out;
 557         }
 558
 559         lcd_clk = clk_get_rate(priv->clk);
 560         div = lcd_clk / (crtc->mode.clock * 1000);
 561
 562         DBG("lcd_clk=%u, mode clock=%d, div=%u", lcd_clk, crtc->mode.clock, div);
 563         DBG("fck=%lu, dpll_disp_ck=%lu", clk_get_rate(priv->clk), clk_get_rate(priv->disp_clk));
 564
 565         /* Configure the LCD clock divisor. */
 566         tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(div) |
 567                         LCDC_RASTER_MODE);
 568
 569         if (priv->rev == 2)
 570                 tilcdc_set(dev, LCDC_CLK_ENABLE_REG,
 571                                 LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN |
 572                                 LCDC_V2_CORE_CLK_EN);
 573
 574         if (dpms == DRM_MODE_DPMS_ON)
 575                 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
 576
 577 out:
 578         pm_runtime_put_sync(dev->dev);
 579 }
 580
 581 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
 582 {
 583         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 584         struct drm_device *dev = crtc->dev;
 585         struct tilcdc_drm_private *priv = dev->dev_private;
 586         uint32_t stat = tilcdc_read_irqstatus(dev);
 587
 588         if ((stat & LCDC_SYNC_LOST) && (stat & LCDC_FIFO_UNDERFLOW)) {
 589                 stop(crtc);
 590                 dev_err(dev->dev, "error: %08x\n", stat);
 591                 tilcdc_clear_irqstatus(dev, stat);
 592                 start(crtc);
 593         } else if (stat & LCDC_PL_LOAD_DONE) {
 594                 tilcdc_clear_irqstatus(dev, stat);
 595         } else {
 596                 struct drm_pending_vblank_event *event;
 597                 unsigned long flags;
 598                 uint32_t dirty = tilcdc_crtc->dirty & stat;
 599
 600                 tilcdc_clear_irqstatus(dev, stat);
 601
 602                 if (dirty & LCDC_END_OF_FRAME0)
 603                         set_scanout(crtc, 0);
 604
 605                 if (dirty & LCDC_END_OF_FRAME1)
 606                         set_scanout(crtc, 1);
 607
 608                 drm_handle_vblank(dev, 0);
 609
 610                 spin_lock_irqsave(&dev->event_lock, flags);
 611                 event = tilcdc_crtc->event;
 612                 tilcdc_crtc->event = NULL;
 613                 if (event)
 614                         drm_send_vblank_event(dev, 0, event);
 615                 spin_unlock_irqrestore(&dev->event_lock, flags);
 616
 617                 if (dirty && !tilcdc_crtc->dirty)
 618                         drm_vblank_put(dev, 0);
 619         }
 620
 621         if (priv->rev == 2) {
 622                 if (stat & LCDC_FRAME_DONE) {
 623                         tilcdc_crtc->frame_done = true;
 624                         wake_up(&tilcdc_crtc->frame_done_wq);
 625                 }
 626                 tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0);
 627         }
 628
 629         return IRQ_HANDLED;
 630 }
 631
 632 void tilcdc_crtc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
 633 {
 634         struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
 635         struct drm_pending_vblank_event *event;
 636         struct drm_device *dev = crtc->dev;
 637         unsigned long flags;
 638
 639         /* Destroy the pending vertical blanking event associated with the
 640          * pending page flip, if any, and disable vertical blanking interrupts.
 641          */
 642         spin_lock_irqsave(&dev->event_lock, flags);
 643         event = tilcdc_crtc->event;
 644         if (event && event->base.file_priv == file) {
 645                 tilcdc_crtc->event = NULL;
 646                 event->base.destroy(&event->base);
 647                 drm_vblank_put(dev, 0);
 648         }
 649         spin_unlock_irqrestore(&dev->event_lock, flags);
 650 }
 651
 652 struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev)
 653 {
 654         struct tilcdc_crtc *tilcdc_crtc;
 655         struct drm_crtc *crtc;
 656         int ret;
 657
 658         tilcdc_crtc = kzalloc(sizeof(*tilcdc_crtc), GFP_KERNEL);
 659         if (!tilcdc_crtc) {
 660                 dev_err(dev->dev, "allocation failed\n");
 661                 return NULL;
 662         }
 663
 664         crtc = &tilcdc_crtc->base;
 665
 666         tilcdc_crtc->dpms = DRM_MODE_DPMS_OFF;
 667         init_waitqueue_head(&tilcdc_crtc->frame_done_wq);
 668
 669         ret = kfifo_alloc(&tilcdc_crtc->unref_fifo, 16, GFP_KERNEL);
 670         if (ret) {
 671                 dev_err(dev->dev, "could not allocate unref FIFO\n");
 672                 goto fail;
 673         }
 674
 675         INIT_WORK(&tilcdc_crtc->work, unref_worker);
 676
 677         ret = drm_crtc_init(dev, crtc, &tilcdc_crtc_funcs);
 678         if (ret < 0)
 679                 goto fail;
 680
 681         drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs);
 682
 683         return crtc;
 684
 685 fail:
 686         tilcdc_crtc_destroy(crtc);
 687         return NULL;
 688 }