2 * Copyright (C) 2012 Texas Instruments
3 * Author: Rob Clark <robdclark@gmail.com>
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 as published by
7 * the Free Software Foundation.
9 * This program is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
14 * You should have received a copy of the GNU General Public License along with
15 * this program. If not, see <http://www.gnu.org/licenses/>.
18 #include <linux/kfifo.h>
20 #include "tilcdc_drv.h"
21 #include "tilcdc_regs.h"
26 const struct tilcdc_panel_info *info;
28 dma_addr_t start, end;
29 struct drm_pending_vblank_event *event;
31 wait_queue_head_t frame_done_wq;
34 /* fb currently set to scanout 0/1: */
35 struct drm_framebuffer *scanout[2];
37 /* for deferred fb unref's: */
38 DECLARE_KFIFO_PTR(unref_fifo, struct drm_framebuffer *);
39 struct work_struct work;
41 #define to_tilcdc_crtc(x) container_of(x, struct tilcdc_crtc, base)
43 static void unref_worker(struct work_struct *work)
45 struct tilcdc_crtc *tilcdc_crtc =
46 container_of(work, struct tilcdc_crtc, work);
47 struct drm_device *dev = tilcdc_crtc->base.dev;
48 struct drm_framebuffer *fb;
50 mutex_lock(&dev->mode_config.mutex);
51 while (kfifo_get(&tilcdc_crtc->unref_fifo, &fb))
52 drm_framebuffer_unreference(fb);
53 mutex_unlock(&dev->mode_config.mutex);
56 static void set_scanout(struct drm_crtc *crtc, int n)
58 static const uint32_t base_reg[] = {
59 LCDC_DMA_FB_BASE_ADDR_0_REG,
60 LCDC_DMA_FB_BASE_ADDR_1_REG,
62 static const uint32_t ceil_reg[] = {
63 LCDC_DMA_FB_CEILING_ADDR_0_REG,
64 LCDC_DMA_FB_CEILING_ADDR_1_REG,
66 static const uint32_t stat[] = {
67 LCDC_END_OF_FRAME0, LCDC_END_OF_FRAME1,
69 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
70 struct drm_device *dev = crtc->dev;
72 pm_runtime_get_sync(dev->dev);
73 tilcdc_write(dev, base_reg[n], tilcdc_crtc->start);
74 tilcdc_write(dev, ceil_reg[n], tilcdc_crtc->end);
75 if (tilcdc_crtc->scanout[n]) {
76 if (kfifo_put(&tilcdc_crtc->unref_fifo,
77 (const struct drm_framebuffer **)&tilcdc_crtc->scanout[n])) {
78 struct tilcdc_drm_private *priv = dev->dev_private;
79 queue_work(priv->wq, &tilcdc_crtc->work);
81 dev_err(dev->dev, "unref fifo full!\n");
82 drm_framebuffer_unreference(tilcdc_crtc->scanout[n]);
85 tilcdc_crtc->scanout[n] = crtc->fb;
86 drm_framebuffer_reference(tilcdc_crtc->scanout[n]);
87 tilcdc_crtc->dirty &= ~stat[n];
88 pm_runtime_put_sync(dev->dev);
91 static void update_scanout(struct drm_crtc *crtc)
93 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
94 struct drm_device *dev = crtc->dev;
95 struct drm_framebuffer *fb = crtc->fb;
96 struct drm_gem_cma_object *gem;
97 unsigned int depth, bpp;
99 drm_fb_get_bpp_depth(fb->pixel_format, &depth, &bpp);
100 gem = drm_fb_cma_get_gem_obj(fb, 0);
102 tilcdc_crtc->start = gem->paddr + fb->offsets[0] +
103 (crtc->y * fb->pitches[0]) + (crtc->x * bpp/8);
105 tilcdc_crtc->end = tilcdc_crtc->start +
106 (crtc->mode.vdisplay * fb->pitches[0]);
108 if (tilcdc_crtc->dpms == DRM_MODE_DPMS_ON) {
109 /* already enabled, so just mark the frames that need
110 * updating and they will be updated on vblank:
112 tilcdc_crtc->dirty |= LCDC_END_OF_FRAME0 | LCDC_END_OF_FRAME1;
113 drm_vblank_get(dev, 0);
115 /* not enabled yet, so update registers immediately: */
116 set_scanout(crtc, 0);
117 set_scanout(crtc, 1);
121 static void start(struct drm_crtc *crtc)
123 struct drm_device *dev = crtc->dev;
124 struct tilcdc_drm_private *priv = dev->dev_private;
126 if (priv->rev == 2) {
127 tilcdc_set(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
129 tilcdc_clear(dev, LCDC_CLK_RESET_REG, LCDC_CLK_MAIN_RESET);
133 tilcdc_set(dev, LCDC_DMA_CTRL_REG, LCDC_DUAL_FRAME_BUFFER_ENABLE);
134 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_PALETTE_LOAD_MODE(DATA_ONLY));
135 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
138 static void stop(struct drm_crtc *crtc)
140 struct drm_device *dev = crtc->dev;
142 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ENABLE);
145 static void tilcdc_crtc_destroy(struct drm_crtc *crtc)
147 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
149 WARN_ON(tilcdc_crtc->dpms == DRM_MODE_DPMS_ON);
151 drm_crtc_cleanup(crtc);
152 WARN_ON(!kfifo_is_empty(&tilcdc_crtc->unref_fifo));
153 kfifo_free(&tilcdc_crtc->unref_fifo);
157 static int tilcdc_crtc_page_flip(struct drm_crtc *crtc,
158 struct drm_framebuffer *fb,
159 struct drm_pending_vblank_event *event)
161 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
162 struct drm_device *dev = crtc->dev;
164 if (tilcdc_crtc->event) {
165 dev_err(dev->dev, "already pending page flip!\n");
170 tilcdc_crtc->event = event;
171 update_scanout(crtc);
176 static void tilcdc_crtc_dpms(struct drm_crtc *crtc, int mode)
178 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
179 struct drm_device *dev = crtc->dev;
180 struct tilcdc_drm_private *priv = dev->dev_private;
182 /* we really only care about on or off: */
183 if (mode != DRM_MODE_DPMS_ON)
184 mode = DRM_MODE_DPMS_OFF;
186 if (tilcdc_crtc->dpms == mode)
189 tilcdc_crtc->dpms = mode;
191 pm_runtime_get_sync(dev->dev);
193 if (mode == DRM_MODE_DPMS_ON) {
194 pm_runtime_forbid(dev->dev);
197 tilcdc_crtc->frame_done = false;
201 * if necessary wait for framedone irq which will still come
202 * before putting things to sleep..
204 if (priv->rev == 2) {
205 int ret = wait_event_timeout(
206 tilcdc_crtc->frame_done_wq,
207 tilcdc_crtc->frame_done,
208 msecs_to_jiffies(50));
210 dev_err(dev->dev, "timeout waiting for framedone\n");
212 pm_runtime_allow(dev->dev);
215 pm_runtime_put_sync(dev->dev);
218 static bool tilcdc_crtc_mode_fixup(struct drm_crtc *crtc,
219 const struct drm_display_mode *mode,
220 struct drm_display_mode *adjusted_mode)
225 static void tilcdc_crtc_prepare(struct drm_crtc *crtc)
227 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
230 static void tilcdc_crtc_commit(struct drm_crtc *crtc)
232 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
235 static int tilcdc_crtc_mode_set(struct drm_crtc *crtc,
236 struct drm_display_mode *mode,
237 struct drm_display_mode *adjusted_mode,
239 struct drm_framebuffer *old_fb)
241 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
242 struct drm_device *dev = crtc->dev;
243 struct tilcdc_drm_private *priv = dev->dev_private;
244 const struct tilcdc_panel_info *info = tilcdc_crtc->info;
245 uint32_t reg, hbp, hfp, hsw, vbp, vfp, vsw;
248 ret = tilcdc_crtc_mode_valid(crtc, mode);
255 pm_runtime_get_sync(dev->dev);
257 /* Configure the Burst Size and fifo threshold of DMA: */
258 reg = tilcdc_read(dev, LCDC_DMA_CTRL_REG) & ~0x00000770;
259 switch (info->dma_burst_sz) {
261 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_1);
264 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_2);
267 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_4);
270 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_8);
273 reg |= LCDC_DMA_BURST_SIZE(LCDC_DMA_BURST_16);
278 reg |= (info->fifo_th << 8);
279 tilcdc_write(dev, LCDC_DMA_CTRL_REG, reg);
281 /* Configure timings: */
282 hbp = mode->htotal - mode->hsync_end;
283 hfp = mode->hsync_start - mode->hdisplay;
284 hsw = mode->hsync_end - mode->hsync_start;
285 vbp = mode->vtotal - mode->vsync_end;
286 vfp = mode->vsync_start - mode->vdisplay;
287 vsw = mode->vsync_end - mode->vsync_start;
289 DBG("%dx%d, hbp=%u, hfp=%u, hsw=%u, vbp=%u, vfp=%u, vsw=%u",
290 mode->hdisplay, mode->vdisplay, hbp, hfp, hsw, vbp, vfp, vsw);
292 /* Configure the AC Bias Period and Number of Transitions per Interrupt: */
293 reg = tilcdc_read(dev, LCDC_RASTER_TIMING_2_REG) & ~0x000fff00;
294 reg |= LCDC_AC_BIAS_FREQUENCY(info->ac_bias) |
295 LCDC_AC_BIAS_TRANSITIONS_PER_INT(info->ac_bias_intrpt);
298 * subtract one from hfp, hbp, hsw because the hardware uses
301 if (priv->rev == 2) {
302 reg |= ((hfp-1) & 0x300) >> 8;
303 reg |= ((hbp-1) & 0x300) >> 4;
304 reg |= ((hsw-1) & 0x3c0) << 21;
306 tilcdc_write(dev, LCDC_RASTER_TIMING_2_REG, reg);
308 reg = (((mode->hdisplay >> 4) - 1) << 4) |
309 (((hbp-1) & 0xff) << 24) |
310 (((hfp-1) & 0xff) << 16) |
311 (((hsw-1) & 0x3f) << 10);
313 reg |= (((mode->hdisplay >> 4) - 1) & 0x40) >> 3;
314 tilcdc_write(dev, LCDC_RASTER_TIMING_0_REG, reg);
316 reg = ((mode->vdisplay - 1) & 0x3ff) |
317 ((vbp & 0xff) << 24) |
318 ((vfp & 0xff) << 16) |
319 (((vsw-1) & 0x3f) << 10);
320 tilcdc_write(dev, LCDC_RASTER_TIMING_1_REG, reg);
323 * be sure to set Bit 10 for the V2 LCDC controller,
324 * otherwise limited to 1024 pixels width, stopping
325 * 1920x1080 being suppoted.
327 if (priv->rev == 2) {
328 if ((mode->vdisplay - 1) & 0x400) {
329 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG,
332 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG,
337 /* Configure display type: */
338 reg = tilcdc_read(dev, LCDC_RASTER_CTRL_REG) &
339 ~(LCDC_TFT_MODE | LCDC_MONO_8BIT_MODE | LCDC_MONOCHROME_MODE |
340 LCDC_V2_TFT_24BPP_MODE | LCDC_V2_TFT_24BPP_UNPACK | 0x000ff000);
341 reg |= LCDC_TFT_MODE; /* no monochrome/passive support */
342 if (info->tft_alt_mode)
343 reg |= LCDC_TFT_ALT_ENABLE;
344 if (priv->rev == 2) {
345 unsigned int depth, bpp;
347 drm_fb_get_bpp_depth(crtc->fb->pixel_format, &depth, &bpp);
352 reg |= LCDC_V2_TFT_24BPP_UNPACK;
355 reg |= LCDC_V2_TFT_24BPP_MODE;
358 dev_err(dev->dev, "invalid pixel format\n");
362 reg |= info->fdd < 12;
363 tilcdc_write(dev, LCDC_RASTER_CTRL_REG, reg);
365 if (info->invert_pxl_clk)
366 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
368 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_PIXEL_CLOCK);
371 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
373 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_CTRL);
376 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
378 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_SYNC_EDGE);
380 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
381 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
383 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_HSYNC);
385 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
386 tilcdc_set(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
388 tilcdc_clear(dev, LCDC_RASTER_TIMING_2_REG, LCDC_INVERT_VSYNC);
390 if (info->raster_order)
391 tilcdc_set(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
393 tilcdc_clear(dev, LCDC_RASTER_CTRL_REG, LCDC_RASTER_ORDER);
396 update_scanout(crtc);
397 tilcdc_crtc_update_clk(crtc);
399 pm_runtime_put_sync(dev->dev);
404 static int tilcdc_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
405 struct drm_framebuffer *old_fb)
407 update_scanout(crtc);
411 static const struct drm_crtc_funcs tilcdc_crtc_funcs = {
412 .destroy = tilcdc_crtc_destroy,
413 .set_config = drm_crtc_helper_set_config,
414 .page_flip = tilcdc_crtc_page_flip,
417 static const struct drm_crtc_helper_funcs tilcdc_crtc_helper_funcs = {
418 .dpms = tilcdc_crtc_dpms,
419 .mode_fixup = tilcdc_crtc_mode_fixup,
420 .prepare = tilcdc_crtc_prepare,
421 .commit = tilcdc_crtc_commit,
422 .mode_set = tilcdc_crtc_mode_set,
423 .mode_set_base = tilcdc_crtc_mode_set_base,
426 int tilcdc_crtc_max_width(struct drm_crtc *crtc)
428 struct drm_device *dev = crtc->dev;
429 struct tilcdc_drm_private *priv = dev->dev_private;
434 else if (priv->rev == 2)
440 int tilcdc_crtc_mode_valid(struct drm_crtc *crtc, struct drm_display_mode *mode)
442 struct tilcdc_drm_private *priv = crtc->dev->dev_private;
443 unsigned int bandwidth;
444 uint32_t hbp, hfp, hsw, vbp, vfp, vsw;
447 * check to see if the width is within the range that
448 * the LCD Controller physically supports
450 if (mode->hdisplay > tilcdc_crtc_max_width(crtc))
451 return MODE_VIRTUAL_X;
453 /* width must be multiple of 16 */
454 if (mode->hdisplay & 0xf)
455 return MODE_VIRTUAL_X;
457 if (mode->vdisplay > 2048)
458 return MODE_VIRTUAL_Y;
460 DBG("Processing mode %dx%d@%d with pixel clock %d",
461 mode->hdisplay, mode->vdisplay,
462 drm_mode_vrefresh(mode), mode->clock);
464 hbp = mode->htotal - mode->hsync_end;
465 hfp = mode->hsync_start - mode->hdisplay;
466 hsw = mode->hsync_end - mode->hsync_start;
467 vbp = mode->vtotal - mode->vsync_end;
468 vfp = mode->vsync_start - mode->vdisplay;
469 vsw = mode->vsync_end - mode->vsync_start;
471 if ((hbp-1) & ~0x3ff) {
472 DBG("Pruning mode: Horizontal Back Porch out of range");
473 return MODE_HBLANK_WIDE;
476 if ((hfp-1) & ~0x3ff) {
477 DBG("Pruning mode: Horizontal Front Porch out of range");
478 return MODE_HBLANK_WIDE;
481 if ((hsw-1) & ~0x3ff) {
482 DBG("Pruning mode: Horizontal Sync Width out of range");
483 return MODE_HSYNC_WIDE;
487 DBG("Pruning mode: Vertical Back Porch out of range");
488 return MODE_VBLANK_WIDE;
492 DBG("Pruning mode: Vertical Front Porch out of range");
493 return MODE_VBLANK_WIDE;
496 if ((vsw-1) & ~0x3f) {
497 DBG("Pruning mode: Vertical Sync Width out of range");
498 return MODE_VSYNC_WIDE;
502 * some devices have a maximum allowed pixel clock
503 * configured from the DT
505 if (mode->clock > priv->max_pixelclock) {
506 DBG("Pruning mode: pixel clock too high");
507 return MODE_CLOCK_HIGH;
511 * some devices further limit the max horizontal resolution
512 * configured from the DT
514 if (mode->hdisplay > priv->max_width)
515 return MODE_BAD_WIDTH;
517 /* filter out modes that would require too much memory bandwidth: */
518 bandwidth = mode->hdisplay * mode->vdisplay *
519 drm_mode_vrefresh(mode);
520 if (bandwidth > priv->max_bandwidth) {
521 DBG("Pruning mode: exceeds defined bandwidth limit");
528 void tilcdc_crtc_set_panel_info(struct drm_crtc *crtc,
529 const struct tilcdc_panel_info *info)
531 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
532 tilcdc_crtc->info = info;
535 void tilcdc_crtc_update_clk(struct drm_crtc *crtc)
537 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
538 struct drm_device *dev = crtc->dev;
539 struct tilcdc_drm_private *priv = dev->dev_private;
540 int dpms = tilcdc_crtc->dpms;
541 unsigned int lcd_clk, div;
544 pm_runtime_get_sync(dev->dev);
546 if (dpms == DRM_MODE_DPMS_ON)
547 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_OFF);
549 /* in raster mode, minimum divisor is 2: */
550 ret = clk_set_rate(priv->disp_clk, crtc->mode.clock * 1000 * 2);
552 dev_err(dev->dev, "failed to set display clock rate to: %d\n",
557 lcd_clk = clk_get_rate(priv->clk);
558 div = lcd_clk / (crtc->mode.clock * 1000);
560 DBG("lcd_clk=%u, mode clock=%d, div=%u", lcd_clk, crtc->mode.clock, div);
561 DBG("fck=%lu, dpll_disp_ck=%lu", clk_get_rate(priv->clk), clk_get_rate(priv->disp_clk));
563 /* Configure the LCD clock divisor. */
564 tilcdc_write(dev, LCDC_CTRL_REG, LCDC_CLK_DIVISOR(div) |
568 tilcdc_set(dev, LCDC_CLK_ENABLE_REG,
569 LCDC_V2_DMA_CLK_EN | LCDC_V2_LIDD_CLK_EN |
570 LCDC_V2_CORE_CLK_EN);
572 if (dpms == DRM_MODE_DPMS_ON)
573 tilcdc_crtc_dpms(crtc, DRM_MODE_DPMS_ON);
576 pm_runtime_put_sync(dev->dev);
579 irqreturn_t tilcdc_crtc_irq(struct drm_crtc *crtc)
581 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
582 struct drm_device *dev = crtc->dev;
583 struct tilcdc_drm_private *priv = dev->dev_private;
584 uint32_t stat = tilcdc_read_irqstatus(dev);
586 if ((stat & LCDC_SYNC_LOST) && (stat & LCDC_FIFO_UNDERFLOW)) {
588 dev_err(dev->dev, "error: %08x\n", stat);
589 tilcdc_clear_irqstatus(dev, stat);
591 } else if (stat & LCDC_PL_LOAD_DONE) {
592 tilcdc_clear_irqstatus(dev, stat);
594 struct drm_pending_vblank_event *event;
596 uint32_t dirty = tilcdc_crtc->dirty & stat;
598 tilcdc_clear_irqstatus(dev, stat);
600 if (dirty & LCDC_END_OF_FRAME0)
601 set_scanout(crtc, 0);
603 if (dirty & LCDC_END_OF_FRAME1)
604 set_scanout(crtc, 1);
606 drm_handle_vblank(dev, 0);
608 spin_lock_irqsave(&dev->event_lock, flags);
609 event = tilcdc_crtc->event;
610 tilcdc_crtc->event = NULL;
612 drm_send_vblank_event(dev, 0, event);
613 spin_unlock_irqrestore(&dev->event_lock, flags);
615 if (dirty && !tilcdc_crtc->dirty)
616 drm_vblank_put(dev, 0);
619 if (priv->rev == 2) {
620 if (stat & LCDC_FRAME_DONE) {
621 tilcdc_crtc->frame_done = true;
622 wake_up(&tilcdc_crtc->frame_done_wq);
624 tilcdc_write(dev, LCDC_END_OF_INT_IND_REG, 0);
630 void tilcdc_crtc_cancel_page_flip(struct drm_crtc *crtc, struct drm_file *file)
632 struct tilcdc_crtc *tilcdc_crtc = to_tilcdc_crtc(crtc);
633 struct drm_pending_vblank_event *event;
634 struct drm_device *dev = crtc->dev;
637 /* Destroy the pending vertical blanking event associated with the
638 * pending page flip, if any, and disable vertical blanking interrupts.
640 spin_lock_irqsave(&dev->event_lock, flags);
641 event = tilcdc_crtc->event;
642 if (event && event->base.file_priv == file) {
643 tilcdc_crtc->event = NULL;
644 event->base.destroy(&event->base);
645 drm_vblank_put(dev, 0);
647 spin_unlock_irqrestore(&dev->event_lock, flags);
650 struct drm_crtc *tilcdc_crtc_create(struct drm_device *dev)
652 struct tilcdc_crtc *tilcdc_crtc;
653 struct drm_crtc *crtc;
656 tilcdc_crtc = kzalloc(sizeof(*tilcdc_crtc), GFP_KERNEL);
658 dev_err(dev->dev, "allocation failed\n");
662 crtc = &tilcdc_crtc->base;
664 tilcdc_crtc->dpms = DRM_MODE_DPMS_OFF;
665 init_waitqueue_head(&tilcdc_crtc->frame_done_wq);
667 ret = kfifo_alloc(&tilcdc_crtc->unref_fifo, 16, GFP_KERNEL);
669 dev_err(dev->dev, "could not allocate unref FIFO\n");
673 INIT_WORK(&tilcdc_crtc->work, unref_worker);
675 ret = drm_crtc_init(dev, crtc, &tilcdc_crtc_funcs);
679 drm_crtc_helper_add(crtc, &tilcdc_crtc_helper_funcs);
684 tilcdc_crtc_destroy(crtc);