drivers/gpu/drm/vmwgfx/vmwgfx_fifo.c

   1 /**************************************************************************
   2  *
   3  * Copyright © 2009 VMware, Inc., Palo Alto, CA., USA
   4  * All Rights Reserved.
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a
   7  * copy of this software and associated documentation files (the
   8  * "Software"), to deal in the Software without restriction, including
   9  * without limitation the rights to use, copy, modify, merge, publish,
  10  * distribute, sub license, and/or sell copies of the Software, and to
  11  * permit persons to whom the Software is furnished to do so, subject to
  12  * the following conditions:
  13  *
  14  * The above copyright notice and this permission notice (including the
  15  * next paragraph) shall be included in all copies or substantial portions
  16  * of the Software.
  17  *
  18  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  19  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  20  * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
  21  * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
  22  * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
  23  * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
  24  * USE OR OTHER DEALINGS IN THE SOFTWARE.
  25  *
  26  **************************************************************************/
  27
  28 #include "vmwgfx_drv.h"
  29 #include <drm/drmP.h>
  30 #include <drm/ttm/ttm_placement.h>
  31
  32 bool vmw_fifo_have_3d(struct vmw_private *dev_priv)
  33 {
  34         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  35         uint32_t fifo_min, hwversion;
  36         const struct vmw_fifo_state *fifo = &dev_priv->fifo;
  37
  38         if (!(dev_priv->capabilities & SVGA_CAP_3D))
  39                 return false;
  40
  41         if (dev_priv->capabilities & SVGA_CAP_GBOBJECTS) {
  42                 uint32_t result;
  43
  44                 if (!dev_priv->has_mob)
  45                         return false;
  46
  47                 mutex_lock(&dev_priv->hw_mutex);
  48                 vmw_write(dev_priv, SVGA_REG_DEV_CAP, SVGA3D_DEVCAP_3D);
  49                 result = vmw_read(dev_priv, SVGA_REG_DEV_CAP);
  50                 mutex_unlock(&dev_priv->hw_mutex);
  51
  52                 return (result != 0);
  53         }
  54
  55         if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
  56                 return false;
  57
  58         fifo_min = ioread32(fifo_mem  + SVGA_FIFO_MIN);
  59         if (fifo_min <= SVGA_FIFO_3D_HWVERSION * sizeof(unsigned int))
  60                 return false;
  61
  62         hwversion = ioread32(fifo_mem +
  63                              ((fifo->capabilities &
  64                                SVGA_FIFO_CAP_3D_HWVERSION_REVISED) ?
  65                               SVGA_FIFO_3D_HWVERSION_REVISED :
  66                               SVGA_FIFO_3D_HWVERSION));
  67
  68         if (hwversion == 0)
  69                 return false;
  70
  71         if (hwversion < SVGA3D_HWVERSION_WS8_B1)
  72                 return false;
  73
  74         /* Non-Screen Object path does not support surfaces */
  75         if (!dev_priv->sou_priv)
  76                 return false;
  77
  78         return true;
  79 }
  80
  81 bool vmw_fifo_have_pitchlock(struct vmw_private *dev_priv)
  82 {
  83         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  84         uint32_t caps;
  85
  86         if (!(dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO))
  87                 return false;
  88
  89         caps = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
  90         if (caps & SVGA_FIFO_CAP_PITCHLOCK)
  91                 return true;
  92
  93         return false;
  94 }
  95
  96 int vmw_fifo_init(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
  97 {
  98         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
  99         uint32_t max;
 100         uint32_t min;
 101         uint32_t dummy;
 102
 103         fifo->static_buffer_size = VMWGFX_FIFO_STATIC_SIZE;
 104         fifo->static_buffer = vmalloc(fifo->static_buffer_size);
 105         if (unlikely(fifo->static_buffer == NULL))
 106                 return -ENOMEM;
 107
 108         fifo->dynamic_buffer = NULL;
 109         fifo->reserved_size = 0;
 110         fifo->using_bounce_buffer = false;
 111
 112         mutex_init(&fifo->fifo_mutex);
 113         init_rwsem(&fifo->rwsem);
 114
 115         /*
 116          * Allow mapping the first page read-only to user-space.
 117          */
 118
 119         DRM_INFO("width %d\n", vmw_read(dev_priv, SVGA_REG_WIDTH));
 120         DRM_INFO("height %d\n", vmw_read(dev_priv, SVGA_REG_HEIGHT));
 121         DRM_INFO("bpp %d\n", vmw_read(dev_priv, SVGA_REG_BITS_PER_PIXEL));
 122
 123         mutex_lock(&dev_priv->hw_mutex);
 124         dev_priv->enable_state = vmw_read(dev_priv, SVGA_REG_ENABLE);
 125         dev_priv->config_done_state = vmw_read(dev_priv, SVGA_REG_CONFIG_DONE);
 126         dev_priv->traces_state = vmw_read(dev_priv, SVGA_REG_TRACES);
 127         vmw_write(dev_priv, SVGA_REG_ENABLE, 1);
 128
 129         min = 4;
 130         if (dev_priv->capabilities & SVGA_CAP_EXTENDED_FIFO)
 131                 min = vmw_read(dev_priv, SVGA_REG_MEM_REGS);
 132         min <<= 2;
 133
 134         if (min < PAGE_SIZE)
 135                 min = PAGE_SIZE;
 136
 137         iowrite32(min, fifo_mem + SVGA_FIFO_MIN);
 138         iowrite32(dev_priv->mmio_size, fifo_mem + SVGA_FIFO_MAX);
 139         wmb();
 140         iowrite32(min,  fifo_mem + SVGA_FIFO_NEXT_CMD);
 141         iowrite32(min,  fifo_mem + SVGA_FIFO_STOP);
 142         iowrite32(0, fifo_mem + SVGA_FIFO_BUSY);
 143         mb();
 144
 145         vmw_write(dev_priv, SVGA_REG_CONFIG_DONE, 1);
 146         mutex_unlock(&dev_priv->hw_mutex);
 147
 148         max = ioread32(fifo_mem + SVGA_FIFO_MAX);
 149         min = ioread32(fifo_mem  + SVGA_FIFO_MIN);
 150         fifo->capabilities = ioread32(fifo_mem + SVGA_FIFO_CAPABILITIES);
 151
 152         DRM_INFO("Fifo max 0x%08x min 0x%08x cap 0x%08x\n",
 153                  (unsigned int) max,
 154                  (unsigned int) min,
 155                  (unsigned int) fifo->capabilities);
 156
 157         atomic_set(&dev_priv->marker_seq, dev_priv->last_read_seqno);
 158         iowrite32(dev_priv->last_read_seqno, fifo_mem + SVGA_FIFO_FENCE);
 159         vmw_marker_queue_init(&fifo->marker_queue);
 160         return vmw_fifo_send_fence(dev_priv, &dummy);
 161 }
 162
 163 void vmw_fifo_ping_host(struct vmw_private *dev_priv, uint32_t reason)
 164 {
 165         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
 166
 167         mutex_lock(&dev_priv->hw_mutex);
 168
 169         if (unlikely(ioread32(fifo_mem + SVGA_FIFO_BUSY) == 0)) {
 170                 iowrite32(1, fifo_mem + SVGA_FIFO_BUSY);
 171                 vmw_write(dev_priv, SVGA_REG_SYNC, reason);
 172         }
 173
 174         mutex_unlock(&dev_priv->hw_mutex);
 175 }
 176
 177 void vmw_fifo_release(struct vmw_private *dev_priv, struct vmw_fifo_state *fifo)
 178 {
 179         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
 180
 181         mutex_lock(&dev_priv->hw_mutex);
 182
 183         vmw_write(dev_priv, SVGA_REG_SYNC, SVGA_SYNC_GENERIC);
 184         while (vmw_read(dev_priv, SVGA_REG_BUSY) != 0)
 185                 ;
 186
 187         dev_priv->last_read_seqno = ioread32(fifo_mem + SVGA_FIFO_FENCE);
 188
 189         vmw_write(dev_priv, SVGA_REG_CONFIG_DONE,
 190                   dev_priv->config_done_state);
 191         vmw_write(dev_priv, SVGA_REG_ENABLE,
 192                   dev_priv->enable_state);
 193         vmw_write(dev_priv, SVGA_REG_TRACES,
 194                   dev_priv->traces_state);
 195
 196         mutex_unlock(&dev_priv->hw_mutex);
 197         vmw_marker_queue_takedown(&fifo->marker_queue);
 198
 199         if (likely(fifo->static_buffer != NULL)) {
 200                 vfree(fifo->static_buffer);
 201                 fifo->static_buffer = NULL;
 202         }
 203
 204         if (likely(fifo->dynamic_buffer != NULL)) {
 205                 vfree(fifo->dynamic_buffer);
 206                 fifo->dynamic_buffer = NULL;
 207         }
 208 }
 209
 210 static bool vmw_fifo_is_full(struct vmw_private *dev_priv, uint32_t bytes)
 211 {
 212         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
 213         uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
 214         uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
 215         uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
 216         uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
 217
 218         return ((max - next_cmd) + (stop - min) <= bytes);
 219 }
 220
 221 static int vmw_fifo_wait_noirq(struct vmw_private *dev_priv,
 222                                uint32_t bytes, bool interruptible,
 223                                unsigned long timeout)
 224 {
 225         int ret = 0;
 226         unsigned long end_jiffies = jiffies + timeout;
 227         DEFINE_WAIT(__wait);
 228
 229         DRM_INFO("Fifo wait noirq.\n");
 230
 231         for (;;) {
 232                 prepare_to_wait(&dev_priv->fifo_queue, &__wait,
 233                                 (interruptible) ?
 234                                 TASK_INTERRUPTIBLE : TASK_UNINTERRUPTIBLE);
 235                 if (!vmw_fifo_is_full(dev_priv, bytes))
 236                         break;
 237                 if (time_after_eq(jiffies, end_jiffies)) {
 238                         ret = -EBUSY;
 239                         DRM_ERROR("SVGA device lockup.\n");
 240                         break;
 241                 }
 242                 schedule_timeout(1);
 243                 if (interruptible && signal_pending(current)) {
 244                         ret = -ERESTARTSYS;
 245                         break;
 246                 }
 247         }
 248         finish_wait(&dev_priv->fifo_queue, &__wait);
 249         wake_up_all(&dev_priv->fifo_queue);
 250         DRM_INFO("Fifo noirq exit.\n");
 251         return ret;
 252 }
 253
 254 static int vmw_fifo_wait(struct vmw_private *dev_priv,
 255                          uint32_t bytes, bool interruptible,
 256                          unsigned long timeout)
 257 {
 258         long ret = 1L;
 259         unsigned long irq_flags;
 260
 261         if (likely(!vmw_fifo_is_full(dev_priv, bytes)))
 262                 return 0;
 263
 264         vmw_fifo_ping_host(dev_priv, SVGA_SYNC_FIFOFULL);
 265         if (!(dev_priv->capabilities & SVGA_CAP_IRQMASK))
 266                 return vmw_fifo_wait_noirq(dev_priv, bytes,
 267                                            interruptible, timeout);
 268
 269         mutex_lock(&dev_priv->hw_mutex);
 270         if (atomic_add_return(1, &dev_priv->fifo_queue_waiters) > 0) {
 271                 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
 272                 outl(SVGA_IRQFLAG_FIFO_PROGRESS,
 273                      dev_priv->io_start + VMWGFX_IRQSTATUS_PORT);
 274                 dev_priv->irq_mask |= SVGA_IRQFLAG_FIFO_PROGRESS;
 275                 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
 276                 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
 277         }
 278         mutex_unlock(&dev_priv->hw_mutex);
 279
 280         if (interruptible)
 281                 ret = wait_event_interruptible_timeout
 282                     (dev_priv->fifo_queue,
 283                      !vmw_fifo_is_full(dev_priv, bytes), timeout);
 284         else
 285                 ret = wait_event_timeout
 286                     (dev_priv->fifo_queue,
 287                      !vmw_fifo_is_full(dev_priv, bytes), timeout);
 288
 289         if (unlikely(ret == 0))
 290                 ret = -EBUSY;
 291         else if (likely(ret > 0))
 292                 ret = 0;
 293
 294         mutex_lock(&dev_priv->hw_mutex);
 295         if (atomic_dec_and_test(&dev_priv->fifo_queue_waiters)) {
 296                 spin_lock_irqsave(&dev_priv->irq_lock, irq_flags);
 297                 dev_priv->irq_mask &= ~SVGA_IRQFLAG_FIFO_PROGRESS;
 298                 vmw_write(dev_priv, SVGA_REG_IRQMASK, dev_priv->irq_mask);
 299                 spin_unlock_irqrestore(&dev_priv->irq_lock, irq_flags);
 300         }
 301         mutex_unlock(&dev_priv->hw_mutex);
 302
 303         return ret;
 304 }
 305
 306 /**
 307  * Reserve @bytes number of bytes in the fifo.
 308  *
 309  * This function will return NULL (error) on two conditions:
 310  *  If it timeouts waiting for fifo space, or if @bytes is larger than the
 311  *   available fifo space.
 312  *
 313  * Returns:
 314  *   Pointer to the fifo, or null on error (possible hardware hang).
 315  */
 316 void *vmw_fifo_reserve(struct vmw_private *dev_priv, uint32_t bytes)
 317 {
 318         struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
 319         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
 320         uint32_t max;
 321         uint32_t min;
 322         uint32_t next_cmd;
 323         uint32_t reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
 324         int ret;
 325
 326         mutex_lock(&fifo_state->fifo_mutex);
 327         max = ioread32(fifo_mem + SVGA_FIFO_MAX);
 328         min = ioread32(fifo_mem + SVGA_FIFO_MIN);
 329         next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
 330
 331         if (unlikely(bytes >= (max - min)))
 332                 goto out_err;
 333
 334         BUG_ON(fifo_state->reserved_size != 0);
 335         BUG_ON(fifo_state->dynamic_buffer != NULL);
 336
 337         fifo_state->reserved_size = bytes;
 338
 339         while (1) {
 340                 uint32_t stop = ioread32(fifo_mem + SVGA_FIFO_STOP);
 341                 bool need_bounce = false;
 342                 bool reserve_in_place = false;
 343
 344                 if (next_cmd >= stop) {
 345                         if (likely((next_cmd + bytes < max ||
 346                                     (next_cmd + bytes == max && stop > min))))
 347                                 reserve_in_place = true;
 348
 349                         else if (vmw_fifo_is_full(dev_priv, bytes)) {
 350                                 ret = vmw_fifo_wait(dev_priv, bytes,
 351                                                     false, 3 * HZ);
 352                                 if (unlikely(ret != 0))
 353                                         goto out_err;
 354                         } else
 355                                 need_bounce = true;
 356
 357                 } else {
 358
 359                         if (likely((next_cmd + bytes < stop)))
 360                                 reserve_in_place = true;
 361                         else {
 362                                 ret = vmw_fifo_wait(dev_priv, bytes,
 363                                                     false, 3 * HZ);
 364                                 if (unlikely(ret != 0))
 365                                         goto out_err;
 366                         }
 367                 }
 368
 369                 if (reserve_in_place) {
 370                         if (reserveable || bytes <= sizeof(uint32_t)) {
 371                                 fifo_state->using_bounce_buffer = false;
 372
 373                                 if (reserveable)
 374                                         iowrite32(bytes, fifo_mem +
 375                                                   SVGA_FIFO_RESERVED);
 376                                 return fifo_mem + (next_cmd >> 2);
 377                         } else {
 378                                 need_bounce = true;
 379                         }
 380                 }
 381
 382                 if (need_bounce) {
 383                         fifo_state->using_bounce_buffer = true;
 384                         if (bytes < fifo_state->static_buffer_size)
 385                                 return fifo_state->static_buffer;
 386                         else {
 387                                 fifo_state->dynamic_buffer = vmalloc(bytes);
 388                                 return fifo_state->dynamic_buffer;
 389                         }
 390                 }
 391         }
 392 out_err:
 393         fifo_state->reserved_size = 0;
 394         mutex_unlock(&fifo_state->fifo_mutex);
 395         return NULL;
 396 }
 397
 398 static void vmw_fifo_res_copy(struct vmw_fifo_state *fifo_state,
 399                               __le32 __iomem *fifo_mem,
 400                               uint32_t next_cmd,
 401                               uint32_t max, uint32_t min, uint32_t bytes)
 402 {
 403         uint32_t chunk_size = max - next_cmd;
 404         uint32_t rest;
 405         uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
 406             fifo_state->dynamic_buffer : fifo_state->static_buffer;
 407
 408         if (bytes < chunk_size)
 409                 chunk_size = bytes;
 410
 411         iowrite32(bytes, fifo_mem + SVGA_FIFO_RESERVED);
 412         mb();
 413         memcpy_toio(fifo_mem + (next_cmd >> 2), buffer, chunk_size);
 414         rest = bytes - chunk_size;
 415         if (rest)
 416                 memcpy_toio(fifo_mem + (min >> 2), buffer + (chunk_size >> 2),
 417                             rest);
 418 }
 419
 420 static void vmw_fifo_slow_copy(struct vmw_fifo_state *fifo_state,
 421                                __le32 __iomem *fifo_mem,
 422                                uint32_t next_cmd,
 423                                uint32_t max, uint32_t min, uint32_t bytes)
 424 {
 425         uint32_t *buffer = (fifo_state->dynamic_buffer != NULL) ?
 426             fifo_state->dynamic_buffer : fifo_state->static_buffer;
 427
 428         while (bytes > 0) {
 429                 iowrite32(*buffer++, fifo_mem + (next_cmd >> 2));
 430                 next_cmd += sizeof(uint32_t);
 431                 if (unlikely(next_cmd == max))
 432                         next_cmd = min;
 433                 mb();
 434                 iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
 435                 mb();
 436                 bytes -= sizeof(uint32_t);
 437         }
 438 }
 439
 440 void vmw_fifo_commit(struct vmw_private *dev_priv, uint32_t bytes)
 441 {
 442         struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
 443         __le32 __iomem *fifo_mem = dev_priv->mmio_virt;
 444         uint32_t next_cmd = ioread32(fifo_mem + SVGA_FIFO_NEXT_CMD);
 445         uint32_t max = ioread32(fifo_mem + SVGA_FIFO_MAX);
 446         uint32_t min = ioread32(fifo_mem + SVGA_FIFO_MIN);
 447         bool reserveable = fifo_state->capabilities & SVGA_FIFO_CAP_RESERVE;
 448
 449         BUG_ON((bytes & 3) != 0);
 450         BUG_ON(bytes > fifo_state->reserved_size);
 451
 452         fifo_state->reserved_size = 0;
 453
 454         if (fifo_state->using_bounce_buffer) {
 455                 if (reserveable)
 456                         vmw_fifo_res_copy(fifo_state, fifo_mem,
 457                                           next_cmd, max, min, bytes);
 458                 else
 459                         vmw_fifo_slow_copy(fifo_state, fifo_mem,
 460                                            next_cmd, max, min, bytes);
 461
 462                 if (fifo_state->dynamic_buffer) {
 463                         vfree(fifo_state->dynamic_buffer);
 464                         fifo_state->dynamic_buffer = NULL;
 465                 }
 466
 467         }
 468
 469         down_write(&fifo_state->rwsem);
 470         if (fifo_state->using_bounce_buffer || reserveable) {
 471                 next_cmd += bytes;
 472                 if (next_cmd >= max)
 473                         next_cmd -= max - min;
 474                 mb();
 475                 iowrite32(next_cmd, fifo_mem + SVGA_FIFO_NEXT_CMD);
 476         }
 477
 478         if (reserveable)
 479                 iowrite32(0, fifo_mem + SVGA_FIFO_RESERVED);
 480         mb();
 481         up_write(&fifo_state->rwsem);
 482         vmw_fifo_ping_host(dev_priv, SVGA_SYNC_GENERIC);
 483         mutex_unlock(&fifo_state->fifo_mutex);
 484 }
 485
 486 int vmw_fifo_send_fence(struct vmw_private *dev_priv, uint32_t *seqno)
 487 {
 488         struct vmw_fifo_state *fifo_state = &dev_priv->fifo;
 489         struct svga_fifo_cmd_fence *cmd_fence;
 490         void *fm;
 491         int ret = 0;
 492         uint32_t bytes = sizeof(__le32) + sizeof(*cmd_fence);
 493
 494         fm = vmw_fifo_reserve(dev_priv, bytes);
 495         if (unlikely(fm == NULL)) {
 496                 *seqno = atomic_read(&dev_priv->marker_seq);
 497                 ret = -ENOMEM;
 498                 (void)vmw_fallback_wait(dev_priv, false, true, *seqno,
 499                                         false, 3*HZ);
 500                 goto out_err;
 501         }
 502
 503         do {
 504                 *seqno = atomic_add_return(1, &dev_priv->marker_seq);
 505         } while (*seqno == 0);
 506
 507         if (!(fifo_state->capabilities & SVGA_FIFO_CAP_FENCE)) {
 508
 509                 /*
 510                  * Don't request hardware to send a fence. The
 511                  * waiting code in vmwgfx_irq.c will emulate this.
 512                  */
 513
 514                 vmw_fifo_commit(dev_priv, 0);
 515                 return 0;
 516         }
 517
 518         *(__le32 *) fm = cpu_to_le32(SVGA_CMD_FENCE);
 519         cmd_fence = (struct svga_fifo_cmd_fence *)
 520             ((unsigned long)fm + sizeof(__le32));
 521
 522         iowrite32(*seqno, &cmd_fence->fence);
 523         vmw_fifo_commit(dev_priv, bytes);
 524         (void) vmw_marker_push(&fifo_state->marker_queue, *seqno);
 525         vmw_update_seqno(dev_priv, fifo_state);
 526
 527 out_err:
 528         return ret;
 529 }
 530
 531 /**
 532  * vmw_fifo_emit_dummy_legacy_query - emits a dummy query to the fifo using
 533  * legacy query commands.
 534  *
 535  * @dev_priv: The device private structure.
 536  * @cid: The hardware context id used for the query.
 537  *
 538  * See the vmw_fifo_emit_dummy_query documentation.
 539  */
 540 static int vmw_fifo_emit_dummy_legacy_query(struct vmw_private *dev_priv,
 541                                             uint32_t cid)
 542 {
 543         /*
 544          * A query wait without a preceding query end will
 545          * actually finish all queries for this cid
 546          * without writing to the query result structure.
 547          */
 548
 549         struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
 550         struct {
 551                 SVGA3dCmdHeader header;
 552                 SVGA3dCmdWaitForQuery body;
 553         } *cmd;
 554
 555         cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
 556
 557         if (unlikely(cmd == NULL)) {
 558                 DRM_ERROR("Out of fifo space for dummy query.\n");
 559                 return -ENOMEM;
 560         }
 561
 562         cmd->header.id = SVGA_3D_CMD_WAIT_FOR_QUERY;
 563         cmd->header.size = sizeof(cmd->body);
 564         cmd->body.cid = cid;
 565         cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;
 566
 567         if (bo->mem.mem_type == TTM_PL_VRAM) {
 568                 cmd->body.guestResult.gmrId = SVGA_GMR_FRAMEBUFFER;
 569                 cmd->body.guestResult.offset = bo->offset;
 570         } else {
 571                 cmd->body.guestResult.gmrId = bo->mem.start;
 572                 cmd->body.guestResult.offset = 0;
 573         }
 574
 575         vmw_fifo_commit(dev_priv, sizeof(*cmd));
 576
 577         return 0;
 578 }
 579
 580 /**
 581  * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using
 582  * guest-backed resource query commands.
 583  *
 584  * @dev_priv: The device private structure.
 585  * @cid: The hardware context id used for the query.
 586  *
 587  * See the vmw_fifo_emit_dummy_query documentation.
 588  */
 589 static int vmw_fifo_emit_dummy_gb_query(struct vmw_private *dev_priv,
 590                                         uint32_t cid)
 591 {
 592         /*
 593          * A query wait without a preceding query end will
 594          * actually finish all queries for this cid
 595          * without writing to the query result structure.
 596          */
 597
 598         struct ttm_buffer_object *bo = dev_priv->dummy_query_bo;
 599         struct {
 600                 SVGA3dCmdHeader header;
 601                 SVGA3dCmdWaitForGBQuery body;
 602         } *cmd;
 603
 604         cmd = vmw_fifo_reserve(dev_priv, sizeof(*cmd));
 605
 606         if (unlikely(cmd == NULL)) {
 607                 DRM_ERROR("Out of fifo space for dummy query.\n");
 608                 return -ENOMEM;
 609         }
 610
 611         cmd->header.id = SVGA_3D_CMD_WAIT_FOR_GB_QUERY;
 612         cmd->header.size = sizeof(cmd->body);
 613         cmd->body.cid = cid;
 614         cmd->body.type = SVGA3D_QUERYTYPE_OCCLUSION;
 615         BUG_ON(bo->mem.mem_type != VMW_PL_MOB);
 616         cmd->body.mobid = bo->mem.start;
 617         cmd->body.offset = 0;
 618
 619         vmw_fifo_commit(dev_priv, sizeof(*cmd));
 620
 621         return 0;
 622 }
 623
 624
 625 /**
 626  * vmw_fifo_emit_dummy_gb_query - emits a dummy query to the fifo using
 627  * appropriate resource query commands.
 628  *
 629  * @dev_priv: The device private structure.
 630  * @cid: The hardware context id used for the query.
 631  *
 632  * This function is used to emit a dummy occlusion query with
 633  * no primitives rendered between query begin and query end.
 634  * It's used to provide a query barrier, in order to know that when
 635  * this query is finished, all preceding queries are also finished.
 636  *
 637  * A Query results structure should have been initialized at the start
 638  * of the dev_priv->dummy_query_bo buffer object. And that buffer object
 639  * must also be either reserved or pinned when this function is called.
 640  *
 641  * Returns -ENOMEM on failure to reserve fifo space.
 642  */
 643 int vmw_fifo_emit_dummy_query(struct vmw_private *dev_priv,
 644                               uint32_t cid)
 645 {
 646         if (dev_priv->has_mob)
 647                 return vmw_fifo_emit_dummy_gb_query(dev_priv, cid);
 648
 649         return vmw_fifo_emit_dummy_legacy_query(dev_priv, cid);
 650 }