2 * Copyright (C) 2012 Avionic Design GmbH
3 * Copyright (C) 2012 NVIDIA CORPORATION. All rights reserved.
5 * This program is free software; you can redistribute it and/or modify
6 * it under the terms of the GNU General Public License version 2 as
7 * published by the Free Software Foundation.
10 #include <linux/clk.h>
11 #include <linux/clk/tegra.h>
12 #include <linux/debugfs.h>
13 #include <linux/hdmi.h>
14 #include <linux/regulator/consumer.h>
16 #include "host1x_client.h"
22 struct tegra_drm_client client;
23 struct tegra_output output;
26 struct regulator *vdd;
27 struct regulator *pll;
32 struct clk *clk_parent;
35 unsigned int audio_source;
36 unsigned int audio_freq;
40 struct drm_info_list *debugfs_files;
41 struct drm_minor *minor;
42 struct dentry *debugfs;
45 static inline struct tegra_hdmi *
46 tegra_drm_client_to_hdmi(struct tegra_drm_client *client)
48 return container_of(client, struct tegra_hdmi, client);
51 static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
53 return container_of(output, struct tegra_hdmi, output);
56 #define HDMI_AUDIOCLK_FREQ 216000000
57 #define HDMI_REKEY_DEFAULT 56
65 static inline unsigned long tegra_hdmi_readl(struct tegra_hdmi *hdmi,
68 return readl(hdmi->regs + (reg << 2));
71 static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, unsigned long val,
74 writel(val, hdmi->regs + (reg << 2));
77 struct tegra_hdmi_audio_config {
84 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
85 { 25200000, 4096, 25200, 24000 },
86 { 27000000, 4096, 27000, 24000 },
87 { 74250000, 4096, 74250, 24000 },
88 { 148500000, 4096, 148500, 24000 },
92 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
93 { 25200000, 5880, 26250, 25000 },
94 { 27000000, 5880, 28125, 25000 },
95 { 74250000, 4704, 61875, 20000 },
96 { 148500000, 4704, 123750, 20000 },
100 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
101 { 25200000, 6144, 25200, 24000 },
102 { 27000000, 6144, 27000, 24000 },
103 { 74250000, 6144, 74250, 24000 },
104 { 148500000, 6144, 148500, 24000 },
108 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = {
109 { 25200000, 11760, 26250, 25000 },
110 { 27000000, 11760, 28125, 25000 },
111 { 74250000, 9408, 61875, 20000 },
112 { 148500000, 9408, 123750, 20000 },
116 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = {
117 { 25200000, 12288, 25200, 24000 },
118 { 27000000, 12288, 27000, 24000 },
119 { 74250000, 12288, 74250, 24000 },
120 { 148500000, 12288, 148500, 24000 },
124 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = {
125 { 25200000, 23520, 26250, 25000 },
126 { 27000000, 23520, 28125, 25000 },
127 { 74250000, 18816, 61875, 20000 },
128 { 148500000, 18816, 123750, 20000 },
132 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = {
133 { 25200000, 24576, 25200, 24000 },
134 { 27000000, 24576, 27000, 24000 },
135 { 74250000, 24576, 74250, 24000 },
136 { 148500000, 24576, 148500, 24000 },
148 static const struct tmds_config tegra2_tmds_config[] = {
149 { /* slow pixel clock modes */
151 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
152 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
153 SOR_PLL_TX_REG_LOAD(3),
154 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
155 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
156 PE_CURRENT1(PE_CURRENT_0_0_mA) |
157 PE_CURRENT2(PE_CURRENT_0_0_mA) |
158 PE_CURRENT3(PE_CURRENT_0_0_mA),
159 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
160 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
161 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
162 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
164 { /* high pixel clock modes */
166 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
167 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
168 SOR_PLL_TX_REG_LOAD(3),
169 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
170 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
171 PE_CURRENT1(PE_CURRENT_6_0_mA) |
172 PE_CURRENT2(PE_CURRENT_6_0_mA) |
173 PE_CURRENT3(PE_CURRENT_6_0_mA),
174 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
175 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
176 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
177 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
181 static const struct tmds_config tegra3_tmds_config[] = {
184 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
185 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
186 SOR_PLL_TX_REG_LOAD(0),
187 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
188 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
189 PE_CURRENT1(PE_CURRENT_0_0_mA) |
190 PE_CURRENT2(PE_CURRENT_0_0_mA) |
191 PE_CURRENT3(PE_CURRENT_0_0_mA),
192 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
193 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
194 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
195 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
196 }, { /* 720p modes */
198 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
199 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
200 SOR_PLL_TX_REG_LOAD(0),
201 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
202 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
203 PE_CURRENT1(PE_CURRENT_5_0_mA) |
204 PE_CURRENT2(PE_CURRENT_5_0_mA) |
205 PE_CURRENT3(PE_CURRENT_5_0_mA),
206 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
207 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
208 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
209 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
210 }, { /* 1080p modes */
212 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
213 SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
214 SOR_PLL_TX_REG_LOAD(0),
215 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
216 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
217 PE_CURRENT1(PE_CURRENT_5_0_mA) |
218 PE_CURRENT2(PE_CURRENT_5_0_mA) |
219 PE_CURRENT3(PE_CURRENT_5_0_mA),
220 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
221 DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
222 DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
223 DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
227 static const struct tegra_hdmi_audio_config *
228 tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pclk)
230 const struct tegra_hdmi_audio_config *table;
232 switch (audio_freq) {
234 table = tegra_hdmi_audio_32k;
238 table = tegra_hdmi_audio_44_1k;
242 table = tegra_hdmi_audio_48k;
246 table = tegra_hdmi_audio_88_2k;
250 table = tegra_hdmi_audio_96k;
254 table = tegra_hdmi_audio_176_4k;
258 table = tegra_hdmi_audio_192k;
265 while (table->pclk) {
266 if (table->pclk == pclk)
275 static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
277 const unsigned int freqs[] = {
278 32000, 44100, 48000, 88200, 96000, 176400, 192000
282 for (i = 0; i < ARRAY_SIZE(freqs); i++) {
283 unsigned int f = freqs[i];
284 unsigned int eight_half;
295 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
296 value = AUDIO_FS_LOW(eight_half - delta) |
297 AUDIO_FS_HIGH(eight_half + delta);
298 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
302 static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi, unsigned int pclk)
304 struct device_node *node = hdmi->dev->of_node;
305 const struct tegra_hdmi_audio_config *config;
306 unsigned int offset = 0;
309 switch (hdmi->audio_source) {
311 value = AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
315 value = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
319 value = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
323 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
324 value |= AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
325 AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
326 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
328 value |= AUDIO_CNTRL0_INJECT_NULLSMPL;
329 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
331 value = AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
332 AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
333 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
336 config = tegra_hdmi_get_audio_config(hdmi->audio_freq, pclk);
338 dev_err(hdmi->dev, "cannot set audio to %u at %u pclk\n",
339 hdmi->audio_freq, pclk);
343 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
345 value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
346 AUDIO_N_VALUE(config->n - 1);
347 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
349 tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
350 HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
352 value = ACR_SUBPACK_CTS(config->cts);
353 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
355 value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
356 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
358 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
359 value &= ~AUDIO_N_RESETF;
360 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
362 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
363 switch (hdmi->audio_freq) {
365 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320;
369 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441;
373 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480;
377 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882;
381 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960;
385 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764;
389 offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920;
393 tegra_hdmi_writel(hdmi, config->aval, offset);
396 tegra_hdmi_setup_audio_fs_tables(hdmi);
401 static inline unsigned long tegra_hdmi_subpack(const u8 *ptr, size_t size)
403 unsigned long value = 0;
406 for (i = size; i > 0; i--)
407 value = (value << 8) | ptr[i - 1];
412 static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data,
415 const u8 *ptr = data;
416 unsigned long offset;
421 case HDMI_INFOFRAME_TYPE_AVI:
422 offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER;
425 case HDMI_INFOFRAME_TYPE_AUDIO:
426 offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER;
429 case HDMI_INFOFRAME_TYPE_VENDOR:
430 offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER;
434 dev_err(hdmi->dev, "unsupported infoframe type: %02x\n",
439 value = INFOFRAME_HEADER_TYPE(ptr[0]) |
440 INFOFRAME_HEADER_VERSION(ptr[1]) |
441 INFOFRAME_HEADER_LEN(ptr[2]);
442 tegra_hdmi_writel(hdmi, value, offset);
446 * Each subpack contains 7 bytes, divided into:
447 * - subpack_low: bytes 0 - 3
448 * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
450 for (i = 3, j = 0; i < size; i += 7, j += 8) {
451 size_t rem = size - i, num = min_t(size_t, rem, 4);
453 value = tegra_hdmi_subpack(&ptr[i], num);
454 tegra_hdmi_writel(hdmi, value, offset++);
456 num = min_t(size_t, rem - num, 3);
458 value = tegra_hdmi_subpack(&ptr[i + 4], num);
459 tegra_hdmi_writel(hdmi, value, offset++);
463 static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
464 struct drm_display_mode *mode)
466 struct hdmi_avi_infoframe frame;
471 tegra_hdmi_writel(hdmi, 0,
472 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
476 err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
478 dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err);
482 err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
484 dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err);
488 tegra_hdmi_write_infopack(hdmi, buffer, err);
490 tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
491 HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
494 static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
496 struct hdmi_audio_infoframe frame;
501 tegra_hdmi_writel(hdmi, 0,
502 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
506 err = hdmi_audio_infoframe_init(&frame);
508 dev_err(hdmi->dev, "failed to initialize audio infoframe: %d\n",
515 err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
517 dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n",
523 * The audio infoframe has only one set of subpack registers, so the
524 * infoframe needs to be truncated. One set of subpack registers can
525 * contain 7 bytes. Including the 3 byte header only the first 10
526 * bytes can be programmed.
528 tegra_hdmi_write_infopack(hdmi, buffer, min(10, err));
530 tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
531 HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
534 static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
536 struct hdmi_vendor_infoframe frame;
542 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
543 value &= ~GENERIC_CTRL_ENABLE;
544 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
548 hdmi_vendor_infoframe_init(&frame);
549 frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING;
551 err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
553 dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n",
558 tegra_hdmi_write_infopack(hdmi, buffer, err);
560 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
561 value |= GENERIC_CTRL_ENABLE;
562 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
565 static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
566 const struct tmds_config *tmds)
570 tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
571 tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
572 tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
574 value = tmds->drive_current | DRIVE_CURRENT_FUSE_OVERRIDE;
575 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
578 static int tegra_output_hdmi_enable(struct tegra_output *output)
580 unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
581 struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
582 struct drm_display_mode *mode = &dc->base.mode;
583 struct tegra_hdmi *hdmi = to_hdmi(output);
584 struct device_node *node = hdmi->dev->of_node;
585 unsigned int pulse_start, div82, pclk;
586 const struct tmds_config *tmds;
587 unsigned int num_tmds;
592 pclk = mode->clock * 1000;
593 h_sync_width = mode->hsync_end - mode->hsync_start;
594 h_back_porch = mode->htotal - mode->hsync_end;
595 h_front_porch = mode->hsync_start - mode->hdisplay;
597 err = regulator_enable(hdmi->vdd);
599 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
603 err = regulator_enable(hdmi->pll);
605 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
610 * This assumes that the display controller will divide its parent
611 * clock by 2 to generate the pixel clock.
613 err = tegra_output_setup_clock(output, hdmi->clk, pclk * 2);
615 dev_err(hdmi->dev, "failed to setup clock: %d\n", err);
619 err = clk_set_rate(hdmi->clk, pclk);
623 err = clk_enable(hdmi->clk);
625 dev_err(hdmi->dev, "failed to enable clock: %d\n", err);
629 tegra_periph_reset_assert(hdmi->clk);
630 usleep_range(1000, 2000);
631 tegra_periph_reset_deassert(hdmi->clk);
633 tegra_dc_writel(dc, VSYNC_H_POSITION(1),
634 DC_DISP_DISP_TIMING_OPTIONS);
635 tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE888,
636 DC_DISP_DISP_COLOR_CONTROL);
638 /* video_preamble uses h_pulse2 */
639 pulse_start = 1 + h_sync_width + h_back_porch - 10;
641 tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
643 value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
645 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
647 value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
648 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
650 value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
652 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
655 value = HDMI_SRC_DISPLAYB;
657 value = HDMI_SRC_DISPLAYA;
659 if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
660 (mode->vdisplay == 576)))
661 tegra_hdmi_writel(hdmi,
662 value | ARM_VIDEO_RANGE_FULL,
663 HDMI_NV_PDISP_INPUT_CONTROL);
665 tegra_hdmi_writel(hdmi,
666 value | ARM_VIDEO_RANGE_LIMITED,
667 HDMI_NV_PDISP_INPUT_CONTROL);
669 div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
670 value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
671 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
674 err = tegra_hdmi_setup_audio(hdmi, pclk);
679 if (of_device_is_compatible(node, "nvidia,tegra20-hdmi")) {
681 * TODO: add ELD support
685 rekey = HDMI_REKEY_DEFAULT;
686 value = HDMI_CTRL_REKEY(rekey);
687 value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
688 h_front_porch - rekey - 18) / 32);
691 value |= HDMI_CTRL_ENABLE;
693 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
696 tegra_hdmi_writel(hdmi, 0x0,
697 HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
699 tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO,
700 HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
702 tegra_hdmi_setup_avi_infoframe(hdmi, mode);
703 tegra_hdmi_setup_audio_infoframe(hdmi);
704 tegra_hdmi_setup_stereo_infoframe(hdmi);
707 if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
708 num_tmds = ARRAY_SIZE(tegra3_tmds_config);
709 tmds = tegra3_tmds_config;
711 num_tmds = ARRAY_SIZE(tegra2_tmds_config);
712 tmds = tegra2_tmds_config;
715 for (i = 0; i < num_tmds; i++) {
716 if (pclk <= tmds[i].pclk) {
717 tegra_hdmi_setup_tmds(hdmi, &tmds[i]);
722 tegra_hdmi_writel(hdmi,
723 SOR_SEQ_CTL_PU_PC(0) |
724 SOR_SEQ_PU_PC_ALT(0) |
726 SOR_SEQ_PD_PC_ALT(8),
727 HDMI_NV_PDISP_SOR_SEQ_CTL);
729 value = SOR_SEQ_INST_WAIT_TIME(1) |
730 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
732 SOR_SEQ_INST_PIN_A_LOW |
733 SOR_SEQ_INST_PIN_B_LOW |
734 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
736 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
737 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
740 value &= ~SOR_CSTM_ROTCLK(~0);
741 value |= SOR_CSTM_ROTCLK(2);
742 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
744 tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
745 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
746 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
749 tegra_hdmi_writel(hdmi,
750 SOR_PWR_NORMAL_STATE_PU |
751 SOR_PWR_NORMAL_START_NORMAL |
752 SOR_PWR_SAFE_STATE_PD |
753 SOR_PWR_SETTING_NEW_TRIGGER,
754 HDMI_NV_PDISP_SOR_PWR);
755 tegra_hdmi_writel(hdmi,
756 SOR_PWR_NORMAL_STATE_PU |
757 SOR_PWR_NORMAL_START_NORMAL |
758 SOR_PWR_SAFE_STATE_PD |
759 SOR_PWR_SETTING_NEW_DONE,
760 HDMI_NV_PDISP_SOR_PWR);
763 BUG_ON(--retries < 0);
764 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
765 } while (value & SOR_PWR_SETTING_NEW_PENDING);
767 value = SOR_STATE_ASY_CRCMODE_COMPLETE |
768 SOR_STATE_ASY_OWNER_HEAD0 |
769 SOR_STATE_ASY_SUBOWNER_BOTH |
770 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
771 SOR_STATE_ASY_DEPOL_POS;
773 /* setup sync polarities */
774 if (mode->flags & DRM_MODE_FLAG_PHSYNC)
775 value |= SOR_STATE_ASY_HSYNCPOL_POS;
777 if (mode->flags & DRM_MODE_FLAG_NHSYNC)
778 value |= SOR_STATE_ASY_HSYNCPOL_NEG;
780 if (mode->flags & DRM_MODE_FLAG_PVSYNC)
781 value |= SOR_STATE_ASY_VSYNCPOL_POS;
783 if (mode->flags & DRM_MODE_FLAG_NVSYNC)
784 value |= SOR_STATE_ASY_VSYNCPOL_NEG;
786 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
788 value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
789 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
791 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
792 tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
793 tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
794 HDMI_NV_PDISP_SOR_STATE1);
795 tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
797 tegra_dc_writel(dc, HDMI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
799 value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
800 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
801 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
803 value = DISP_CTRL_MODE_C_DISPLAY;
804 tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
806 tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
807 tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
809 /* TODO: add HDCP support */
814 static int tegra_output_hdmi_disable(struct tegra_output *output)
816 struct tegra_hdmi *hdmi = to_hdmi(output);
818 tegra_periph_reset_assert(hdmi->clk);
819 clk_disable(hdmi->clk);
820 regulator_disable(hdmi->pll);
821 regulator_disable(hdmi->vdd);
826 static int tegra_output_hdmi_setup_clock(struct tegra_output *output,
827 struct clk *clk, unsigned long pclk)
829 struct tegra_hdmi *hdmi = to_hdmi(output);
833 err = clk_set_parent(clk, hdmi->clk_parent);
835 dev_err(output->dev, "failed to set parent: %d\n", err);
839 base = clk_get_parent(hdmi->clk_parent);
842 * This assumes that the parent clock is pll_d_out0 or pll_d2_out
843 * respectively, each of which divides the base pll_d by 2.
845 err = clk_set_rate(base, pclk * 2);
848 "failed to set base clock rate to %lu Hz\n",
854 static int tegra_output_hdmi_check_mode(struct tegra_output *output,
855 struct drm_display_mode *mode,
856 enum drm_mode_status *status)
858 struct tegra_hdmi *hdmi = to_hdmi(output);
859 unsigned long pclk = mode->clock * 1000;
863 parent = clk_get_parent(hdmi->clk_parent);
865 err = clk_round_rate(parent, pclk * 4);
867 *status = MODE_NOCLOCK;
874 static const struct tegra_output_ops hdmi_ops = {
875 .enable = tegra_output_hdmi_enable,
876 .disable = tegra_output_hdmi_disable,
877 .setup_clock = tegra_output_hdmi_setup_clock,
878 .check_mode = tegra_output_hdmi_check_mode,
881 static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
883 struct drm_info_node *node = s->private;
884 struct tegra_hdmi *hdmi = node->info_ent->data;
887 err = clk_enable(hdmi->clk);
891 #define DUMP_REG(name) \
892 seq_printf(s, "%-56s %#05x %08lx\n", #name, name, \
893 tegra_hdmi_readl(hdmi, name))
895 DUMP_REG(HDMI_CTXSW);
896 DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
897 DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
898 DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
899 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
900 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
901 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
902 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
903 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
904 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
905 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
906 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
907 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
908 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
909 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
910 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
911 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
912 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
913 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
914 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
915 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
916 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
917 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
918 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
919 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
920 DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
921 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
922 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
923 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
924 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
925 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
926 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
927 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
928 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
929 DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
930 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
931 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
932 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
933 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
934 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
935 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
936 DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
937 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
938 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
939 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
940 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
941 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
942 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
943 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
944 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
945 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
946 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
947 DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
948 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
949 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
950 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
951 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
952 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
953 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
954 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
955 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
956 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
957 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
958 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
959 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
960 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
961 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
962 DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
963 DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
964 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
965 DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
966 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
967 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
968 DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
969 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
970 DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
971 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
972 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
973 DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
974 DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
975 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
976 DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
977 DUMP_REG(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL);
978 DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
979 DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
980 DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
981 DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
982 DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
983 DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
984 DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
985 DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
986 DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
987 DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
988 DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
989 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
990 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(0));
991 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(1));
992 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(2));
993 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(3));
994 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(4));
995 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(5));
996 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(6));
997 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(7));
998 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(8));
999 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(9));
1000 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(10));
1001 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(11));
1002 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(12));
1003 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(13));
1004 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(14));
1005 DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(15));
1006 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
1007 DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
1008 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
1009 DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
1010 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
1011 DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
1012 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
1013 DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
1014 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
1015 DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
1016 DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
1017 DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
1018 DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1019 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
1020 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
1021 DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
1022 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
1023 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
1024 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
1025 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
1026 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
1027 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
1028 DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
1029 DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
1030 DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
1031 DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
1032 DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
1033 DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
1034 DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
1035 DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
1036 DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
1037 DUMP_REG(HDMI_NV_PDISP_SCRATCH);
1038 DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
1039 DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
1040 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
1041 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
1042 DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
1043 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
1044 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
1045 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
1046 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
1047 DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
1048 DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
1049 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
1050 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
1051 DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
1055 clk_disable(hdmi->clk);
1060 static struct drm_info_list debugfs_files[] = {
1061 { "regs", tegra_hdmi_show_regs, 0, NULL },
1064 static int tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi,
1065 struct drm_minor *minor)
1070 hdmi->debugfs = debugfs_create_dir("hdmi", minor->debugfs_root);
1074 hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1076 if (!hdmi->debugfs_files) {
1081 for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1082 hdmi->debugfs_files[i].data = hdmi;
1084 err = drm_debugfs_create_files(hdmi->debugfs_files,
1085 ARRAY_SIZE(debugfs_files),
1086 hdmi->debugfs, minor);
1090 hdmi->minor = minor;
1095 kfree(hdmi->debugfs_files);
1096 hdmi->debugfs_files = NULL;
1098 debugfs_remove(hdmi->debugfs);
1099 hdmi->debugfs = NULL;
1104 static int tegra_hdmi_debugfs_exit(struct tegra_hdmi *hdmi)
1106 drm_debugfs_remove_files(hdmi->debugfs_files, ARRAY_SIZE(debugfs_files),
1110 kfree(hdmi->debugfs_files);
1111 hdmi->debugfs_files = NULL;
1113 debugfs_remove(hdmi->debugfs);
1114 hdmi->debugfs = NULL;
1119 static int tegra_hdmi_init(struct host1x_client *client)
1121 struct tegra_drm_client *drm = to_tegra_drm_client(client);
1122 struct tegra_hdmi *hdmi = tegra_drm_client_to_hdmi(drm);
1125 hdmi->output.type = TEGRA_OUTPUT_HDMI;
1126 hdmi->output.dev = client->dev;
1127 hdmi->output.ops = &hdmi_ops;
1129 err = tegra_output_init(drm->drm, &hdmi->output);
1131 dev_err(client->dev, "output setup failed: %d\n", err);
1135 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1136 err = tegra_hdmi_debugfs_init(hdmi, drm->drm->primary);
1138 dev_err(client->dev, "debugfs setup failed: %d\n", err);
1144 static int tegra_hdmi_exit(struct host1x_client *client)
1146 struct tegra_drm_client *drm = to_tegra_drm_client(client);
1147 struct tegra_hdmi *hdmi = tegra_drm_client_to_hdmi(drm);
1150 if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1151 err = tegra_hdmi_debugfs_exit(hdmi);
1153 dev_err(client->dev, "debugfs cleanup failed: %d\n",
1157 err = tegra_output_disable(&hdmi->output);
1159 dev_err(client->dev, "output failed to disable: %d\n", err);
1163 err = tegra_output_exit(&hdmi->output);
1165 dev_err(client->dev, "output cleanup failed: %d\n", err);
1172 static const struct host1x_client_ops hdmi_client_ops = {
1173 .init = tegra_hdmi_init,
1174 .exit = tegra_hdmi_exit,
1177 static int tegra_hdmi_probe(struct platform_device *pdev)
1179 struct tegra_drm *tegra = host1x_get_drm_data(pdev->dev.parent);
1180 struct tegra_hdmi *hdmi;
1181 struct resource *regs;
1184 hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1188 hdmi->dev = &pdev->dev;
1189 hdmi->audio_source = AUTO;
1190 hdmi->audio_freq = 44100;
1191 hdmi->stereo = false;
1194 hdmi->clk = devm_clk_get(&pdev->dev, NULL);
1195 if (IS_ERR(hdmi->clk)) {
1196 dev_err(&pdev->dev, "failed to get clock\n");
1197 return PTR_ERR(hdmi->clk);
1200 err = clk_prepare(hdmi->clk);
1204 hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1205 if (IS_ERR(hdmi->clk_parent))
1206 return PTR_ERR(hdmi->clk_parent);
1208 err = clk_prepare(hdmi->clk_parent);
1212 err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
1214 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
1218 hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
1219 if (IS_ERR(hdmi->vdd)) {
1220 dev_err(&pdev->dev, "failed to get VDD regulator\n");
1221 return PTR_ERR(hdmi->vdd);
1224 hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
1225 if (IS_ERR(hdmi->pll)) {
1226 dev_err(&pdev->dev, "failed to get PLL regulator\n");
1227 return PTR_ERR(hdmi->pll);
1230 hdmi->output.dev = &pdev->dev;
1232 err = tegra_output_parse_dt(&hdmi->output);
1236 regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1240 hdmi->regs = devm_ioremap_resource(&pdev->dev, regs);
1241 if (IS_ERR(hdmi->regs))
1242 return PTR_ERR(hdmi->regs);
1244 err = platform_get_irq(pdev, 0);
1250 INIT_LIST_HEAD(&hdmi->client.base.list);
1251 hdmi->client.base.ops = &hdmi_client_ops;
1252 hdmi->client.base.dev = &pdev->dev;
1254 err = host1x_register_client(tegra, &hdmi->client.base);
1256 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1261 platform_set_drvdata(pdev, hdmi);
1266 static int tegra_hdmi_remove(struct platform_device *pdev)
1268 struct tegra_drm *tegra = host1x_get_drm_data(pdev->dev.parent);
1269 struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
1272 err = host1x_unregister_client(tegra, &hdmi->client.base);
1274 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1279 clk_unprepare(hdmi->clk_parent);
1280 clk_unprepare(hdmi->clk);
1285 static struct of_device_id tegra_hdmi_of_match[] = {
1286 { .compatible = "nvidia,tegra30-hdmi", },
1287 { .compatible = "nvidia,tegra20-hdmi", },
1291 struct platform_driver tegra_hdmi_driver = {
1293 .name = "tegra-hdmi",
1294 .owner = THIS_MODULE,
1295 .of_match_table = tegra_hdmi_of_match,
1297 .probe = tegra_hdmi_probe,
1298 .remove = tegra_hdmi_remove,