gpu: host1x: Expose syncpt and channel functionality
[firefly-linux-kernel-4.4.55.git] / drivers / gpu / host1x / drm / hdmi.c
1 /*
2  * Copyright (C) 2012 Avionic Design GmbH
3  * Copyright (C) 2012 NVIDIA CORPORATION.  All rights reserved.
4  *
5  * This program is free software; you can redistribute it and/or modify
6  * it under the terms of the GNU General Public License version 2 as
7  * published by the Free Software Foundation.
8  */
9
10 #include <linux/clk.h>
11 #include <linux/clk/tegra.h>
12 #include <linux/debugfs.h>
13 #include <linux/hdmi.h>
14 #include <linux/regulator/consumer.h>
15
16 #include "host1x_client.h"
17 #include "hdmi.h"
18 #include "drm.h"
19 #include "dc.h"
20
21 struct tegra_hdmi {
22         struct tegra_drm_client client;
23         struct tegra_output output;
24         struct device *dev;
25
26         struct regulator *vdd;
27         struct regulator *pll;
28
29         void __iomem *regs;
30         unsigned int irq;
31
32         struct clk *clk_parent;
33         struct clk *clk;
34
35         unsigned int audio_source;
36         unsigned int audio_freq;
37         bool stereo;
38         bool dvi;
39
40         struct drm_info_list *debugfs_files;
41         struct drm_minor *minor;
42         struct dentry *debugfs;
43 };
44
45 static inline struct tegra_hdmi *
46 tegra_drm_client_to_hdmi(struct tegra_drm_client *client)
47 {
48         return container_of(client, struct tegra_hdmi, client);
49 }
50
51 static inline struct tegra_hdmi *to_hdmi(struct tegra_output *output)
52 {
53         return container_of(output, struct tegra_hdmi, output);
54 }
55
56 #define HDMI_AUDIOCLK_FREQ 216000000
57 #define HDMI_REKEY_DEFAULT 56
58
59 enum {
60         AUTO = 0,
61         SPDIF,
62         HDA,
63 };
64
65 static inline unsigned long tegra_hdmi_readl(struct tegra_hdmi *hdmi,
66                                              unsigned long reg)
67 {
68         return readl(hdmi->regs + (reg << 2));
69 }
70
71 static inline void tegra_hdmi_writel(struct tegra_hdmi *hdmi, unsigned long val,
72                                      unsigned long reg)
73 {
74         writel(val, hdmi->regs + (reg << 2));
75 }
76
77 struct tegra_hdmi_audio_config {
78         unsigned int pclk;
79         unsigned int n;
80         unsigned int cts;
81         unsigned int aval;
82 };
83
84 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_32k[] = {
85         {  25200000, 4096,  25200, 24000 },
86         {  27000000, 4096,  27000, 24000 },
87         {  74250000, 4096,  74250, 24000 },
88         { 148500000, 4096, 148500, 24000 },
89         {         0,    0,      0,     0 },
90 };
91
92 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_44_1k[] = {
93         {  25200000, 5880,  26250, 25000 },
94         {  27000000, 5880,  28125, 25000 },
95         {  74250000, 4704,  61875, 20000 },
96         { 148500000, 4704, 123750, 20000 },
97         {         0,    0,      0,     0 },
98 };
99
100 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_48k[] = {
101         {  25200000, 6144,  25200, 24000 },
102         {  27000000, 6144,  27000, 24000 },
103         {  74250000, 6144,  74250, 24000 },
104         { 148500000, 6144, 148500, 24000 },
105         {         0,    0,      0,     0 },
106 };
107
108 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_88_2k[] = {
109         {  25200000, 11760,  26250, 25000 },
110         {  27000000, 11760,  28125, 25000 },
111         {  74250000,  9408,  61875, 20000 },
112         { 148500000,  9408, 123750, 20000 },
113         {         0,     0,      0,     0 },
114 };
115
116 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_96k[] = {
117         {  25200000, 12288,  25200, 24000 },
118         {  27000000, 12288,  27000, 24000 },
119         {  74250000, 12288,  74250, 24000 },
120         { 148500000, 12288, 148500, 24000 },
121         {         0,     0,      0,     0 },
122 };
123
124 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_176_4k[] = {
125         {  25200000, 23520,  26250, 25000 },
126         {  27000000, 23520,  28125, 25000 },
127         {  74250000, 18816,  61875, 20000 },
128         { 148500000, 18816, 123750, 20000 },
129         {         0,     0,      0,     0 },
130 };
131
132 static const struct tegra_hdmi_audio_config tegra_hdmi_audio_192k[] = {
133         {  25200000, 24576,  25200, 24000 },
134         {  27000000, 24576,  27000, 24000 },
135         {  74250000, 24576,  74250, 24000 },
136         { 148500000, 24576, 148500, 24000 },
137         {         0,     0,      0,     0 },
138 };
139
140 struct tmds_config {
141         unsigned int pclk;
142         u32 pll0;
143         u32 pll1;
144         u32 pe_current;
145         u32 drive_current;
146 };
147
148 static const struct tmds_config tegra2_tmds_config[] = {
149         { /* slow pixel clock modes */
150                 .pclk = 27000000,
151                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
152                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
153                         SOR_PLL_TX_REG_LOAD(3),
154                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
155                 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
156                         PE_CURRENT1(PE_CURRENT_0_0_mA) |
157                         PE_CURRENT2(PE_CURRENT_0_0_mA) |
158                         PE_CURRENT3(PE_CURRENT_0_0_mA),
159                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
160                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
161                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
162                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
163         },
164         { /* high pixel clock modes */
165                 .pclk = UINT_MAX,
166                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
167                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
168                         SOR_PLL_TX_REG_LOAD(3),
169                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
170                 .pe_current = PE_CURRENT0(PE_CURRENT_6_0_mA) |
171                         PE_CURRENT1(PE_CURRENT_6_0_mA) |
172                         PE_CURRENT2(PE_CURRENT_6_0_mA) |
173                         PE_CURRENT3(PE_CURRENT_6_0_mA),
174                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_7_125_mA) |
175                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_7_125_mA) |
176                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_7_125_mA) |
177                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_7_125_mA),
178         },
179 };
180
181 static const struct tmds_config tegra3_tmds_config[] = {
182         { /* 480p modes */
183                 .pclk = 27000000,
184                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
185                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(0) |
186                         SOR_PLL_TX_REG_LOAD(0),
187                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE,
188                 .pe_current = PE_CURRENT0(PE_CURRENT_0_0_mA) |
189                         PE_CURRENT1(PE_CURRENT_0_0_mA) |
190                         PE_CURRENT2(PE_CURRENT_0_0_mA) |
191                         PE_CURRENT3(PE_CURRENT_0_0_mA),
192                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
193                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
194                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
195                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
196         }, { /* 720p modes */
197                 .pclk = 74250000,
198                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
199                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(1) |
200                         SOR_PLL_TX_REG_LOAD(0),
201                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
202                 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
203                         PE_CURRENT1(PE_CURRENT_5_0_mA) |
204                         PE_CURRENT2(PE_CURRENT_5_0_mA) |
205                         PE_CURRENT3(PE_CURRENT_5_0_mA),
206                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
207                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
208                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
209                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
210         }, { /* 1080p modes */
211                 .pclk = UINT_MAX,
212                 .pll0 = SOR_PLL_BG_V17_S(3) | SOR_PLL_ICHPMP(1) |
213                         SOR_PLL_RESISTORSEL | SOR_PLL_VCOCAP(3) |
214                         SOR_PLL_TX_REG_LOAD(0),
215                 .pll1 = SOR_PLL_TMDS_TERM_ENABLE | SOR_PLL_PE_EN,
216                 .pe_current = PE_CURRENT0(PE_CURRENT_5_0_mA) |
217                         PE_CURRENT1(PE_CURRENT_5_0_mA) |
218                         PE_CURRENT2(PE_CURRENT_5_0_mA) |
219                         PE_CURRENT3(PE_CURRENT_5_0_mA),
220                 .drive_current = DRIVE_CURRENT_LANE0(DRIVE_CURRENT_5_250_mA) |
221                         DRIVE_CURRENT_LANE1(DRIVE_CURRENT_5_250_mA) |
222                         DRIVE_CURRENT_LANE2(DRIVE_CURRENT_5_250_mA) |
223                         DRIVE_CURRENT_LANE3(DRIVE_CURRENT_5_250_mA),
224         },
225 };
226
227 static const struct tegra_hdmi_audio_config *
228 tegra_hdmi_get_audio_config(unsigned int audio_freq, unsigned int pclk)
229 {
230         const struct tegra_hdmi_audio_config *table;
231
232         switch (audio_freq) {
233         case 32000:
234                 table = tegra_hdmi_audio_32k;
235                 break;
236
237         case 44100:
238                 table = tegra_hdmi_audio_44_1k;
239                 break;
240
241         case 48000:
242                 table = tegra_hdmi_audio_48k;
243                 break;
244
245         case 88200:
246                 table = tegra_hdmi_audio_88_2k;
247                 break;
248
249         case 96000:
250                 table = tegra_hdmi_audio_96k;
251                 break;
252
253         case 176400:
254                 table = tegra_hdmi_audio_176_4k;
255                 break;
256
257         case 192000:
258                 table = tegra_hdmi_audio_192k;
259                 break;
260
261         default:
262                 return NULL;
263         }
264
265         while (table->pclk) {
266                 if (table->pclk == pclk)
267                         return table;
268
269                 table++;
270         }
271
272         return NULL;
273 }
274
275 static void tegra_hdmi_setup_audio_fs_tables(struct tegra_hdmi *hdmi)
276 {
277         const unsigned int freqs[] = {
278                 32000, 44100, 48000, 88200, 96000, 176400, 192000
279         };
280         unsigned int i;
281
282         for (i = 0; i < ARRAY_SIZE(freqs); i++) {
283                 unsigned int f = freqs[i];
284                 unsigned int eight_half;
285                 unsigned long value;
286                 unsigned int delta;
287
288                 if (f > 96000)
289                         delta = 2;
290                 else if (f > 480000)
291                         delta = 6;
292                 else
293                         delta = 9;
294
295                 eight_half = (8 * HDMI_AUDIOCLK_FREQ) / (f * 128);
296                 value = AUDIO_FS_LOW(eight_half - delta) |
297                         AUDIO_FS_HIGH(eight_half + delta);
298                 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_FS(i));
299         }
300 }
301
302 static int tegra_hdmi_setup_audio(struct tegra_hdmi *hdmi, unsigned int pclk)
303 {
304         struct device_node *node = hdmi->dev->of_node;
305         const struct tegra_hdmi_audio_config *config;
306         unsigned int offset = 0;
307         unsigned long value;
308
309         switch (hdmi->audio_source) {
310         case HDA:
311                 value = AUDIO_CNTRL0_SOURCE_SELECT_HDAL;
312                 break;
313
314         case SPDIF:
315                 value = AUDIO_CNTRL0_SOURCE_SELECT_SPDIF;
316                 break;
317
318         default:
319                 value = AUDIO_CNTRL0_SOURCE_SELECT_AUTO;
320                 break;
321         }
322
323         if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
324                 value |= AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
325                          AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
326                 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
327         } else {
328                 value |= AUDIO_CNTRL0_INJECT_NULLSMPL;
329                 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
330
331                 value = AUDIO_CNTRL0_ERROR_TOLERANCE(6) |
332                         AUDIO_CNTRL0_FRAMES_PER_BLOCK(0xc0);
333                 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_CNTRL0);
334         }
335
336         config = tegra_hdmi_get_audio_config(hdmi->audio_freq, pclk);
337         if (!config) {
338                 dev_err(hdmi->dev, "cannot set audio to %u at %u pclk\n",
339                         hdmi->audio_freq, pclk);
340                 return -EINVAL;
341         }
342
343         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_HDMI_ACR_CTRL);
344
345         value = AUDIO_N_RESETF | AUDIO_N_GENERATE_ALTERNATE |
346                 AUDIO_N_VALUE(config->n - 1);
347         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
348
349         tegra_hdmi_writel(hdmi, ACR_SUBPACK_N(config->n) | ACR_ENABLE,
350                           HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
351
352         value = ACR_SUBPACK_CTS(config->cts);
353         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
354
355         value = SPARE_HW_CTS | SPARE_FORCE_SW_CTS | SPARE_CTS_RESET_VAL(1);
356         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_SPARE);
357
358         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_AUDIO_N);
359         value &= ~AUDIO_N_RESETF;
360         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_AUDIO_N);
361
362         if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
363                 switch (hdmi->audio_freq) {
364                 case 32000:
365                         offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0320;
366                         break;
367
368                 case 44100:
369                         offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0441;
370                         break;
371
372                 case 48000:
373                         offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0480;
374                         break;
375
376                 case 88200:
377                         offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0882;
378                         break;
379
380                 case 96000:
381                         offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_0960;
382                         break;
383
384                 case 176400:
385                         offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1764;
386                         break;
387
388                 case 192000:
389                         offset = HDMI_NV_PDISP_SOR_AUDIO_AVAL_1920;
390                         break;
391                 }
392
393                 tegra_hdmi_writel(hdmi, config->aval, offset);
394         }
395
396         tegra_hdmi_setup_audio_fs_tables(hdmi);
397
398         return 0;
399 }
400
401 static inline unsigned long tegra_hdmi_subpack(const u8 *ptr, size_t size)
402 {
403         unsigned long value = 0;
404         size_t i;
405
406         for (i = size; i > 0; i--)
407                 value = (value << 8) | ptr[i - 1];
408
409         return value;
410 }
411
412 static void tegra_hdmi_write_infopack(struct tegra_hdmi *hdmi, const void *data,
413                                       size_t size)
414 {
415         const u8 *ptr = data;
416         unsigned long offset;
417         unsigned long value;
418         size_t i, j;
419
420         switch (ptr[0]) {
421         case HDMI_INFOFRAME_TYPE_AVI:
422                 offset = HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER;
423                 break;
424
425         case HDMI_INFOFRAME_TYPE_AUDIO:
426                 offset = HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER;
427                 break;
428
429         case HDMI_INFOFRAME_TYPE_VENDOR:
430                 offset = HDMI_NV_PDISP_HDMI_GENERIC_HEADER;
431                 break;
432
433         default:
434                 dev_err(hdmi->dev, "unsupported infoframe type: %02x\n",
435                         ptr[0]);
436                 return;
437         }
438
439         value = INFOFRAME_HEADER_TYPE(ptr[0]) |
440                 INFOFRAME_HEADER_VERSION(ptr[1]) |
441                 INFOFRAME_HEADER_LEN(ptr[2]);
442         tegra_hdmi_writel(hdmi, value, offset);
443         offset++;
444
445         /*
446          * Each subpack contains 7 bytes, divided into:
447          * - subpack_low: bytes 0 - 3
448          * - subpack_high: bytes 4 - 6 (with byte 7 padded to 0x00)
449          */
450         for (i = 3, j = 0; i < size; i += 7, j += 8) {
451                 size_t rem = size - i, num = min_t(size_t, rem, 4);
452
453                 value = tegra_hdmi_subpack(&ptr[i], num);
454                 tegra_hdmi_writel(hdmi, value, offset++);
455
456                 num = min_t(size_t, rem - num, 3);
457
458                 value = tegra_hdmi_subpack(&ptr[i + 4], num);
459                 tegra_hdmi_writel(hdmi, value, offset++);
460         }
461 }
462
463 static void tegra_hdmi_setup_avi_infoframe(struct tegra_hdmi *hdmi,
464                                            struct drm_display_mode *mode)
465 {
466         struct hdmi_avi_infoframe frame;
467         u8 buffer[17];
468         ssize_t err;
469
470         if (hdmi->dvi) {
471                 tegra_hdmi_writel(hdmi, 0,
472                                   HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
473                 return;
474         }
475
476         err = drm_hdmi_avi_infoframe_from_display_mode(&frame, mode);
477         if (err < 0) {
478                 dev_err(hdmi->dev, "failed to setup AVI infoframe: %zd\n", err);
479                 return;
480         }
481
482         err = hdmi_avi_infoframe_pack(&frame, buffer, sizeof(buffer));
483         if (err < 0) {
484                 dev_err(hdmi->dev, "failed to pack AVI infoframe: %zd\n", err);
485                 return;
486         }
487
488         tegra_hdmi_write_infopack(hdmi, buffer, err);
489
490         tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
491                           HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
492 }
493
494 static void tegra_hdmi_setup_audio_infoframe(struct tegra_hdmi *hdmi)
495 {
496         struct hdmi_audio_infoframe frame;
497         u8 buffer[14];
498         ssize_t err;
499
500         if (hdmi->dvi) {
501                 tegra_hdmi_writel(hdmi, 0,
502                                   HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
503                 return;
504         }
505
506         err = hdmi_audio_infoframe_init(&frame);
507         if (err < 0) {
508                 dev_err(hdmi->dev, "failed to initialize audio infoframe: %d\n",
509                         err);
510                 return;
511         }
512
513         frame.channels = 2;
514
515         err = hdmi_audio_infoframe_pack(&frame, buffer, sizeof(buffer));
516         if (err < 0) {
517                 dev_err(hdmi->dev, "failed to pack audio infoframe: %zd\n",
518                         err);
519                 return;
520         }
521
522         /*
523          * The audio infoframe has only one set of subpack registers, so the
524          * infoframe needs to be truncated. One set of subpack registers can
525          * contain 7 bytes. Including the 3 byte header only the first 10
526          * bytes can be programmed.
527          */
528         tegra_hdmi_write_infopack(hdmi, buffer, min(10, err));
529
530         tegra_hdmi_writel(hdmi, INFOFRAME_CTRL_ENABLE,
531                           HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
532 }
533
534 static void tegra_hdmi_setup_stereo_infoframe(struct tegra_hdmi *hdmi)
535 {
536         struct hdmi_vendor_infoframe frame;
537         unsigned long value;
538         u8 buffer[10];
539         ssize_t err;
540
541         if (!hdmi->stereo) {
542                 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
543                 value &= ~GENERIC_CTRL_ENABLE;
544                 tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
545                 return;
546         }
547
548         hdmi_vendor_infoframe_init(&frame);
549         frame.s3d_struct = HDMI_3D_STRUCTURE_FRAME_PACKING;
550
551         err = hdmi_vendor_infoframe_pack(&frame, buffer, sizeof(buffer));
552         if (err < 0) {
553                 dev_err(hdmi->dev, "failed to pack vendor infoframe: %zd\n",
554                         err);
555                 return;
556         }
557
558         tegra_hdmi_write_infopack(hdmi, buffer, err);
559
560         value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
561         value |= GENERIC_CTRL_ENABLE;
562         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
563 }
564
565 static void tegra_hdmi_setup_tmds(struct tegra_hdmi *hdmi,
566                                   const struct tmds_config *tmds)
567 {
568         unsigned long value;
569
570         tegra_hdmi_writel(hdmi, tmds->pll0, HDMI_NV_PDISP_SOR_PLL0);
571         tegra_hdmi_writel(hdmi, tmds->pll1, HDMI_NV_PDISP_SOR_PLL1);
572         tegra_hdmi_writel(hdmi, tmds->pe_current, HDMI_NV_PDISP_PE_CURRENT);
573
574         value = tmds->drive_current | DRIVE_CURRENT_FUSE_OVERRIDE;
575         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
576 }
577
578 static int tegra_output_hdmi_enable(struct tegra_output *output)
579 {
580         unsigned int h_sync_width, h_front_porch, h_back_porch, i, rekey;
581         struct tegra_dc *dc = to_tegra_dc(output->encoder.crtc);
582         struct drm_display_mode *mode = &dc->base.mode;
583         struct tegra_hdmi *hdmi = to_hdmi(output);
584         struct device_node *node = hdmi->dev->of_node;
585         unsigned int pulse_start, div82, pclk;
586         const struct tmds_config *tmds;
587         unsigned int num_tmds;
588         unsigned long value;
589         int retries = 1000;
590         int err;
591
592         pclk = mode->clock * 1000;
593         h_sync_width = mode->hsync_end - mode->hsync_start;
594         h_back_porch = mode->htotal - mode->hsync_end;
595         h_front_porch = mode->hsync_start - mode->hdisplay;
596
597         err = regulator_enable(hdmi->vdd);
598         if (err < 0) {
599                 dev_err(hdmi->dev, "failed to enable VDD regulator: %d\n", err);
600                 return err;
601         }
602
603         err = regulator_enable(hdmi->pll);
604         if (err < 0) {
605                 dev_err(hdmi->dev, "failed to enable PLL regulator: %d\n", err);
606                 return err;
607         }
608
609         /*
610          * This assumes that the display controller will divide its parent
611          * clock by 2 to generate the pixel clock.
612          */
613         err = tegra_output_setup_clock(output, hdmi->clk, pclk * 2);
614         if (err < 0) {
615                 dev_err(hdmi->dev, "failed to setup clock: %d\n", err);
616                 return err;
617         }
618
619         err = clk_set_rate(hdmi->clk, pclk);
620         if (err < 0)
621                 return err;
622
623         err = clk_enable(hdmi->clk);
624         if (err < 0) {
625                 dev_err(hdmi->dev, "failed to enable clock: %d\n", err);
626                 return err;
627         }
628
629         tegra_periph_reset_assert(hdmi->clk);
630         usleep_range(1000, 2000);
631         tegra_periph_reset_deassert(hdmi->clk);
632
633         tegra_dc_writel(dc, VSYNC_H_POSITION(1),
634                         DC_DISP_DISP_TIMING_OPTIONS);
635         tegra_dc_writel(dc, DITHER_CONTROL_DISABLE | BASE_COLOR_SIZE888,
636                         DC_DISP_DISP_COLOR_CONTROL);
637
638         /* video_preamble uses h_pulse2 */
639         pulse_start = 1 + h_sync_width + h_back_porch - 10;
640
641         tegra_dc_writel(dc, H_PULSE_2_ENABLE, DC_DISP_DISP_SIGNAL_OPTIONS0);
642
643         value = PULSE_MODE_NORMAL | PULSE_POLARITY_HIGH | PULSE_QUAL_VACTIVE |
644                 PULSE_LAST_END_A;
645         tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL);
646
647         value = PULSE_START(pulse_start) | PULSE_END(pulse_start + 8);
648         tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A);
649
650         value = VSYNC_WINDOW_END(0x210) | VSYNC_WINDOW_START(0x200) |
651                 VSYNC_WINDOW_ENABLE;
652         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
653
654         if (dc->pipe)
655                 value = HDMI_SRC_DISPLAYB;
656         else
657                 value = HDMI_SRC_DISPLAYA;
658
659         if ((mode->hdisplay == 720) && ((mode->vdisplay == 480) ||
660                                         (mode->vdisplay == 576)))
661                 tegra_hdmi_writel(hdmi,
662                                   value | ARM_VIDEO_RANGE_FULL,
663                                   HDMI_NV_PDISP_INPUT_CONTROL);
664         else
665                 tegra_hdmi_writel(hdmi,
666                                   value | ARM_VIDEO_RANGE_LIMITED,
667                                   HDMI_NV_PDISP_INPUT_CONTROL);
668
669         div82 = clk_get_rate(hdmi->clk) / 1000000 * 4;
670         value = SOR_REFCLK_DIV_INT(div82 >> 2) | SOR_REFCLK_DIV_FRAC(div82);
671         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_REFCLK);
672
673         if (!hdmi->dvi) {
674                 err = tegra_hdmi_setup_audio(hdmi, pclk);
675                 if (err < 0)
676                         hdmi->dvi = true;
677         }
678
679         if (of_device_is_compatible(node, "nvidia,tegra20-hdmi")) {
680                 /*
681                  * TODO: add ELD support
682                  */
683         }
684
685         rekey = HDMI_REKEY_DEFAULT;
686         value = HDMI_CTRL_REKEY(rekey);
687         value |= HDMI_CTRL_MAX_AC_PACKET((h_sync_width + h_back_porch +
688                                           h_front_porch - rekey - 18) / 32);
689
690         if (!hdmi->dvi)
691                 value |= HDMI_CTRL_ENABLE;
692
693         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_HDMI_CTRL);
694
695         if (hdmi->dvi)
696                 tegra_hdmi_writel(hdmi, 0x0,
697                                   HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
698         else
699                 tegra_hdmi_writel(hdmi, GENERIC_CTRL_AUDIO,
700                                   HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
701
702         tegra_hdmi_setup_avi_infoframe(hdmi, mode);
703         tegra_hdmi_setup_audio_infoframe(hdmi);
704         tegra_hdmi_setup_stereo_infoframe(hdmi);
705
706         /* TMDS CONFIG */
707         if (of_device_is_compatible(node, "nvidia,tegra30-hdmi")) {
708                 num_tmds = ARRAY_SIZE(tegra3_tmds_config);
709                 tmds = tegra3_tmds_config;
710         } else {
711                 num_tmds = ARRAY_SIZE(tegra2_tmds_config);
712                 tmds = tegra2_tmds_config;
713         }
714
715         for (i = 0; i < num_tmds; i++) {
716                 if (pclk <= tmds[i].pclk) {
717                         tegra_hdmi_setup_tmds(hdmi, &tmds[i]);
718                         break;
719                 }
720         }
721
722         tegra_hdmi_writel(hdmi,
723                           SOR_SEQ_CTL_PU_PC(0) |
724                           SOR_SEQ_PU_PC_ALT(0) |
725                           SOR_SEQ_PD_PC(8) |
726                           SOR_SEQ_PD_PC_ALT(8),
727                           HDMI_NV_PDISP_SOR_SEQ_CTL);
728
729         value = SOR_SEQ_INST_WAIT_TIME(1) |
730                 SOR_SEQ_INST_WAIT_UNITS_VSYNC |
731                 SOR_SEQ_INST_HALT |
732                 SOR_SEQ_INST_PIN_A_LOW |
733                 SOR_SEQ_INST_PIN_B_LOW |
734                 SOR_SEQ_INST_DRIVE_PWM_OUT_LO;
735
736         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(0));
737         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_SEQ_INST(8));
738
739         value = 0x1c800;
740         value &= ~SOR_CSTM_ROTCLK(~0);
741         value |= SOR_CSTM_ROTCLK(2);
742         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_CSTM);
743
744         tegra_dc_writel(dc, DISP_CTRL_MODE_STOP, DC_CMD_DISPLAY_COMMAND);
745         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
746         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
747
748         /* start SOR */
749         tegra_hdmi_writel(hdmi,
750                           SOR_PWR_NORMAL_STATE_PU |
751                           SOR_PWR_NORMAL_START_NORMAL |
752                           SOR_PWR_SAFE_STATE_PD |
753                           SOR_PWR_SETTING_NEW_TRIGGER,
754                           HDMI_NV_PDISP_SOR_PWR);
755         tegra_hdmi_writel(hdmi,
756                           SOR_PWR_NORMAL_STATE_PU |
757                           SOR_PWR_NORMAL_START_NORMAL |
758                           SOR_PWR_SAFE_STATE_PD |
759                           SOR_PWR_SETTING_NEW_DONE,
760                           HDMI_NV_PDISP_SOR_PWR);
761
762         do {
763                 BUG_ON(--retries < 0);
764                 value = tegra_hdmi_readl(hdmi, HDMI_NV_PDISP_SOR_PWR);
765         } while (value & SOR_PWR_SETTING_NEW_PENDING);
766
767         value = SOR_STATE_ASY_CRCMODE_COMPLETE |
768                 SOR_STATE_ASY_OWNER_HEAD0 |
769                 SOR_STATE_ASY_SUBOWNER_BOTH |
770                 SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A |
771                 SOR_STATE_ASY_DEPOL_POS;
772
773         /* setup sync polarities */
774         if (mode->flags & DRM_MODE_FLAG_PHSYNC)
775                 value |= SOR_STATE_ASY_HSYNCPOL_POS;
776
777         if (mode->flags & DRM_MODE_FLAG_NHSYNC)
778                 value |= SOR_STATE_ASY_HSYNCPOL_NEG;
779
780         if (mode->flags & DRM_MODE_FLAG_PVSYNC)
781                 value |= SOR_STATE_ASY_VSYNCPOL_POS;
782
783         if (mode->flags & DRM_MODE_FLAG_NVSYNC)
784                 value |= SOR_STATE_ASY_VSYNCPOL_NEG;
785
786         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE2);
787
788         value = SOR_STATE_ASY_HEAD_OPMODE_AWAKE | SOR_STATE_ASY_ORMODE_NORMAL;
789         tegra_hdmi_writel(hdmi, value, HDMI_NV_PDISP_SOR_STATE1);
790
791         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
792         tegra_hdmi_writel(hdmi, SOR_STATE_UPDATE, HDMI_NV_PDISP_SOR_STATE0);
793         tegra_hdmi_writel(hdmi, value | SOR_STATE_ATTACHED,
794                           HDMI_NV_PDISP_SOR_STATE1);
795         tegra_hdmi_writel(hdmi, 0, HDMI_NV_PDISP_SOR_STATE0);
796
797         tegra_dc_writel(dc, HDMI_ENABLE, DC_DISP_DISP_WIN_OPTIONS);
798
799         value = PW0_ENABLE | PW1_ENABLE | PW2_ENABLE | PW3_ENABLE |
800                 PW4_ENABLE | PM0_ENABLE | PM1_ENABLE;
801         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_POWER_CONTROL);
802
803         value = DISP_CTRL_MODE_C_DISPLAY;
804         tegra_dc_writel(dc, value, DC_CMD_DISPLAY_COMMAND);
805
806         tegra_dc_writel(dc, GENERAL_ACT_REQ << 8, DC_CMD_STATE_CONTROL);
807         tegra_dc_writel(dc, GENERAL_ACT_REQ, DC_CMD_STATE_CONTROL);
808
809         /* TODO: add HDCP support */
810
811         return 0;
812 }
813
814 static int tegra_output_hdmi_disable(struct tegra_output *output)
815 {
816         struct tegra_hdmi *hdmi = to_hdmi(output);
817
818         tegra_periph_reset_assert(hdmi->clk);
819         clk_disable(hdmi->clk);
820         regulator_disable(hdmi->pll);
821         regulator_disable(hdmi->vdd);
822
823         return 0;
824 }
825
826 static int tegra_output_hdmi_setup_clock(struct tegra_output *output,
827                                          struct clk *clk, unsigned long pclk)
828 {
829         struct tegra_hdmi *hdmi = to_hdmi(output);
830         struct clk *base;
831         int err;
832
833         err = clk_set_parent(clk, hdmi->clk_parent);
834         if (err < 0) {
835                 dev_err(output->dev, "failed to set parent: %d\n", err);
836                 return err;
837         }
838
839         base = clk_get_parent(hdmi->clk_parent);
840
841         /*
842          * This assumes that the parent clock is pll_d_out0 or pll_d2_out
843          * respectively, each of which divides the base pll_d by 2.
844          */
845         err = clk_set_rate(base, pclk * 2);
846         if (err < 0)
847                 dev_err(output->dev,
848                         "failed to set base clock rate to %lu Hz\n",
849                         pclk * 2);
850
851         return 0;
852 }
853
854 static int tegra_output_hdmi_check_mode(struct tegra_output *output,
855                                         struct drm_display_mode *mode,
856                                         enum drm_mode_status *status)
857 {
858         struct tegra_hdmi *hdmi = to_hdmi(output);
859         unsigned long pclk = mode->clock * 1000;
860         struct clk *parent;
861         long err;
862
863         parent = clk_get_parent(hdmi->clk_parent);
864
865         err = clk_round_rate(parent, pclk * 4);
866         if (err < 0)
867                 *status = MODE_NOCLOCK;
868         else
869                 *status = MODE_OK;
870
871         return 0;
872 }
873
874 static const struct tegra_output_ops hdmi_ops = {
875         .enable = tegra_output_hdmi_enable,
876         .disable = tegra_output_hdmi_disable,
877         .setup_clock = tegra_output_hdmi_setup_clock,
878         .check_mode = tegra_output_hdmi_check_mode,
879 };
880
881 static int tegra_hdmi_show_regs(struct seq_file *s, void *data)
882 {
883         struct drm_info_node *node = s->private;
884         struct tegra_hdmi *hdmi = node->info_ent->data;
885         int err;
886
887         err = clk_enable(hdmi->clk);
888         if (err)
889                 return err;
890
891 #define DUMP_REG(name)                                          \
892         seq_printf(s, "%-56s %#05x %08lx\n", #name, name,       \
893                 tegra_hdmi_readl(hdmi, name))
894
895         DUMP_REG(HDMI_CTXSW);
896         DUMP_REG(HDMI_NV_PDISP_SOR_STATE0);
897         DUMP_REG(HDMI_NV_PDISP_SOR_STATE1);
898         DUMP_REG(HDMI_NV_PDISP_SOR_STATE2);
899         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_MSB);
900         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AN_LSB);
901         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_MSB);
902         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CN_LSB);
903         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_MSB);
904         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_AKSV_LSB);
905         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_MSB);
906         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_BKSV_LSB);
907         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_MSB);
908         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CKSV_LSB);
909         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_MSB);
910         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_DKSV_LSB);
911         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CTRL);
912         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CMODE);
913         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_MSB);
914         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_MPRIME_LSB);
915         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_MSB);
916         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB2);
917         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_SPRIME_LSB1);
918         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_RI);
919         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_MSB);
920         DUMP_REG(HDMI_NV_PDISP_RG_HDCP_CS_LSB);
921         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU0);
922         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU_RDATA0);
923         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU1);
924         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_EMU2);
925         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_CTRL);
926         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_STATUS);
927         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_HEADER);
928         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_LOW);
929         DUMP_REG(HDMI_NV_PDISP_HDMI_AUDIO_INFOFRAME_SUBPACK0_HIGH);
930         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_CTRL);
931         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_STATUS);
932         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_HEADER);
933         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_LOW);
934         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK0_HIGH);
935         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_LOW);
936         DUMP_REG(HDMI_NV_PDISP_HDMI_AVI_INFOFRAME_SUBPACK1_HIGH);
937         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_CTRL);
938         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_STATUS);
939         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_HEADER);
940         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_LOW);
941         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK0_HIGH);
942         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_LOW);
943         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK1_HIGH);
944         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_LOW);
945         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK2_HIGH);
946         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_LOW);
947         DUMP_REG(HDMI_NV_PDISP_HDMI_GENERIC_SUBPACK3_HIGH);
948         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_CTRL);
949         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_LOW);
950         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0320_SUBPACK_HIGH);
951         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_LOW);
952         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0441_SUBPACK_HIGH);
953         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_LOW);
954         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0882_SUBPACK_HIGH);
955         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_LOW);
956         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1764_SUBPACK_HIGH);
957         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_LOW);
958         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0480_SUBPACK_HIGH);
959         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_LOW);
960         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_0960_SUBPACK_HIGH);
961         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_LOW);
962         DUMP_REG(HDMI_NV_PDISP_HDMI_ACR_1920_SUBPACK_HIGH);
963         DUMP_REG(HDMI_NV_PDISP_HDMI_CTRL);
964         DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_KEEPOUT);
965         DUMP_REG(HDMI_NV_PDISP_HDMI_VSYNC_WINDOW);
966         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_CTRL);
967         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_STATUS);
968         DUMP_REG(HDMI_NV_PDISP_HDMI_GCP_SUBPACK);
969         DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS1);
970         DUMP_REG(HDMI_NV_PDISP_HDMI_CHANNEL_STATUS2);
971         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU0);
972         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1);
973         DUMP_REG(HDMI_NV_PDISP_HDMI_EMU1_RDATA);
974         DUMP_REG(HDMI_NV_PDISP_HDMI_SPARE);
975         DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS1);
976         DUMP_REG(HDMI_NV_PDISP_HDMI_SPDIF_CHN_STATUS2);
977         DUMP_REG(HDMI_NV_PDISP_HDMI_HDCPRIF_ROM_CTRL);
978         DUMP_REG(HDMI_NV_PDISP_SOR_CAP);
979         DUMP_REG(HDMI_NV_PDISP_SOR_PWR);
980         DUMP_REG(HDMI_NV_PDISP_SOR_TEST);
981         DUMP_REG(HDMI_NV_PDISP_SOR_PLL0);
982         DUMP_REG(HDMI_NV_PDISP_SOR_PLL1);
983         DUMP_REG(HDMI_NV_PDISP_SOR_PLL2);
984         DUMP_REG(HDMI_NV_PDISP_SOR_CSTM);
985         DUMP_REG(HDMI_NV_PDISP_SOR_LVDS);
986         DUMP_REG(HDMI_NV_PDISP_SOR_CRCA);
987         DUMP_REG(HDMI_NV_PDISP_SOR_CRCB);
988         DUMP_REG(HDMI_NV_PDISP_SOR_BLANK);
989         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_CTL);
990         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(0));
991         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(1));
992         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(2));
993         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(3));
994         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(4));
995         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(5));
996         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(6));
997         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(7));
998         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(8));
999         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(9));
1000         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(10));
1001         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(11));
1002         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(12));
1003         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(13));
1004         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(14));
1005         DUMP_REG(HDMI_NV_PDISP_SOR_SEQ_INST(15));
1006         DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA0);
1007         DUMP_REG(HDMI_NV_PDISP_SOR_VCRCA1);
1008         DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA0);
1009         DUMP_REG(HDMI_NV_PDISP_SOR_CCRCA1);
1010         DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA0);
1011         DUMP_REG(HDMI_NV_PDISP_SOR_EDATAA1);
1012         DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA0);
1013         DUMP_REG(HDMI_NV_PDISP_SOR_COUNTA1);
1014         DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA0);
1015         DUMP_REG(HDMI_NV_PDISP_SOR_DEBUGA1);
1016         DUMP_REG(HDMI_NV_PDISP_SOR_TRIG);
1017         DUMP_REG(HDMI_NV_PDISP_SOR_MSCHECK);
1018         DUMP_REG(HDMI_NV_PDISP_SOR_LANE_DRIVE_CURRENT);
1019         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG0);
1020         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG1);
1021         DUMP_REG(HDMI_NV_PDISP_AUDIO_DEBUG2);
1022         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(0));
1023         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(1));
1024         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(2));
1025         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(3));
1026         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(4));
1027         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(5));
1028         DUMP_REG(HDMI_NV_PDISP_AUDIO_FS(6));
1029         DUMP_REG(HDMI_NV_PDISP_AUDIO_PULSE_WIDTH);
1030         DUMP_REG(HDMI_NV_PDISP_AUDIO_THRESHOLD);
1031         DUMP_REG(HDMI_NV_PDISP_AUDIO_CNTRL0);
1032         DUMP_REG(HDMI_NV_PDISP_AUDIO_N);
1033         DUMP_REG(HDMI_NV_PDISP_HDCPRIF_ROM_TIMING);
1034         DUMP_REG(HDMI_NV_PDISP_SOR_REFCLK);
1035         DUMP_REG(HDMI_NV_PDISP_CRC_CONTROL);
1036         DUMP_REG(HDMI_NV_PDISP_INPUT_CONTROL);
1037         DUMP_REG(HDMI_NV_PDISP_SCRATCH);
1038         DUMP_REG(HDMI_NV_PDISP_PE_CURRENT);
1039         DUMP_REG(HDMI_NV_PDISP_KEY_CTRL);
1040         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG0);
1041         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG1);
1042         DUMP_REG(HDMI_NV_PDISP_KEY_DEBUG2);
1043         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_0);
1044         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_1);
1045         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_2);
1046         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_3);
1047         DUMP_REG(HDMI_NV_PDISP_KEY_HDCP_KEY_TRIG);
1048         DUMP_REG(HDMI_NV_PDISP_KEY_SKEY_INDEX);
1049         DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_CNTRL0);
1050         DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_ELD_BUFWR);
1051         DUMP_REG(HDMI_NV_PDISP_SOR_AUDIO_HDA_PRESENSE);
1052
1053 #undef DUMP_REG
1054
1055         clk_disable(hdmi->clk);
1056
1057         return 0;
1058 }
1059
1060 static struct drm_info_list debugfs_files[] = {
1061         { "regs", tegra_hdmi_show_regs, 0, NULL },
1062 };
1063
1064 static int tegra_hdmi_debugfs_init(struct tegra_hdmi *hdmi,
1065                                    struct drm_minor *minor)
1066 {
1067         unsigned int i;
1068         int err;
1069
1070         hdmi->debugfs = debugfs_create_dir("hdmi", minor->debugfs_root);
1071         if (!hdmi->debugfs)
1072                 return -ENOMEM;
1073
1074         hdmi->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files),
1075                                       GFP_KERNEL);
1076         if (!hdmi->debugfs_files) {
1077                 err = -ENOMEM;
1078                 goto remove;
1079         }
1080
1081         for (i = 0; i < ARRAY_SIZE(debugfs_files); i++)
1082                 hdmi->debugfs_files[i].data = hdmi;
1083
1084         err = drm_debugfs_create_files(hdmi->debugfs_files,
1085                                        ARRAY_SIZE(debugfs_files),
1086                                        hdmi->debugfs, minor);
1087         if (err < 0)
1088                 goto free;
1089
1090         hdmi->minor = minor;
1091
1092         return 0;
1093
1094 free:
1095         kfree(hdmi->debugfs_files);
1096         hdmi->debugfs_files = NULL;
1097 remove:
1098         debugfs_remove(hdmi->debugfs);
1099         hdmi->debugfs = NULL;
1100
1101         return err;
1102 }
1103
1104 static int tegra_hdmi_debugfs_exit(struct tegra_hdmi *hdmi)
1105 {
1106         drm_debugfs_remove_files(hdmi->debugfs_files, ARRAY_SIZE(debugfs_files),
1107                                  hdmi->minor);
1108         hdmi->minor = NULL;
1109
1110         kfree(hdmi->debugfs_files);
1111         hdmi->debugfs_files = NULL;
1112
1113         debugfs_remove(hdmi->debugfs);
1114         hdmi->debugfs = NULL;
1115
1116         return 0;
1117 }
1118
1119 static int tegra_hdmi_init(struct host1x_client *client)
1120 {
1121         struct tegra_drm_client *drm = to_tegra_drm_client(client);
1122         struct tegra_hdmi *hdmi = tegra_drm_client_to_hdmi(drm);
1123         int err;
1124
1125         hdmi->output.type = TEGRA_OUTPUT_HDMI;
1126         hdmi->output.dev = client->dev;
1127         hdmi->output.ops = &hdmi_ops;
1128
1129         err = tegra_output_init(drm->drm, &hdmi->output);
1130         if (err < 0) {
1131                 dev_err(client->dev, "output setup failed: %d\n", err);
1132                 return err;
1133         }
1134
1135         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1136                 err = tegra_hdmi_debugfs_init(hdmi, drm->drm->primary);
1137                 if (err < 0)
1138                         dev_err(client->dev, "debugfs setup failed: %d\n", err);
1139         }
1140
1141         return 0;
1142 }
1143
1144 static int tegra_hdmi_exit(struct host1x_client *client)
1145 {
1146         struct tegra_drm_client *drm = to_tegra_drm_client(client);
1147         struct tegra_hdmi *hdmi = tegra_drm_client_to_hdmi(drm);
1148         int err;
1149
1150         if (IS_ENABLED(CONFIG_DEBUG_FS)) {
1151                 err = tegra_hdmi_debugfs_exit(hdmi);
1152                 if (err < 0)
1153                         dev_err(client->dev, "debugfs cleanup failed: %d\n",
1154                                 err);
1155         }
1156
1157         err = tegra_output_disable(&hdmi->output);
1158         if (err < 0) {
1159                 dev_err(client->dev, "output failed to disable: %d\n", err);
1160                 return err;
1161         }
1162
1163         err = tegra_output_exit(&hdmi->output);
1164         if (err < 0) {
1165                 dev_err(client->dev, "output cleanup failed: %d\n", err);
1166                 return err;
1167         }
1168
1169         return 0;
1170 }
1171
1172 static const struct host1x_client_ops hdmi_client_ops = {
1173         .init = tegra_hdmi_init,
1174         .exit = tegra_hdmi_exit,
1175 };
1176
1177 static int tegra_hdmi_probe(struct platform_device *pdev)
1178 {
1179         struct tegra_drm *tegra = host1x_get_drm_data(pdev->dev.parent);
1180         struct tegra_hdmi *hdmi;
1181         struct resource *regs;
1182         int err;
1183
1184         hdmi = devm_kzalloc(&pdev->dev, sizeof(*hdmi), GFP_KERNEL);
1185         if (!hdmi)
1186                 return -ENOMEM;
1187
1188         hdmi->dev = &pdev->dev;
1189         hdmi->audio_source = AUTO;
1190         hdmi->audio_freq = 44100;
1191         hdmi->stereo = false;
1192         hdmi->dvi = false;
1193
1194         hdmi->clk = devm_clk_get(&pdev->dev, NULL);
1195         if (IS_ERR(hdmi->clk)) {
1196                 dev_err(&pdev->dev, "failed to get clock\n");
1197                 return PTR_ERR(hdmi->clk);
1198         }
1199
1200         err = clk_prepare(hdmi->clk);
1201         if (err < 0)
1202                 return err;
1203
1204         hdmi->clk_parent = devm_clk_get(&pdev->dev, "parent");
1205         if (IS_ERR(hdmi->clk_parent))
1206                 return PTR_ERR(hdmi->clk_parent);
1207
1208         err = clk_prepare(hdmi->clk_parent);
1209         if (err < 0)
1210                 return err;
1211
1212         err = clk_set_parent(hdmi->clk, hdmi->clk_parent);
1213         if (err < 0) {
1214                 dev_err(&pdev->dev, "failed to setup clocks: %d\n", err);
1215                 return err;
1216         }
1217
1218         hdmi->vdd = devm_regulator_get(&pdev->dev, "vdd");
1219         if (IS_ERR(hdmi->vdd)) {
1220                 dev_err(&pdev->dev, "failed to get VDD regulator\n");
1221                 return PTR_ERR(hdmi->vdd);
1222         }
1223
1224         hdmi->pll = devm_regulator_get(&pdev->dev, "pll");
1225         if (IS_ERR(hdmi->pll)) {
1226                 dev_err(&pdev->dev, "failed to get PLL regulator\n");
1227                 return PTR_ERR(hdmi->pll);
1228         }
1229
1230         hdmi->output.dev = &pdev->dev;
1231
1232         err = tegra_output_parse_dt(&hdmi->output);
1233         if (err < 0)
1234                 return err;
1235
1236         regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1237         if (!regs)
1238                 return -ENXIO;
1239
1240         hdmi->regs = devm_ioremap_resource(&pdev->dev, regs);
1241         if (IS_ERR(hdmi->regs))
1242                 return PTR_ERR(hdmi->regs);
1243
1244         err = platform_get_irq(pdev, 0);
1245         if (err < 0)
1246                 return err;
1247
1248         hdmi->irq = err;
1249
1250         INIT_LIST_HEAD(&hdmi->client.base.list);
1251         hdmi->client.base.ops = &hdmi_client_ops;
1252         hdmi->client.base.dev = &pdev->dev;
1253
1254         err = host1x_register_client(tegra, &hdmi->client.base);
1255         if (err < 0) {
1256                 dev_err(&pdev->dev, "failed to register host1x client: %d\n",
1257                         err);
1258                 return err;
1259         }
1260
1261         platform_set_drvdata(pdev, hdmi);
1262
1263         return 0;
1264 }
1265
1266 static int tegra_hdmi_remove(struct platform_device *pdev)
1267 {
1268         struct tegra_drm *tegra = host1x_get_drm_data(pdev->dev.parent);
1269         struct tegra_hdmi *hdmi = platform_get_drvdata(pdev);
1270         int err;
1271
1272         err = host1x_unregister_client(tegra, &hdmi->client.base);
1273         if (err < 0) {
1274                 dev_err(&pdev->dev, "failed to unregister host1x client: %d\n",
1275                         err);
1276                 return err;
1277         }
1278
1279         clk_unprepare(hdmi->clk_parent);
1280         clk_unprepare(hdmi->clk);
1281
1282         return 0;
1283 }
1284
1285 static struct of_device_id tegra_hdmi_of_match[] = {
1286         { .compatible = "nvidia,tegra30-hdmi", },
1287         { .compatible = "nvidia,tegra20-hdmi", },
1288         { },
1289 };
1290
1291 struct platform_driver tegra_hdmi_driver = {
1292         .driver = {
1293                 .name = "tegra-hdmi",
1294                 .owner = THIS_MODULE,
1295                 .of_match_table = tegra_hdmi_of_match,
1296         },
1297         .probe = tegra_hdmi_probe,
1298         .remove = tegra_hdmi_remove,
1299 };