2 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 #include <linux/module.h>
16 #include <linux/export.h>
17 #include <linux/types.h>
18 #include <linux/reset.h>
19 #include <linux/platform_device.h>
20 #include <linux/err.h>
21 #include <linux/spinlock.h>
22 #include <linux/delay.h>
23 #include <linux/interrupt.h>
25 #include <linux/clk.h>
26 #include <linux/list.h>
27 #include <linux/irq.h>
28 #include <linux/irqchip/chained_irq.h>
29 #include <linux/irqdomain.h>
30 #include <linux/of_device.h>
32 #include <drm/drm_fourcc.h>
34 #include <video/imx-ipu-v3.h>
37 static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
39 return readl(ipu->cm_reg + offset);
42 static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset)
44 writel(value, ipu->cm_reg + offset);
47 void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
51 val = ipu_cm_read(ipu, IPU_SRM_PRI2);
53 ipu_cm_write(ipu, val, IPU_SRM_PRI2);
55 EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update);
57 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)
60 case DRM_FORMAT_ARGB1555:
61 case DRM_FORMAT_ABGR1555:
62 case DRM_FORMAT_RGBA5551:
63 case DRM_FORMAT_BGRA5551:
64 case DRM_FORMAT_RGB565:
65 case DRM_FORMAT_BGR565:
66 case DRM_FORMAT_RGB888:
67 case DRM_FORMAT_BGR888:
68 case DRM_FORMAT_ARGB4444:
69 case DRM_FORMAT_XRGB8888:
70 case DRM_FORMAT_XBGR8888:
71 case DRM_FORMAT_RGBX8888:
72 case DRM_FORMAT_BGRX8888:
73 case DRM_FORMAT_ARGB8888:
74 case DRM_FORMAT_ABGR8888:
75 case DRM_FORMAT_RGBA8888:
76 case DRM_FORMAT_BGRA8888:
77 return IPUV3_COLORSPACE_RGB;
80 case DRM_FORMAT_YUV420:
81 case DRM_FORMAT_YVU420:
82 case DRM_FORMAT_YUV422:
83 case DRM_FORMAT_YVU422:
88 return IPUV3_COLORSPACE_YUV;
90 return IPUV3_COLORSPACE_UNKNOWN;
93 EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace);
95 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat)
97 switch (pixelformat) {
98 case V4L2_PIX_FMT_YUV420:
99 case V4L2_PIX_FMT_YVU420:
100 case V4L2_PIX_FMT_YUV422P:
101 case V4L2_PIX_FMT_UYVY:
102 case V4L2_PIX_FMT_YUYV:
103 case V4L2_PIX_FMT_NV12:
104 case V4L2_PIX_FMT_NV21:
105 case V4L2_PIX_FMT_NV16:
106 case V4L2_PIX_FMT_NV61:
107 return IPUV3_COLORSPACE_YUV;
108 case V4L2_PIX_FMT_RGB32:
109 case V4L2_PIX_FMT_BGR32:
110 case V4L2_PIX_FMT_RGB24:
111 case V4L2_PIX_FMT_BGR24:
112 case V4L2_PIX_FMT_RGB565:
113 return IPUV3_COLORSPACE_RGB;
115 return IPUV3_COLORSPACE_UNKNOWN;
118 EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace);
120 bool ipu_pixelformat_is_planar(u32 pixelformat)
122 switch (pixelformat) {
123 case V4L2_PIX_FMT_YUV420:
124 case V4L2_PIX_FMT_YVU420:
125 case V4L2_PIX_FMT_YUV422P:
126 case V4L2_PIX_FMT_NV12:
127 case V4L2_PIX_FMT_NV21:
128 case V4L2_PIX_FMT_NV16:
129 case V4L2_PIX_FMT_NV61:
135 EXPORT_SYMBOL_GPL(ipu_pixelformat_is_planar);
137 enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code)
139 switch (mbus_code & 0xf000) {
141 return IPUV3_COLORSPACE_RGB;
143 return IPUV3_COLORSPACE_YUV;
145 return IPUV3_COLORSPACE_UNKNOWN;
148 EXPORT_SYMBOL_GPL(ipu_mbus_code_to_colorspace);
150 int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat)
152 switch (pixelformat) {
153 case V4L2_PIX_FMT_YUV420:
154 case V4L2_PIX_FMT_YVU420:
155 case V4L2_PIX_FMT_YUV422P:
156 case V4L2_PIX_FMT_NV12:
157 case V4L2_PIX_FMT_NV21:
158 case V4L2_PIX_FMT_NV16:
159 case V4L2_PIX_FMT_NV61:
161 * for the planar YUV formats, the stride passed to
162 * cpmem must be the stride in bytes of the Y plane.
163 * And all the planar YUV formats have an 8-bit
166 return (8 * pixel_stride) >> 3;
167 case V4L2_PIX_FMT_RGB565:
168 case V4L2_PIX_FMT_YUYV:
169 case V4L2_PIX_FMT_UYVY:
170 return (16 * pixel_stride) >> 3;
171 case V4L2_PIX_FMT_BGR24:
172 case V4L2_PIX_FMT_RGB24:
173 return (24 * pixel_stride) >> 3;
174 case V4L2_PIX_FMT_BGR32:
175 case V4L2_PIX_FMT_RGB32:
176 return (32 * pixel_stride) >> 3;
183 EXPORT_SYMBOL_GPL(ipu_stride_to_bytes);
185 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
186 bool hflip, bool vflip)
212 *mode = (enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf);
215 EXPORT_SYMBOL_GPL(ipu_degrees_to_rot_mode);
217 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
218 bool hflip, bool vflip)
222 r90 = ((u32)mode >> 2) & 0x1;
223 hf = ((u32)mode >> 1) & 0x1;
224 vf = ((u32)mode >> 0) & 0x1;
228 switch ((enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf)) {
229 case IPU_ROTATE_NONE:
232 case IPU_ROTATE_90_RIGHT:
238 case IPU_ROTATE_90_LEFT:
247 EXPORT_SYMBOL_GPL(ipu_rot_mode_to_degrees);
249 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num)
251 struct ipuv3_channel *channel;
253 dev_dbg(ipu->dev, "%s %d\n", __func__, num);
256 return ERR_PTR(-ENODEV);
258 mutex_lock(&ipu->channel_lock);
260 channel = &ipu->channel[num];
263 channel = ERR_PTR(-EBUSY);
267 channel->busy = true;
271 mutex_unlock(&ipu->channel_lock);
275 EXPORT_SYMBOL_GPL(ipu_idmac_get);
277 void ipu_idmac_put(struct ipuv3_channel *channel)
279 struct ipu_soc *ipu = channel->ipu;
281 dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num);
283 mutex_lock(&ipu->channel_lock);
285 channel->busy = false;
287 mutex_unlock(&ipu->channel_lock);
289 EXPORT_SYMBOL_GPL(ipu_idmac_put);
291 #define idma_mask(ch) (1 << ((ch) & 0x1f))
294 * This is an undocumented feature, a write one to a channel bit in
295 * IPU_CHA_CUR_BUF and IPU_CHA_TRIPLE_CUR_BUF will reset the channel's
296 * internal current buffer pointer so that transfers start from buffer
297 * 0 on the next channel enable (that's the theory anyway, the imx6 TRM
298 * only says these are read-only registers). This operation is required
299 * for channel linking to work correctly, for instance video capture
300 * pipelines that carry out image rotations will fail after the first
301 * streaming unless this function is called for each channel before
302 * re-enabling the channels.
304 static void __ipu_idmac_reset_current_buffer(struct ipuv3_channel *channel)
306 struct ipu_soc *ipu = channel->ipu;
307 unsigned int chno = channel->num;
309 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno));
312 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
315 struct ipu_soc *ipu = channel->ipu;
319 spin_lock_irqsave(&ipu->lock, flags);
321 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
323 reg |= idma_mask(channel->num);
325 reg &= ~idma_mask(channel->num);
326 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num));
328 __ipu_idmac_reset_current_buffer(channel);
330 spin_unlock_irqrestore(&ipu->lock, flags);
332 EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer);
334 static const struct {
338 } idmac_lock_en_info[] = {
339 { .chnum = 5, .reg = IDMAC_CH_LOCK_EN_1, .shift = 0, },
340 { .chnum = 11, .reg = IDMAC_CH_LOCK_EN_1, .shift = 2, },
341 { .chnum = 12, .reg = IDMAC_CH_LOCK_EN_1, .shift = 4, },
342 { .chnum = 14, .reg = IDMAC_CH_LOCK_EN_1, .shift = 6, },
343 { .chnum = 15, .reg = IDMAC_CH_LOCK_EN_1, .shift = 8, },
344 { .chnum = 20, .reg = IDMAC_CH_LOCK_EN_1, .shift = 10, },
345 { .chnum = 21, .reg = IDMAC_CH_LOCK_EN_1, .shift = 12, },
346 { .chnum = 22, .reg = IDMAC_CH_LOCK_EN_1, .shift = 14, },
347 { .chnum = 23, .reg = IDMAC_CH_LOCK_EN_1, .shift = 16, },
348 { .chnum = 27, .reg = IDMAC_CH_LOCK_EN_1, .shift = 18, },
349 { .chnum = 28, .reg = IDMAC_CH_LOCK_EN_1, .shift = 20, },
350 { .chnum = 45, .reg = IDMAC_CH_LOCK_EN_2, .shift = 0, },
351 { .chnum = 46, .reg = IDMAC_CH_LOCK_EN_2, .shift = 2, },
352 { .chnum = 47, .reg = IDMAC_CH_LOCK_EN_2, .shift = 4, },
353 { .chnum = 48, .reg = IDMAC_CH_LOCK_EN_2, .shift = 6, },
354 { .chnum = 49, .reg = IDMAC_CH_LOCK_EN_2, .shift = 8, },
355 { .chnum = 50, .reg = IDMAC_CH_LOCK_EN_2, .shift = 10, },
358 int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts)
360 struct ipu_soc *ipu = channel->ipu;
365 switch (num_bursts) {
368 bursts = 0x00; /* locking disabled */
383 for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) {
384 if (channel->num == idmac_lock_en_info[i].chnum)
387 if (i >= ARRAY_SIZE(idmac_lock_en_info))
390 spin_lock_irqsave(&ipu->lock, flags);
392 regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg);
393 regval &= ~(0x03 << idmac_lock_en_info[i].shift);
394 regval |= (bursts << idmac_lock_en_info[i].shift);
395 ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg);
397 spin_unlock_irqrestore(&ipu->lock, flags);
401 EXPORT_SYMBOL_GPL(ipu_idmac_lock_enable);
403 int ipu_module_enable(struct ipu_soc *ipu, u32 mask)
405 unsigned long lock_flags;
408 spin_lock_irqsave(&ipu->lock, lock_flags);
410 val = ipu_cm_read(ipu, IPU_DISP_GEN);
412 if (mask & IPU_CONF_DI0_EN)
413 val |= IPU_DI0_COUNTER_RELEASE;
414 if (mask & IPU_CONF_DI1_EN)
415 val |= IPU_DI1_COUNTER_RELEASE;
417 ipu_cm_write(ipu, val, IPU_DISP_GEN);
419 val = ipu_cm_read(ipu, IPU_CONF);
421 ipu_cm_write(ipu, val, IPU_CONF);
423 spin_unlock_irqrestore(&ipu->lock, lock_flags);
427 EXPORT_SYMBOL_GPL(ipu_module_enable);
429 int ipu_module_disable(struct ipu_soc *ipu, u32 mask)
431 unsigned long lock_flags;
434 spin_lock_irqsave(&ipu->lock, lock_flags);
436 val = ipu_cm_read(ipu, IPU_CONF);
438 ipu_cm_write(ipu, val, IPU_CONF);
440 val = ipu_cm_read(ipu, IPU_DISP_GEN);
442 if (mask & IPU_CONF_DI0_EN)
443 val &= ~IPU_DI0_COUNTER_RELEASE;
444 if (mask & IPU_CONF_DI1_EN)
445 val &= ~IPU_DI1_COUNTER_RELEASE;
447 ipu_cm_write(ipu, val, IPU_DISP_GEN);
449 spin_unlock_irqrestore(&ipu->lock, lock_flags);
453 EXPORT_SYMBOL_GPL(ipu_module_disable);
455 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel)
457 struct ipu_soc *ipu = channel->ipu;
458 unsigned int chno = channel->num;
460 return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;
462 EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer);
464 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num)
466 struct ipu_soc *ipu = channel->ipu;
470 spin_lock_irqsave(&ipu->lock, flags);
473 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num));
476 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num));
479 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num));
482 spin_unlock_irqrestore(&ipu->lock, flags);
484 return ((reg & idma_mask(channel->num)) != 0);
486 EXPORT_SYMBOL_GPL(ipu_idmac_buffer_is_ready);
488 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num)
490 struct ipu_soc *ipu = channel->ipu;
491 unsigned int chno = channel->num;
494 spin_lock_irqsave(&ipu->lock, flags);
496 /* Mark buffer as ready. */
498 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
500 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
502 spin_unlock_irqrestore(&ipu->lock, flags);
504 EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer);
506 void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num)
508 struct ipu_soc *ipu = channel->ipu;
509 unsigned int chno = channel->num;
512 spin_lock_irqsave(&ipu->lock, flags);
514 ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */
517 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
520 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
523 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno));
528 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
530 spin_unlock_irqrestore(&ipu->lock, flags);
532 EXPORT_SYMBOL_GPL(ipu_idmac_clear_buffer);
534 int ipu_idmac_enable_channel(struct ipuv3_channel *channel)
536 struct ipu_soc *ipu = channel->ipu;
540 spin_lock_irqsave(&ipu->lock, flags);
542 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
543 val |= idma_mask(channel->num);
544 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
546 spin_unlock_irqrestore(&ipu->lock, flags);
550 EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel);
552 bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno)
554 return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno));
556 EXPORT_SYMBOL_GPL(ipu_idmac_channel_busy);
558 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms)
560 struct ipu_soc *ipu = channel->ipu;
561 unsigned long timeout;
563 timeout = jiffies + msecs_to_jiffies(ms);
564 while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) &
565 idma_mask(channel->num)) {
566 if (time_after(jiffies, timeout))
573 EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy);
575 int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms)
577 unsigned long timeout;
579 timeout = jiffies + msecs_to_jiffies(ms);
580 ipu_cm_write(ipu, BIT(irq % 32), IPU_INT_STAT(irq / 32));
581 while (!(ipu_cm_read(ipu, IPU_INT_STAT(irq / 32) & BIT(irq % 32)))) {
582 if (time_after(jiffies, timeout))
589 EXPORT_SYMBOL_GPL(ipu_wait_interrupt);
591 int ipu_idmac_disable_channel(struct ipuv3_channel *channel)
593 struct ipu_soc *ipu = channel->ipu;
597 spin_lock_irqsave(&ipu->lock, flags);
599 /* Disable DMA channel(s) */
600 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
601 val &= ~idma_mask(channel->num);
602 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
604 __ipu_idmac_reset_current_buffer(channel);
606 /* Set channel buffers NOT to be ready */
607 ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */
609 if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) &
610 idma_mask(channel->num)) {
611 ipu_cm_write(ipu, idma_mask(channel->num),
612 IPU_CHA_BUF0_RDY(channel->num));
615 if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) &
616 idma_mask(channel->num)) {
617 ipu_cm_write(ipu, idma_mask(channel->num),
618 IPU_CHA_BUF1_RDY(channel->num));
621 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
623 /* Reset the double buffer */
624 val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
625 val &= ~idma_mask(channel->num);
626 ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num));
628 spin_unlock_irqrestore(&ipu->lock, flags);
632 EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel);
635 * The imx6 rev. D TRM says that enabling the WM feature will increase
636 * a channel's priority. Refer to Table 36-8 Calculated priority value.
637 * The sub-module that is the sink or source for the channel must enable
638 * watermark signal for this to take effect (SMFC_WM for instance).
640 void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable)
642 struct ipu_soc *ipu = channel->ipu;
646 spin_lock_irqsave(&ipu->lock, flags);
648 val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num));
650 val |= 1 << (channel->num % 32);
652 val &= ~(1 << (channel->num % 32));
653 ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num));
655 spin_unlock_irqrestore(&ipu->lock, flags);
657 EXPORT_SYMBOL_GPL(ipu_idmac_enable_watermark);
659 static int ipu_memory_reset(struct ipu_soc *ipu)
661 unsigned long timeout;
663 ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
665 timeout = jiffies + msecs_to_jiffies(1000);
666 while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
667 if (time_after(jiffies, timeout))
676 * Set the source mux for the given CSI. Selects either parallel or
679 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2)
684 mask = (csi_id == 1) ? IPU_CONF_CSI1_DATA_SOURCE :
685 IPU_CONF_CSI0_DATA_SOURCE;
687 spin_lock_irqsave(&ipu->lock, flags);
689 val = ipu_cm_read(ipu, IPU_CONF);
694 ipu_cm_write(ipu, val, IPU_CONF);
696 spin_unlock_irqrestore(&ipu->lock, flags);
698 EXPORT_SYMBOL_GPL(ipu_set_csi_src_mux);
701 * Set the source mux for the IC. Selects either CSI[01] or the VDI.
703 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi)
708 spin_lock_irqsave(&ipu->lock, flags);
710 val = ipu_cm_read(ipu, IPU_CONF);
712 val |= IPU_CONF_IC_INPUT;
714 val &= ~IPU_CONF_IC_INPUT;
716 val |= IPU_CONF_CSI_SEL;
718 val &= ~IPU_CONF_CSI_SEL;
720 ipu_cm_write(ipu, val, IPU_CONF);
722 spin_unlock_irqrestore(&ipu->lock, flags);
724 EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux);
728 unsigned long cm_ofs;
729 unsigned long cpmem_ofs;
730 unsigned long srm_ofs;
731 unsigned long tpm_ofs;
732 unsigned long csi0_ofs;
733 unsigned long csi1_ofs;
734 unsigned long ic_ofs;
735 unsigned long disp0_ofs;
736 unsigned long disp1_ofs;
737 unsigned long dc_tmpl_ofs;
738 unsigned long vdi_ofs;
739 enum ipuv3_type type;
742 static struct ipu_devtype ipu_type_imx51 = {
744 .cm_ofs = 0x1e000000,
745 .cpmem_ofs = 0x1f000000,
746 .srm_ofs = 0x1f040000,
747 .tpm_ofs = 0x1f060000,
748 .csi0_ofs = 0x1f030000,
749 .csi1_ofs = 0x1f038000,
750 .ic_ofs = 0x1e020000,
751 .disp0_ofs = 0x1e040000,
752 .disp1_ofs = 0x1e048000,
753 .dc_tmpl_ofs = 0x1f080000,
754 .vdi_ofs = 0x1e068000,
758 static struct ipu_devtype ipu_type_imx53 = {
760 .cm_ofs = 0x06000000,
761 .cpmem_ofs = 0x07000000,
762 .srm_ofs = 0x07040000,
763 .tpm_ofs = 0x07060000,
764 .csi0_ofs = 0x07030000,
765 .csi1_ofs = 0x07038000,
766 .ic_ofs = 0x06020000,
767 .disp0_ofs = 0x06040000,
768 .disp1_ofs = 0x06048000,
769 .dc_tmpl_ofs = 0x07080000,
770 .vdi_ofs = 0x06068000,
774 static struct ipu_devtype ipu_type_imx6q = {
776 .cm_ofs = 0x00200000,
777 .cpmem_ofs = 0x00300000,
778 .srm_ofs = 0x00340000,
779 .tpm_ofs = 0x00360000,
780 .csi0_ofs = 0x00230000,
781 .csi1_ofs = 0x00238000,
782 .ic_ofs = 0x00220000,
783 .disp0_ofs = 0x00240000,
784 .disp1_ofs = 0x00248000,
785 .dc_tmpl_ofs = 0x00380000,
786 .vdi_ofs = 0x00268000,
790 static const struct of_device_id imx_ipu_dt_ids[] = {
791 { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, },
792 { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, },
793 { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, },
796 MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids);
798 static int ipu_submodules_init(struct ipu_soc *ipu,
799 struct platform_device *pdev, unsigned long ipu_base,
804 struct device *dev = &pdev->dev;
805 const struct ipu_devtype *devtype = ipu->devtype;
807 ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs);
813 ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs,
814 IPU_CONF_CSI0_EN, ipu_clk);
820 ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs,
821 IPU_CONF_CSI1_EN, ipu_clk);
827 ret = ipu_ic_init(ipu, dev,
828 ipu_base + devtype->ic_ofs,
829 ipu_base + devtype->tpm_ofs);
835 ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
836 IPU_CONF_DI0_EN, ipu_clk);
842 ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs,
843 IPU_CONF_DI1_EN, ipu_clk);
849 ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs +
850 IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs);
852 unit = "dc_template";
856 ret = ipu_dmfc_init(ipu, dev, ipu_base +
857 devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk);
863 ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs);
869 ret = ipu_smfc_init(ipu, dev, ipu_base +
870 devtype->cm_ofs + IPU_CM_SMFC_REG_OFS);
891 ipu_csi_exit(ipu, 1);
893 ipu_csi_exit(ipu, 0);
897 dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret);
901 static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs)
903 unsigned long status;
906 for (i = 0; i < num_regs; i++) {
908 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i]));
909 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i]));
911 for_each_set_bit(bit, &status, 32) {
912 irq = irq_linear_revmap(ipu->domain,
915 generic_handle_irq(irq);
920 static void ipu_irq_handler(struct irq_desc *desc)
922 struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
923 struct irq_chip *chip = irq_desc_get_chip(desc);
924 const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14};
926 chained_irq_enter(chip, desc);
928 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
930 chained_irq_exit(chip, desc);
933 static void ipu_err_irq_handler(struct irq_desc *desc)
935 struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
936 struct irq_chip *chip = irq_desc_get_chip(desc);
937 const int int_reg[] = { 4, 5, 8, 9};
939 chained_irq_enter(chip, desc);
941 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
943 chained_irq_exit(chip, desc);
946 int ipu_map_irq(struct ipu_soc *ipu, int irq)
950 virq = irq_linear_revmap(ipu->domain, irq);
952 virq = irq_create_mapping(ipu->domain, irq);
956 EXPORT_SYMBOL_GPL(ipu_map_irq);
958 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
959 enum ipu_channel_irq irq_type)
961 return ipu_map_irq(ipu, irq_type + channel->num);
963 EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq);
965 static void ipu_submodules_exit(struct ipu_soc *ipu)
974 ipu_csi_exit(ipu, 1);
975 ipu_csi_exit(ipu, 0);
979 static int platform_remove_devices_fn(struct device *dev, void *unused)
981 struct platform_device *pdev = to_platform_device(dev);
983 platform_device_unregister(pdev);
988 static void platform_device_unregister_children(struct platform_device *pdev)
990 device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn);
993 struct ipu_platform_reg {
994 struct ipu_client_platformdata pdata;
999 static const struct ipu_platform_reg client_reg[] = {
1004 .dp = IPU_DP_FLOW_SYNC_BG,
1005 .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC,
1006 .dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC,
1008 .name = "imx-ipuv3-crtc",
1014 .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC,
1017 .name = "imx-ipuv3-crtc",
1021 .dma[0] = IPUV3_CHANNEL_CSI0,
1024 .reg_offset = IPU_CM_CSI0_REG_OFS,
1025 .name = "imx-ipuv3-camera",
1029 .dma[0] = IPUV3_CHANNEL_CSI1,
1032 .reg_offset = IPU_CM_CSI1_REG_OFS,
1033 .name = "imx-ipuv3-camera",
1037 static DEFINE_MUTEX(ipu_client_id_mutex);
1038 static int ipu_client_id;
1040 static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base)
1042 struct device *dev = ipu->dev;
1046 mutex_lock(&ipu_client_id_mutex);
1048 ipu_client_id += ARRAY_SIZE(client_reg);
1049 mutex_unlock(&ipu_client_id_mutex);
1051 for (i = 0; i < ARRAY_SIZE(client_reg); i++) {
1052 const struct ipu_platform_reg *reg = &client_reg[i];
1053 struct platform_device *pdev;
1054 struct resource res;
1056 if (reg->reg_offset) {
1057 memset(&res, 0, sizeof(res));
1058 res.flags = IORESOURCE_MEM;
1059 res.start = ipu_base + ipu->devtype->cm_ofs + reg->reg_offset;
1060 res.end = res.start + PAGE_SIZE - 1;
1061 pdev = platform_device_register_resndata(dev, reg->name,
1062 id++, &res, 1, ®->pdata, sizeof(reg->pdata));
1064 pdev = platform_device_register_data(dev, reg->name,
1065 id++, ®->pdata, sizeof(reg->pdata));
1069 ret = PTR_ERR(pdev);
1077 platform_device_unregister_children(to_platform_device(dev));
1083 static int ipu_irq_init(struct ipu_soc *ipu)
1085 struct irq_chip_generic *gc;
1086 struct irq_chip_type *ct;
1087 unsigned long unused[IPU_NUM_IRQS / 32] = {
1088 0x400100d0, 0xffe000fd,
1089 0x400100d0, 0xffe000fd,
1090 0x400100d0, 0xffe000fd,
1091 0x4077ffff, 0xffe7e1fd,
1092 0x23fffffe, 0x8880fff0,
1093 0xf98fe7d0, 0xfff81fff,
1094 0x400100d0, 0xffe000fd,
1099 ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS,
1100 &irq_generic_chip_ops, ipu);
1102 dev_err(ipu->dev, "failed to add irq domain\n");
1106 ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU",
1107 handle_level_irq, 0, 0, 0);
1109 dev_err(ipu->dev, "failed to alloc generic irq chips\n");
1110 irq_domain_remove(ipu->domain);
1114 for (i = 0; i < IPU_NUM_IRQS; i += 32)
1115 ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32));
1117 for (i = 0; i < IPU_NUM_IRQS; i += 32) {
1118 gc = irq_get_domain_generic_chip(ipu->domain, i);
1119 gc->reg_base = ipu->cm_reg;
1120 gc->unused = unused[i / 32];
1121 ct = gc->chip_types;
1122 ct->chip.irq_ack = irq_gc_ack_set_bit;
1123 ct->chip.irq_mask = irq_gc_mask_clr_bit;
1124 ct->chip.irq_unmask = irq_gc_mask_set_bit;
1125 ct->regs.ack = IPU_INT_STAT(i / 32);
1126 ct->regs.mask = IPU_INT_CTRL(i / 32);
1129 irq_set_chained_handler_and_data(ipu->irq_sync, ipu_irq_handler, ipu);
1130 irq_set_chained_handler_and_data(ipu->irq_err, ipu_err_irq_handler,
1136 static void ipu_irq_exit(struct ipu_soc *ipu)
1140 irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL);
1141 irq_set_chained_handler_and_data(ipu->irq_sync, NULL, NULL);
1143 /* TODO: remove irq_domain_generic_chips */
1145 for (i = 0; i < IPU_NUM_IRQS; i++) {
1146 irq = irq_linear_revmap(ipu->domain, i);
1148 irq_dispose_mapping(irq);
1151 irq_domain_remove(ipu->domain);
1154 void ipu_dump(struct ipu_soc *ipu)
1158 dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n",
1159 ipu_cm_read(ipu, IPU_CONF));
1160 dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n",
1161 ipu_idmac_read(ipu, IDMAC_CONF));
1162 dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n",
1163 ipu_idmac_read(ipu, IDMAC_CHA_EN(0)));
1164 dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n",
1165 ipu_idmac_read(ipu, IDMAC_CHA_EN(32)));
1166 dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n",
1167 ipu_idmac_read(ipu, IDMAC_CHA_PRI(0)));
1168 dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n",
1169 ipu_idmac_read(ipu, IDMAC_CHA_PRI(32)));
1170 dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n",
1171 ipu_idmac_read(ipu, IDMAC_BAND_EN(0)));
1172 dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n",
1173 ipu_idmac_read(ipu, IDMAC_BAND_EN(32)));
1174 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
1175 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0)));
1176 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
1177 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32)));
1178 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n",
1179 ipu_cm_read(ipu, IPU_FS_PROC_FLOW1));
1180 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n",
1181 ipu_cm_read(ipu, IPU_FS_PROC_FLOW2));
1182 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n",
1183 ipu_cm_read(ipu, IPU_FS_PROC_FLOW3));
1184 dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n",
1185 ipu_cm_read(ipu, IPU_FS_DISP_FLOW1));
1186 for (i = 0; i < 15; i++)
1187 dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i,
1188 ipu_cm_read(ipu, IPU_INT_CTRL(i)));
1190 EXPORT_SYMBOL_GPL(ipu_dump);
1192 static int ipu_probe(struct platform_device *pdev)
1194 const struct of_device_id *of_id =
1195 of_match_device(imx_ipu_dt_ids, &pdev->dev);
1196 struct ipu_soc *ipu;
1197 struct resource *res;
1198 unsigned long ipu_base;
1199 int i, ret, irq_sync, irq_err;
1200 const struct ipu_devtype *devtype;
1202 devtype = of_id->data;
1204 irq_sync = platform_get_irq(pdev, 0);
1205 irq_err = platform_get_irq(pdev, 1);
1206 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1208 dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n",
1211 if (!res || irq_sync < 0 || irq_err < 0)
1214 ipu_base = res->start;
1216 ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL);
1220 for (i = 0; i < 64; i++)
1221 ipu->channel[i].ipu = ipu;
1222 ipu->devtype = devtype;
1223 ipu->ipu_type = devtype->type;
1225 spin_lock_init(&ipu->lock);
1226 mutex_init(&ipu->channel_lock);
1228 dev_dbg(&pdev->dev, "cm_reg: 0x%08lx\n",
1229 ipu_base + devtype->cm_ofs);
1230 dev_dbg(&pdev->dev, "idmac: 0x%08lx\n",
1231 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS);
1232 dev_dbg(&pdev->dev, "cpmem: 0x%08lx\n",
1233 ipu_base + devtype->cpmem_ofs);
1234 dev_dbg(&pdev->dev, "csi0: 0x%08lx\n",
1235 ipu_base + devtype->csi0_ofs);
1236 dev_dbg(&pdev->dev, "csi1: 0x%08lx\n",
1237 ipu_base + devtype->csi1_ofs);
1238 dev_dbg(&pdev->dev, "ic: 0x%08lx\n",
1239 ipu_base + devtype->ic_ofs);
1240 dev_dbg(&pdev->dev, "disp0: 0x%08lx\n",
1241 ipu_base + devtype->disp0_ofs);
1242 dev_dbg(&pdev->dev, "disp1: 0x%08lx\n",
1243 ipu_base + devtype->disp1_ofs);
1244 dev_dbg(&pdev->dev, "srm: 0x%08lx\n",
1245 ipu_base + devtype->srm_ofs);
1246 dev_dbg(&pdev->dev, "tpm: 0x%08lx\n",
1247 ipu_base + devtype->tpm_ofs);
1248 dev_dbg(&pdev->dev, "dc: 0x%08lx\n",
1249 ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS);
1250 dev_dbg(&pdev->dev, "ic: 0x%08lx\n",
1251 ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS);
1252 dev_dbg(&pdev->dev, "dmfc: 0x%08lx\n",
1253 ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS);
1254 dev_dbg(&pdev->dev, "vdi: 0x%08lx\n",
1255 ipu_base + devtype->vdi_ofs);
1257 ipu->cm_reg = devm_ioremap(&pdev->dev,
1258 ipu_base + devtype->cm_ofs, PAGE_SIZE);
1259 ipu->idmac_reg = devm_ioremap(&pdev->dev,
1260 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS,
1263 if (!ipu->cm_reg || !ipu->idmac_reg)
1266 ipu->clk = devm_clk_get(&pdev->dev, "bus");
1267 if (IS_ERR(ipu->clk)) {
1268 ret = PTR_ERR(ipu->clk);
1269 dev_err(&pdev->dev, "clk_get failed with %d", ret);
1273 platform_set_drvdata(pdev, ipu);
1275 ret = clk_prepare_enable(ipu->clk);
1277 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1281 ipu->dev = &pdev->dev;
1282 ipu->irq_sync = irq_sync;
1283 ipu->irq_err = irq_err;
1285 ret = ipu_irq_init(ipu);
1287 goto out_failed_irq;
1289 ret = device_reset(&pdev->dev);
1291 dev_err(&pdev->dev, "failed to reset: %d\n", ret);
1292 goto out_failed_reset;
1294 ret = ipu_memory_reset(ipu);
1296 goto out_failed_reset;
1298 /* Set MCU_T to divide MCU access window into 2 */
1299 ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
1302 ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk);
1304 goto failed_submodules_init;
1306 ret = ipu_add_client_devices(ipu, ipu_base);
1308 dev_err(&pdev->dev, "adding client devices failed with %d\n",
1310 goto failed_add_clients;
1313 dev_info(&pdev->dev, "%s probed\n", devtype->name);
1318 ipu_submodules_exit(ipu);
1319 failed_submodules_init:
1323 clk_disable_unprepare(ipu->clk);
1327 static int ipu_remove(struct platform_device *pdev)
1329 struct ipu_soc *ipu = platform_get_drvdata(pdev);
1331 platform_device_unregister_children(pdev);
1332 ipu_submodules_exit(ipu);
1335 clk_disable_unprepare(ipu->clk);
1340 static struct platform_driver imx_ipu_driver = {
1342 .name = "imx-ipuv3",
1343 .of_match_table = imx_ipu_dt_ids,
1346 .remove = ipu_remove,
1349 module_platform_driver(imx_ipu_driver);
1351 MODULE_ALIAS("platform:imx-ipuv3");
1352 MODULE_DESCRIPTION("i.MX IPU v3 driver");
1353 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1354 MODULE_LICENSE("GPL");