2 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 #include <linux/module.h>
16 #include <linux/export.h>
17 #include <linux/types.h>
18 #include <linux/reset.h>
19 #include <linux/platform_device.h>
20 #include <linux/err.h>
21 #include <linux/spinlock.h>
22 #include <linux/delay.h>
23 #include <linux/interrupt.h>
25 #include <linux/clk.h>
26 #include <linux/list.h>
27 #include <linux/irq.h>
28 #include <linux/irqchip/chained_irq.h>
29 #include <linux/irqdomain.h>
30 #include <linux/of_device.h>
31 #include <linux/of_graph.h>
33 #include <drm/drm_fourcc.h>
35 #include <video/imx-ipu-v3.h>
38 static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset)
40 return readl(ipu->cm_reg + offset);
43 static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset)
45 writel(value, ipu->cm_reg + offset);
48 void ipu_srm_dp_sync_update(struct ipu_soc *ipu)
52 val = ipu_cm_read(ipu, IPU_SRM_PRI2);
54 ipu_cm_write(ipu, val, IPU_SRM_PRI2);
56 EXPORT_SYMBOL_GPL(ipu_srm_dp_sync_update);
58 enum ipu_color_space ipu_drm_fourcc_to_colorspace(u32 drm_fourcc)
61 case DRM_FORMAT_ARGB1555:
62 case DRM_FORMAT_ABGR1555:
63 case DRM_FORMAT_RGBA5551:
64 case DRM_FORMAT_BGRA5551:
65 case DRM_FORMAT_RGB565:
66 case DRM_FORMAT_BGR565:
67 case DRM_FORMAT_RGB888:
68 case DRM_FORMAT_BGR888:
69 case DRM_FORMAT_ARGB4444:
70 case DRM_FORMAT_XRGB8888:
71 case DRM_FORMAT_XBGR8888:
72 case DRM_FORMAT_RGBX8888:
73 case DRM_FORMAT_BGRX8888:
74 case DRM_FORMAT_ARGB8888:
75 case DRM_FORMAT_ABGR8888:
76 case DRM_FORMAT_RGBA8888:
77 case DRM_FORMAT_BGRA8888:
78 return IPUV3_COLORSPACE_RGB;
81 case DRM_FORMAT_YUV420:
82 case DRM_FORMAT_YVU420:
83 case DRM_FORMAT_YUV422:
84 case DRM_FORMAT_YVU422:
89 return IPUV3_COLORSPACE_YUV;
91 return IPUV3_COLORSPACE_UNKNOWN;
94 EXPORT_SYMBOL_GPL(ipu_drm_fourcc_to_colorspace);
96 enum ipu_color_space ipu_pixelformat_to_colorspace(u32 pixelformat)
98 switch (pixelformat) {
99 case V4L2_PIX_FMT_YUV420:
100 case V4L2_PIX_FMT_YVU420:
101 case V4L2_PIX_FMT_YUV422P:
102 case V4L2_PIX_FMT_UYVY:
103 case V4L2_PIX_FMT_YUYV:
104 case V4L2_PIX_FMT_NV12:
105 case V4L2_PIX_FMT_NV21:
106 case V4L2_PIX_FMT_NV16:
107 case V4L2_PIX_FMT_NV61:
108 return IPUV3_COLORSPACE_YUV;
109 case V4L2_PIX_FMT_RGB32:
110 case V4L2_PIX_FMT_BGR32:
111 case V4L2_PIX_FMT_RGB24:
112 case V4L2_PIX_FMT_BGR24:
113 case V4L2_PIX_FMT_RGB565:
114 return IPUV3_COLORSPACE_RGB;
116 return IPUV3_COLORSPACE_UNKNOWN;
119 EXPORT_SYMBOL_GPL(ipu_pixelformat_to_colorspace);
121 bool ipu_pixelformat_is_planar(u32 pixelformat)
123 switch (pixelformat) {
124 case V4L2_PIX_FMT_YUV420:
125 case V4L2_PIX_FMT_YVU420:
126 case V4L2_PIX_FMT_YUV422P:
127 case V4L2_PIX_FMT_NV12:
128 case V4L2_PIX_FMT_NV21:
129 case V4L2_PIX_FMT_NV16:
130 case V4L2_PIX_FMT_NV61:
136 EXPORT_SYMBOL_GPL(ipu_pixelformat_is_planar);
138 enum ipu_color_space ipu_mbus_code_to_colorspace(u32 mbus_code)
140 switch (mbus_code & 0xf000) {
142 return IPUV3_COLORSPACE_RGB;
144 return IPUV3_COLORSPACE_YUV;
146 return IPUV3_COLORSPACE_UNKNOWN;
149 EXPORT_SYMBOL_GPL(ipu_mbus_code_to_colorspace);
151 int ipu_stride_to_bytes(u32 pixel_stride, u32 pixelformat)
153 switch (pixelformat) {
154 case V4L2_PIX_FMT_YUV420:
155 case V4L2_PIX_FMT_YVU420:
156 case V4L2_PIX_FMT_YUV422P:
157 case V4L2_PIX_FMT_NV12:
158 case V4L2_PIX_FMT_NV21:
159 case V4L2_PIX_FMT_NV16:
160 case V4L2_PIX_FMT_NV61:
162 * for the planar YUV formats, the stride passed to
163 * cpmem must be the stride in bytes of the Y plane.
164 * And all the planar YUV formats have an 8-bit
167 return (8 * pixel_stride) >> 3;
168 case V4L2_PIX_FMT_RGB565:
169 case V4L2_PIX_FMT_YUYV:
170 case V4L2_PIX_FMT_UYVY:
171 return (16 * pixel_stride) >> 3;
172 case V4L2_PIX_FMT_BGR24:
173 case V4L2_PIX_FMT_RGB24:
174 return (24 * pixel_stride) >> 3;
175 case V4L2_PIX_FMT_BGR32:
176 case V4L2_PIX_FMT_RGB32:
177 return (32 * pixel_stride) >> 3;
184 EXPORT_SYMBOL_GPL(ipu_stride_to_bytes);
186 int ipu_degrees_to_rot_mode(enum ipu_rotate_mode *mode, int degrees,
187 bool hflip, bool vflip)
213 *mode = (enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf);
216 EXPORT_SYMBOL_GPL(ipu_degrees_to_rot_mode);
218 int ipu_rot_mode_to_degrees(int *degrees, enum ipu_rotate_mode mode,
219 bool hflip, bool vflip)
223 r90 = ((u32)mode >> 2) & 0x1;
224 hf = ((u32)mode >> 1) & 0x1;
225 vf = ((u32)mode >> 0) & 0x1;
229 switch ((enum ipu_rotate_mode)((r90 << 2) | (hf << 1) | vf)) {
230 case IPU_ROTATE_NONE:
233 case IPU_ROTATE_90_RIGHT:
239 case IPU_ROTATE_90_LEFT:
248 EXPORT_SYMBOL_GPL(ipu_rot_mode_to_degrees);
250 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num)
252 struct ipuv3_channel *channel;
254 dev_dbg(ipu->dev, "%s %d\n", __func__, num);
257 return ERR_PTR(-ENODEV);
259 mutex_lock(&ipu->channel_lock);
261 channel = &ipu->channel[num];
264 channel = ERR_PTR(-EBUSY);
268 channel->busy = true;
272 mutex_unlock(&ipu->channel_lock);
276 EXPORT_SYMBOL_GPL(ipu_idmac_get);
278 void ipu_idmac_put(struct ipuv3_channel *channel)
280 struct ipu_soc *ipu = channel->ipu;
282 dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num);
284 mutex_lock(&ipu->channel_lock);
286 channel->busy = false;
288 mutex_unlock(&ipu->channel_lock);
290 EXPORT_SYMBOL_GPL(ipu_idmac_put);
292 #define idma_mask(ch) (1 << ((ch) & 0x1f))
295 * This is an undocumented feature, a write one to a channel bit in
296 * IPU_CHA_CUR_BUF and IPU_CHA_TRIPLE_CUR_BUF will reset the channel's
297 * internal current buffer pointer so that transfers start from buffer
298 * 0 on the next channel enable (that's the theory anyway, the imx6 TRM
299 * only says these are read-only registers). This operation is required
300 * for channel linking to work correctly, for instance video capture
301 * pipelines that carry out image rotations will fail after the first
302 * streaming unless this function is called for each channel before
303 * re-enabling the channels.
305 static void __ipu_idmac_reset_current_buffer(struct ipuv3_channel *channel)
307 struct ipu_soc *ipu = channel->ipu;
308 unsigned int chno = channel->num;
310 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno));
313 void ipu_idmac_set_double_buffer(struct ipuv3_channel *channel,
316 struct ipu_soc *ipu = channel->ipu;
320 spin_lock_irqsave(&ipu->lock, flags);
322 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
324 reg |= idma_mask(channel->num);
326 reg &= ~idma_mask(channel->num);
327 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num));
329 __ipu_idmac_reset_current_buffer(channel);
331 spin_unlock_irqrestore(&ipu->lock, flags);
333 EXPORT_SYMBOL_GPL(ipu_idmac_set_double_buffer);
335 static const struct {
339 } idmac_lock_en_info[] = {
340 { .chnum = 5, .reg = IDMAC_CH_LOCK_EN_1, .shift = 0, },
341 { .chnum = 11, .reg = IDMAC_CH_LOCK_EN_1, .shift = 2, },
342 { .chnum = 12, .reg = IDMAC_CH_LOCK_EN_1, .shift = 4, },
343 { .chnum = 14, .reg = IDMAC_CH_LOCK_EN_1, .shift = 6, },
344 { .chnum = 15, .reg = IDMAC_CH_LOCK_EN_1, .shift = 8, },
345 { .chnum = 20, .reg = IDMAC_CH_LOCK_EN_1, .shift = 10, },
346 { .chnum = 21, .reg = IDMAC_CH_LOCK_EN_1, .shift = 12, },
347 { .chnum = 22, .reg = IDMAC_CH_LOCK_EN_1, .shift = 14, },
348 { .chnum = 23, .reg = IDMAC_CH_LOCK_EN_1, .shift = 16, },
349 { .chnum = 27, .reg = IDMAC_CH_LOCK_EN_1, .shift = 18, },
350 { .chnum = 28, .reg = IDMAC_CH_LOCK_EN_1, .shift = 20, },
351 { .chnum = 45, .reg = IDMAC_CH_LOCK_EN_2, .shift = 0, },
352 { .chnum = 46, .reg = IDMAC_CH_LOCK_EN_2, .shift = 2, },
353 { .chnum = 47, .reg = IDMAC_CH_LOCK_EN_2, .shift = 4, },
354 { .chnum = 48, .reg = IDMAC_CH_LOCK_EN_2, .shift = 6, },
355 { .chnum = 49, .reg = IDMAC_CH_LOCK_EN_2, .shift = 8, },
356 { .chnum = 50, .reg = IDMAC_CH_LOCK_EN_2, .shift = 10, },
359 int ipu_idmac_lock_enable(struct ipuv3_channel *channel, int num_bursts)
361 struct ipu_soc *ipu = channel->ipu;
366 switch (num_bursts) {
369 bursts = 0x00; /* locking disabled */
384 for (i = 0; i < ARRAY_SIZE(idmac_lock_en_info); i++) {
385 if (channel->num == idmac_lock_en_info[i].chnum)
388 if (i >= ARRAY_SIZE(idmac_lock_en_info))
391 spin_lock_irqsave(&ipu->lock, flags);
393 regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg);
394 regval &= ~(0x03 << idmac_lock_en_info[i].shift);
395 regval |= (bursts << idmac_lock_en_info[i].shift);
396 ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg);
398 spin_unlock_irqrestore(&ipu->lock, flags);
402 EXPORT_SYMBOL_GPL(ipu_idmac_lock_enable);
404 int ipu_module_enable(struct ipu_soc *ipu, u32 mask)
406 unsigned long lock_flags;
409 spin_lock_irqsave(&ipu->lock, lock_flags);
411 val = ipu_cm_read(ipu, IPU_DISP_GEN);
413 if (mask & IPU_CONF_DI0_EN)
414 val |= IPU_DI0_COUNTER_RELEASE;
415 if (mask & IPU_CONF_DI1_EN)
416 val |= IPU_DI1_COUNTER_RELEASE;
418 ipu_cm_write(ipu, val, IPU_DISP_GEN);
420 val = ipu_cm_read(ipu, IPU_CONF);
422 ipu_cm_write(ipu, val, IPU_CONF);
424 spin_unlock_irqrestore(&ipu->lock, lock_flags);
428 EXPORT_SYMBOL_GPL(ipu_module_enable);
430 int ipu_module_disable(struct ipu_soc *ipu, u32 mask)
432 unsigned long lock_flags;
435 spin_lock_irqsave(&ipu->lock, lock_flags);
437 val = ipu_cm_read(ipu, IPU_CONF);
439 ipu_cm_write(ipu, val, IPU_CONF);
441 val = ipu_cm_read(ipu, IPU_DISP_GEN);
443 if (mask & IPU_CONF_DI0_EN)
444 val &= ~IPU_DI0_COUNTER_RELEASE;
445 if (mask & IPU_CONF_DI1_EN)
446 val &= ~IPU_DI1_COUNTER_RELEASE;
448 ipu_cm_write(ipu, val, IPU_DISP_GEN);
450 spin_unlock_irqrestore(&ipu->lock, lock_flags);
454 EXPORT_SYMBOL_GPL(ipu_module_disable);
456 int ipu_idmac_get_current_buffer(struct ipuv3_channel *channel)
458 struct ipu_soc *ipu = channel->ipu;
459 unsigned int chno = channel->num;
461 return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0;
463 EXPORT_SYMBOL_GPL(ipu_idmac_get_current_buffer);
465 bool ipu_idmac_buffer_is_ready(struct ipuv3_channel *channel, u32 buf_num)
467 struct ipu_soc *ipu = channel->ipu;
471 spin_lock_irqsave(&ipu->lock, flags);
474 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num));
477 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num));
480 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num));
483 spin_unlock_irqrestore(&ipu->lock, flags);
485 return ((reg & idma_mask(channel->num)) != 0);
487 EXPORT_SYMBOL_GPL(ipu_idmac_buffer_is_ready);
489 void ipu_idmac_select_buffer(struct ipuv3_channel *channel, u32 buf_num)
491 struct ipu_soc *ipu = channel->ipu;
492 unsigned int chno = channel->num;
495 spin_lock_irqsave(&ipu->lock, flags);
497 /* Mark buffer as ready. */
499 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
501 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
503 spin_unlock_irqrestore(&ipu->lock, flags);
505 EXPORT_SYMBOL_GPL(ipu_idmac_select_buffer);
507 void ipu_idmac_clear_buffer(struct ipuv3_channel *channel, u32 buf_num)
509 struct ipu_soc *ipu = channel->ipu;
510 unsigned int chno = channel->num;
513 spin_lock_irqsave(&ipu->lock, flags);
515 ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */
518 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno));
521 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno));
524 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno));
529 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
531 spin_unlock_irqrestore(&ipu->lock, flags);
533 EXPORT_SYMBOL_GPL(ipu_idmac_clear_buffer);
535 int ipu_idmac_enable_channel(struct ipuv3_channel *channel)
537 struct ipu_soc *ipu = channel->ipu;
541 spin_lock_irqsave(&ipu->lock, flags);
543 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
544 val |= idma_mask(channel->num);
545 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
547 spin_unlock_irqrestore(&ipu->lock, flags);
551 EXPORT_SYMBOL_GPL(ipu_idmac_enable_channel);
553 bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno)
555 return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno));
557 EXPORT_SYMBOL_GPL(ipu_idmac_channel_busy);
559 int ipu_idmac_wait_busy(struct ipuv3_channel *channel, int ms)
561 struct ipu_soc *ipu = channel->ipu;
562 unsigned long timeout;
564 timeout = jiffies + msecs_to_jiffies(ms);
565 while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) &
566 idma_mask(channel->num)) {
567 if (time_after(jiffies, timeout))
574 EXPORT_SYMBOL_GPL(ipu_idmac_wait_busy);
576 int ipu_wait_interrupt(struct ipu_soc *ipu, int irq, int ms)
578 unsigned long timeout;
580 timeout = jiffies + msecs_to_jiffies(ms);
581 ipu_cm_write(ipu, BIT(irq % 32), IPU_INT_STAT(irq / 32));
582 while (!(ipu_cm_read(ipu, IPU_INT_STAT(irq / 32) & BIT(irq % 32)))) {
583 if (time_after(jiffies, timeout))
590 EXPORT_SYMBOL_GPL(ipu_wait_interrupt);
592 int ipu_idmac_disable_channel(struct ipuv3_channel *channel)
594 struct ipu_soc *ipu = channel->ipu;
598 spin_lock_irqsave(&ipu->lock, flags);
600 /* Disable DMA channel(s) */
601 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num));
602 val &= ~idma_mask(channel->num);
603 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num));
605 __ipu_idmac_reset_current_buffer(channel);
607 /* Set channel buffers NOT to be ready */
608 ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */
610 if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) &
611 idma_mask(channel->num)) {
612 ipu_cm_write(ipu, idma_mask(channel->num),
613 IPU_CHA_BUF0_RDY(channel->num));
616 if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) &
617 idma_mask(channel->num)) {
618 ipu_cm_write(ipu, idma_mask(channel->num),
619 IPU_CHA_BUF1_RDY(channel->num));
622 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */
624 /* Reset the double buffer */
625 val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num));
626 val &= ~idma_mask(channel->num);
627 ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num));
629 spin_unlock_irqrestore(&ipu->lock, flags);
633 EXPORT_SYMBOL_GPL(ipu_idmac_disable_channel);
636 * The imx6 rev. D TRM says that enabling the WM feature will increase
637 * a channel's priority. Refer to Table 36-8 Calculated priority value.
638 * The sub-module that is the sink or source for the channel must enable
639 * watermark signal for this to take effect (SMFC_WM for instance).
641 void ipu_idmac_enable_watermark(struct ipuv3_channel *channel, bool enable)
643 struct ipu_soc *ipu = channel->ipu;
647 spin_lock_irqsave(&ipu->lock, flags);
649 val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num));
651 val |= 1 << (channel->num % 32);
653 val &= ~(1 << (channel->num % 32));
654 ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num));
656 spin_unlock_irqrestore(&ipu->lock, flags);
658 EXPORT_SYMBOL_GPL(ipu_idmac_enable_watermark);
660 static int ipu_memory_reset(struct ipu_soc *ipu)
662 unsigned long timeout;
664 ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST);
666 timeout = jiffies + msecs_to_jiffies(1000);
667 while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) {
668 if (time_after(jiffies, timeout))
677 * Set the source mux for the given CSI. Selects either parallel or
680 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2)
685 mask = (csi_id == 1) ? IPU_CONF_CSI1_DATA_SOURCE :
686 IPU_CONF_CSI0_DATA_SOURCE;
688 spin_lock_irqsave(&ipu->lock, flags);
690 val = ipu_cm_read(ipu, IPU_CONF);
695 ipu_cm_write(ipu, val, IPU_CONF);
697 spin_unlock_irqrestore(&ipu->lock, flags);
699 EXPORT_SYMBOL_GPL(ipu_set_csi_src_mux);
702 * Set the source mux for the IC. Selects either CSI[01] or the VDI.
704 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi)
709 spin_lock_irqsave(&ipu->lock, flags);
711 val = ipu_cm_read(ipu, IPU_CONF);
713 val |= IPU_CONF_IC_INPUT;
715 val &= ~IPU_CONF_IC_INPUT;
717 val |= IPU_CONF_CSI_SEL;
719 val &= ~IPU_CONF_CSI_SEL;
721 ipu_cm_write(ipu, val, IPU_CONF);
723 spin_unlock_irqrestore(&ipu->lock, flags);
725 EXPORT_SYMBOL_GPL(ipu_set_ic_src_mux);
729 unsigned long cm_ofs;
730 unsigned long cpmem_ofs;
731 unsigned long srm_ofs;
732 unsigned long tpm_ofs;
733 unsigned long csi0_ofs;
734 unsigned long csi1_ofs;
735 unsigned long ic_ofs;
736 unsigned long disp0_ofs;
737 unsigned long disp1_ofs;
738 unsigned long dc_tmpl_ofs;
739 unsigned long vdi_ofs;
740 enum ipuv3_type type;
743 static struct ipu_devtype ipu_type_imx51 = {
745 .cm_ofs = 0x1e000000,
746 .cpmem_ofs = 0x1f000000,
747 .srm_ofs = 0x1f040000,
748 .tpm_ofs = 0x1f060000,
749 .csi0_ofs = 0x1f030000,
750 .csi1_ofs = 0x1f038000,
751 .ic_ofs = 0x1e020000,
752 .disp0_ofs = 0x1e040000,
753 .disp1_ofs = 0x1e048000,
754 .dc_tmpl_ofs = 0x1f080000,
755 .vdi_ofs = 0x1e068000,
759 static struct ipu_devtype ipu_type_imx53 = {
761 .cm_ofs = 0x06000000,
762 .cpmem_ofs = 0x07000000,
763 .srm_ofs = 0x07040000,
764 .tpm_ofs = 0x07060000,
765 .csi0_ofs = 0x07030000,
766 .csi1_ofs = 0x07038000,
767 .ic_ofs = 0x06020000,
768 .disp0_ofs = 0x06040000,
769 .disp1_ofs = 0x06048000,
770 .dc_tmpl_ofs = 0x07080000,
771 .vdi_ofs = 0x06068000,
775 static struct ipu_devtype ipu_type_imx6q = {
777 .cm_ofs = 0x00200000,
778 .cpmem_ofs = 0x00300000,
779 .srm_ofs = 0x00340000,
780 .tpm_ofs = 0x00360000,
781 .csi0_ofs = 0x00230000,
782 .csi1_ofs = 0x00238000,
783 .ic_ofs = 0x00220000,
784 .disp0_ofs = 0x00240000,
785 .disp1_ofs = 0x00248000,
786 .dc_tmpl_ofs = 0x00380000,
787 .vdi_ofs = 0x00268000,
791 static const struct of_device_id imx_ipu_dt_ids[] = {
792 { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, },
793 { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, },
794 { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, },
797 MODULE_DEVICE_TABLE(of, imx_ipu_dt_ids);
799 static int ipu_submodules_init(struct ipu_soc *ipu,
800 struct platform_device *pdev, unsigned long ipu_base,
805 struct device *dev = &pdev->dev;
806 const struct ipu_devtype *devtype = ipu->devtype;
808 ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs);
814 ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs,
815 IPU_CONF_CSI0_EN, ipu_clk);
821 ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs,
822 IPU_CONF_CSI1_EN, ipu_clk);
828 ret = ipu_ic_init(ipu, dev,
829 ipu_base + devtype->ic_ofs,
830 ipu_base + devtype->tpm_ofs);
836 ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs,
837 IPU_CONF_DI0_EN, ipu_clk);
843 ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs,
844 IPU_CONF_DI1_EN, ipu_clk);
850 ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs +
851 IPU_CM_DC_REG_OFS, ipu_base + devtype->dc_tmpl_ofs);
853 unit = "dc_template";
857 ret = ipu_dmfc_init(ipu, dev, ipu_base +
858 devtype->cm_ofs + IPU_CM_DMFC_REG_OFS, ipu_clk);
864 ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs);
870 ret = ipu_smfc_init(ipu, dev, ipu_base +
871 devtype->cm_ofs + IPU_CM_SMFC_REG_OFS);
892 ipu_csi_exit(ipu, 1);
894 ipu_csi_exit(ipu, 0);
898 dev_err(&pdev->dev, "init %s failed with %d\n", unit, ret);
902 static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs)
904 unsigned long status;
907 for (i = 0; i < num_regs; i++) {
909 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i]));
910 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i]));
912 for_each_set_bit(bit, &status, 32) {
913 irq = irq_linear_revmap(ipu->domain,
916 generic_handle_irq(irq);
921 static void ipu_irq_handler(struct irq_desc *desc)
923 struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
924 struct irq_chip *chip = irq_desc_get_chip(desc);
925 const int int_reg[] = { 0, 1, 2, 3, 10, 11, 12, 13, 14};
927 chained_irq_enter(chip, desc);
929 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
931 chained_irq_exit(chip, desc);
934 static void ipu_err_irq_handler(struct irq_desc *desc)
936 struct ipu_soc *ipu = irq_desc_get_handler_data(desc);
937 struct irq_chip *chip = irq_desc_get_chip(desc);
938 const int int_reg[] = { 4, 5, 8, 9};
940 chained_irq_enter(chip, desc);
942 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg));
944 chained_irq_exit(chip, desc);
947 int ipu_map_irq(struct ipu_soc *ipu, int irq)
951 virq = irq_linear_revmap(ipu->domain, irq);
953 virq = irq_create_mapping(ipu->domain, irq);
957 EXPORT_SYMBOL_GPL(ipu_map_irq);
959 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel,
960 enum ipu_channel_irq irq_type)
962 return ipu_map_irq(ipu, irq_type + channel->num);
964 EXPORT_SYMBOL_GPL(ipu_idmac_channel_irq);
966 static void ipu_submodules_exit(struct ipu_soc *ipu)
975 ipu_csi_exit(ipu, 1);
976 ipu_csi_exit(ipu, 0);
980 static int platform_remove_devices_fn(struct device *dev, void *unused)
982 struct platform_device *pdev = to_platform_device(dev);
984 platform_device_unregister(pdev);
989 static void platform_device_unregister_children(struct platform_device *pdev)
991 device_for_each_child(&pdev->dev, NULL, platform_remove_devices_fn);
994 struct ipu_platform_reg {
995 struct ipu_client_platformdata pdata;
999 /* These must be in the order of the corresponding device tree port nodes */
1000 static const struct ipu_platform_reg client_reg[] = {
1004 .dma[0] = IPUV3_CHANNEL_CSI0,
1007 .name = "imx-ipuv3-camera",
1011 .dma[0] = IPUV3_CHANNEL_CSI1,
1014 .name = "imx-ipuv3-camera",
1019 .dp = IPU_DP_FLOW_SYNC_BG,
1020 .dma[0] = IPUV3_CHANNEL_MEM_BG_SYNC,
1021 .dma[1] = IPUV3_CHANNEL_MEM_FG_SYNC,
1023 .name = "imx-ipuv3-crtc",
1029 .dma[0] = IPUV3_CHANNEL_MEM_DC_SYNC,
1032 .name = "imx-ipuv3-crtc",
1036 static DEFINE_MUTEX(ipu_client_id_mutex);
1037 static int ipu_client_id;
1039 static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base)
1041 struct device *dev = ipu->dev;
1045 mutex_lock(&ipu_client_id_mutex);
1047 ipu_client_id += ARRAY_SIZE(client_reg);
1048 mutex_unlock(&ipu_client_id_mutex);
1050 for (i = 0; i < ARRAY_SIZE(client_reg); i++) {
1051 const struct ipu_platform_reg *reg = &client_reg[i];
1052 struct platform_device *pdev;
1054 pdev = platform_device_alloc(reg->name, id++);
1060 pdev->dev.parent = dev;
1062 /* Associate subdevice with the corresponding port node */
1063 pdev->dev.of_node = of_graph_get_port_by_id(dev->of_node, i);
1064 if (!pdev->dev.of_node) {
1065 dev_err(dev, "missing port@%d node in %s\n", i,
1066 dev->of_node->full_name);
1071 ret = platform_device_add_data(pdev, ®->pdata,
1072 sizeof(reg->pdata));
1074 ret = platform_device_add(pdev);
1076 platform_device_put(pdev);
1084 platform_device_unregister_children(to_platform_device(dev));
1090 static int ipu_irq_init(struct ipu_soc *ipu)
1092 struct irq_chip_generic *gc;
1093 struct irq_chip_type *ct;
1094 unsigned long unused[IPU_NUM_IRQS / 32] = {
1095 0x400100d0, 0xffe000fd,
1096 0x400100d0, 0xffe000fd,
1097 0x400100d0, 0xffe000fd,
1098 0x4077ffff, 0xffe7e1fd,
1099 0x23fffffe, 0x8880fff0,
1100 0xf98fe7d0, 0xfff81fff,
1101 0x400100d0, 0xffe000fd,
1106 ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS,
1107 &irq_generic_chip_ops, ipu);
1109 dev_err(ipu->dev, "failed to add irq domain\n");
1113 ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU",
1114 handle_level_irq, 0, 0, 0);
1116 dev_err(ipu->dev, "failed to alloc generic irq chips\n");
1117 irq_domain_remove(ipu->domain);
1121 for (i = 0; i < IPU_NUM_IRQS; i += 32)
1122 ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32));
1124 for (i = 0; i < IPU_NUM_IRQS; i += 32) {
1125 gc = irq_get_domain_generic_chip(ipu->domain, i);
1126 gc->reg_base = ipu->cm_reg;
1127 gc->unused = unused[i / 32];
1128 ct = gc->chip_types;
1129 ct->chip.irq_ack = irq_gc_ack_set_bit;
1130 ct->chip.irq_mask = irq_gc_mask_clr_bit;
1131 ct->chip.irq_unmask = irq_gc_mask_set_bit;
1132 ct->regs.ack = IPU_INT_STAT(i / 32);
1133 ct->regs.mask = IPU_INT_CTRL(i / 32);
1136 irq_set_chained_handler_and_data(ipu->irq_sync, ipu_irq_handler, ipu);
1137 irq_set_chained_handler_and_data(ipu->irq_err, ipu_err_irq_handler,
1143 static void ipu_irq_exit(struct ipu_soc *ipu)
1147 irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL);
1148 irq_set_chained_handler_and_data(ipu->irq_sync, NULL, NULL);
1150 /* TODO: remove irq_domain_generic_chips */
1152 for (i = 0; i < IPU_NUM_IRQS; i++) {
1153 irq = irq_linear_revmap(ipu->domain, i);
1155 irq_dispose_mapping(irq);
1158 irq_domain_remove(ipu->domain);
1161 void ipu_dump(struct ipu_soc *ipu)
1165 dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n",
1166 ipu_cm_read(ipu, IPU_CONF));
1167 dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n",
1168 ipu_idmac_read(ipu, IDMAC_CONF));
1169 dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n",
1170 ipu_idmac_read(ipu, IDMAC_CHA_EN(0)));
1171 dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n",
1172 ipu_idmac_read(ipu, IDMAC_CHA_EN(32)));
1173 dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n",
1174 ipu_idmac_read(ipu, IDMAC_CHA_PRI(0)));
1175 dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n",
1176 ipu_idmac_read(ipu, IDMAC_CHA_PRI(32)));
1177 dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n",
1178 ipu_idmac_read(ipu, IDMAC_BAND_EN(0)));
1179 dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n",
1180 ipu_idmac_read(ipu, IDMAC_BAND_EN(32)));
1181 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n",
1182 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0)));
1183 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n",
1184 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32)));
1185 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n",
1186 ipu_cm_read(ipu, IPU_FS_PROC_FLOW1));
1187 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n",
1188 ipu_cm_read(ipu, IPU_FS_PROC_FLOW2));
1189 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n",
1190 ipu_cm_read(ipu, IPU_FS_PROC_FLOW3));
1191 dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n",
1192 ipu_cm_read(ipu, IPU_FS_DISP_FLOW1));
1193 for (i = 0; i < 15; i++)
1194 dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i,
1195 ipu_cm_read(ipu, IPU_INT_CTRL(i)));
1197 EXPORT_SYMBOL_GPL(ipu_dump);
1199 static int ipu_probe(struct platform_device *pdev)
1201 const struct of_device_id *of_id =
1202 of_match_device(imx_ipu_dt_ids, &pdev->dev);
1203 struct ipu_soc *ipu;
1204 struct resource *res;
1205 unsigned long ipu_base;
1206 int i, ret, irq_sync, irq_err;
1207 const struct ipu_devtype *devtype;
1209 devtype = of_id->data;
1211 irq_sync = platform_get_irq(pdev, 0);
1212 irq_err = platform_get_irq(pdev, 1);
1213 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1215 dev_dbg(&pdev->dev, "irq_sync: %d irq_err: %d\n",
1218 if (!res || irq_sync < 0 || irq_err < 0)
1221 ipu_base = res->start;
1223 ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL);
1227 for (i = 0; i < 64; i++)
1228 ipu->channel[i].ipu = ipu;
1229 ipu->devtype = devtype;
1230 ipu->ipu_type = devtype->type;
1232 spin_lock_init(&ipu->lock);
1233 mutex_init(&ipu->channel_lock);
1235 dev_dbg(&pdev->dev, "cm_reg: 0x%08lx\n",
1236 ipu_base + devtype->cm_ofs);
1237 dev_dbg(&pdev->dev, "idmac: 0x%08lx\n",
1238 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS);
1239 dev_dbg(&pdev->dev, "cpmem: 0x%08lx\n",
1240 ipu_base + devtype->cpmem_ofs);
1241 dev_dbg(&pdev->dev, "csi0: 0x%08lx\n",
1242 ipu_base + devtype->csi0_ofs);
1243 dev_dbg(&pdev->dev, "csi1: 0x%08lx\n",
1244 ipu_base + devtype->csi1_ofs);
1245 dev_dbg(&pdev->dev, "ic: 0x%08lx\n",
1246 ipu_base + devtype->ic_ofs);
1247 dev_dbg(&pdev->dev, "disp0: 0x%08lx\n",
1248 ipu_base + devtype->disp0_ofs);
1249 dev_dbg(&pdev->dev, "disp1: 0x%08lx\n",
1250 ipu_base + devtype->disp1_ofs);
1251 dev_dbg(&pdev->dev, "srm: 0x%08lx\n",
1252 ipu_base + devtype->srm_ofs);
1253 dev_dbg(&pdev->dev, "tpm: 0x%08lx\n",
1254 ipu_base + devtype->tpm_ofs);
1255 dev_dbg(&pdev->dev, "dc: 0x%08lx\n",
1256 ipu_base + devtype->cm_ofs + IPU_CM_DC_REG_OFS);
1257 dev_dbg(&pdev->dev, "ic: 0x%08lx\n",
1258 ipu_base + devtype->cm_ofs + IPU_CM_IC_REG_OFS);
1259 dev_dbg(&pdev->dev, "dmfc: 0x%08lx\n",
1260 ipu_base + devtype->cm_ofs + IPU_CM_DMFC_REG_OFS);
1261 dev_dbg(&pdev->dev, "vdi: 0x%08lx\n",
1262 ipu_base + devtype->vdi_ofs);
1264 ipu->cm_reg = devm_ioremap(&pdev->dev,
1265 ipu_base + devtype->cm_ofs, PAGE_SIZE);
1266 ipu->idmac_reg = devm_ioremap(&pdev->dev,
1267 ipu_base + devtype->cm_ofs + IPU_CM_IDMAC_REG_OFS,
1270 if (!ipu->cm_reg || !ipu->idmac_reg)
1273 ipu->clk = devm_clk_get(&pdev->dev, "bus");
1274 if (IS_ERR(ipu->clk)) {
1275 ret = PTR_ERR(ipu->clk);
1276 dev_err(&pdev->dev, "clk_get failed with %d", ret);
1280 platform_set_drvdata(pdev, ipu);
1282 ret = clk_prepare_enable(ipu->clk);
1284 dev_err(&pdev->dev, "clk_prepare_enable failed: %d\n", ret);
1288 ipu->dev = &pdev->dev;
1289 ipu->irq_sync = irq_sync;
1290 ipu->irq_err = irq_err;
1292 ret = ipu_irq_init(ipu);
1294 goto out_failed_irq;
1296 ret = device_reset(&pdev->dev);
1298 dev_err(&pdev->dev, "failed to reset: %d\n", ret);
1299 goto out_failed_reset;
1301 ret = ipu_memory_reset(ipu);
1303 goto out_failed_reset;
1305 /* Set MCU_T to divide MCU access window into 2 */
1306 ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18),
1309 ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk);
1311 goto failed_submodules_init;
1313 ret = ipu_add_client_devices(ipu, ipu_base);
1315 dev_err(&pdev->dev, "adding client devices failed with %d\n",
1317 goto failed_add_clients;
1320 dev_info(&pdev->dev, "%s probed\n", devtype->name);
1325 ipu_submodules_exit(ipu);
1326 failed_submodules_init:
1330 clk_disable_unprepare(ipu->clk);
1334 static int ipu_remove(struct platform_device *pdev)
1336 struct ipu_soc *ipu = platform_get_drvdata(pdev);
1338 platform_device_unregister_children(pdev);
1339 ipu_submodules_exit(ipu);
1342 clk_disable_unprepare(ipu->clk);
1347 static struct platform_driver imx_ipu_driver = {
1349 .name = "imx-ipuv3",
1350 .of_match_table = imx_ipu_dt_ids,
1353 .remove = ipu_remove,
1356 module_platform_driver(imx_ipu_driver);
1358 MODULE_ALIAS("platform:imx-ipuv3");
1359 MODULE_DESCRIPTION("i.MX IPU v3 driver");
1360 MODULE_AUTHOR("Sascha Hauer <s.hauer@pengutronix.de>");
1361 MODULE_LICENSE("GPL");