2 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
16 #include <linux/export.h>
17 #include <linux/module.h>
18 #include <linux/types.h>
19 #include <linux/errno.h>
20 #include <linux/delay.h>
21 #include <linux/interrupt.h>
24 #include <video/imx-ipu-v3.h>
27 #define DC_MAP_CONF_PTR(n) (0x108 + ((n) & ~0x1) * 2)
28 #define DC_MAP_CONF_VAL(n) (0x144 + ((n) & ~0x1) * 2)
33 #define DC_EVT_NFIELD 3
35 #define DC_EVT_EOFIELD 5
36 #define DC_EVT_NEW_ADDR 6
37 #define DC_EVT_NEW_CHAN 7
38 #define DC_EVT_NEW_DATA 8
40 #define DC_EVT_NEW_ADDR_W_0 0
41 #define DC_EVT_NEW_ADDR_W_1 1
42 #define DC_EVT_NEW_CHAN_W_0 2
43 #define DC_EVT_NEW_CHAN_W_1 3
44 #define DC_EVT_NEW_DATA_W_0 4
45 #define DC_EVT_NEW_DATA_W_1 5
46 #define DC_EVT_NEW_ADDR_R_0 6
47 #define DC_EVT_NEW_ADDR_R_1 7
48 #define DC_EVT_NEW_CHAN_R_0 8
49 #define DC_EVT_NEW_CHAN_R_1 9
50 #define DC_EVT_NEW_DATA_R_0 10
51 #define DC_EVT_NEW_DATA_R_1 11
53 #define DC_WR_CH_CONF 0x0
54 #define DC_WR_CH_ADDR 0x4
55 #define DC_RL_CH(evt) (8 + ((evt) & ~0x1) * 2)
58 #define DC_DISP_CONF1(disp) (0xd8 + (disp) * 4)
59 #define DC_DISP_CONF2(disp) (0xe8 + (disp) * 4)
62 #define WROD(lf) (0x18 | ((lf) << 1))
67 #define NULL_WAVE (-1)
69 #define DC_GEN_SYNC_1_6_SYNC (2 << 1)
70 #define DC_GEN_SYNC_PRIORITY_1 (1 << 7)
72 #define DC_WR_CH_CONF_WORD_SIZE_8 (0 << 0)
73 #define DC_WR_CH_CONF_WORD_SIZE_16 (1 << 0)
74 #define DC_WR_CH_CONF_WORD_SIZE_24 (2 << 0)
75 #define DC_WR_CH_CONF_WORD_SIZE_32 (3 << 0)
76 #define DC_WR_CH_CONF_DISP_ID_PARALLEL(i) (((i) & 0x1) << 3)
77 #define DC_WR_CH_CONF_DISP_ID_SERIAL (2 << 3)
78 #define DC_WR_CH_CONF_DISP_ID_ASYNC (3 << 4)
79 #define DC_WR_CH_CONF_FIELD_MODE (1 << 9)
80 #define DC_WR_CH_CONF_PROG_TYPE_NORMAL (4 << 5)
81 #define DC_WR_CH_CONF_PROG_TYPE_MASK (7 << 5)
82 #define DC_WR_CH_CONF_PROG_DI_ID (1 << 2)
83 #define DC_WR_CH_CONF_PROG_DISP_ID(i) (((i) & 0x1) << 3)
85 #define IPU_DC_NUM_CHANNELS 10
92 IPU_DC_MAP_GBR24, /* TVEv2 */
99 /* The display interface number assigned to this dc channel */
102 struct ipu_dc_priv *priv;
108 void __iomem *dc_reg;
109 void __iomem *dc_tmpl_reg;
112 struct ipu_dc channels[IPU_DC_NUM_CHANNELS];
114 struct completion comp;
120 static void dc_link_event(struct ipu_dc *dc, int event, int addr, int priority)
124 reg = readl(dc->base + DC_RL_CH(event));
125 reg &= ~(0xffff << (16 * (event & 0x1)));
126 reg |= ((addr << 8) | priority) << (16 * (event & 0x1));
127 writel(reg, dc->base + DC_RL_CH(event));
130 static void dc_write_tmpl(struct ipu_dc *dc, int word, u32 opcode, u32 operand,
131 int map, int wave, int glue, int sync, int stop)
133 struct ipu_dc_priv *priv = dc->priv;
136 if (opcode == WCLK) {
137 reg1 = (operand << 20) & 0xfff00000;
138 reg2 = operand >> 12 | opcode << 1 | stop << 9;
139 } else if (opcode == WRG) {
140 reg1 = sync | glue << 4 | ++wave << 11 | ((operand << 15) & 0xffff8000);
141 reg2 = operand >> 17 | opcode << 7 | stop << 9;
143 reg1 = sync | glue << 4 | ++wave << 11 | ++map << 15 | ((operand << 20) & 0xfff00000);
144 reg2 = operand >> 12 | opcode << 4 | stop << 9;
146 writel(reg1, priv->dc_tmpl_reg + word * 8);
147 writel(reg2, priv->dc_tmpl_reg + word * 8 + 4);
150 static int ipu_bus_format_to_map(u32 fmt)
153 case MEDIA_BUS_FMT_RGB888_1X24:
154 return IPU_DC_MAP_RGB24;
155 case MEDIA_BUS_FMT_RGB565_1X16:
156 return IPU_DC_MAP_RGB565;
157 case MEDIA_BUS_FMT_GBR888_1X24:
158 return IPU_DC_MAP_GBR24;
159 case MEDIA_BUS_FMT_RGB666_1X18:
160 return IPU_DC_MAP_BGR666;
161 case MEDIA_BUS_FMT_RGB666_1X24_CPADHI:
162 return IPU_DC_MAP_LVDS666;
163 case MEDIA_BUS_FMT_BGR888_1X24:
164 return IPU_DC_MAP_BGR24;
170 int ipu_dc_init_sync(struct ipu_dc *dc, struct ipu_di *di, bool interlaced,
171 u32 bus_format, u32 width)
173 struct ipu_dc_priv *priv = dc->priv;
177 dc->di = ipu_di_get_num(di);
179 map = ipu_bus_format_to_map(bus_format);
181 dev_dbg(priv->dev, "IPU_DISP: No MAP\n");
193 dc_link_event(dc, DC_EVT_NL, addr, 3);
194 dc_link_event(dc, DC_EVT_EOL, addr, 2);
195 dc_link_event(dc, DC_EVT_NEW_DATA, addr, 1);
197 /* Init template microcode */
198 dc_write_tmpl(dc, addr, WROD(0), 0, map, SYNC_WAVE, 0, 6, 1);
201 dc_link_event(dc, DC_EVT_NL, 2, 3);
202 dc_link_event(dc, DC_EVT_EOL, 3, 2);
203 dc_link_event(dc, DC_EVT_NEW_DATA, 1, 1);
204 /* Init template microcode */
205 dc_write_tmpl(dc, 2, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
206 dc_write_tmpl(dc, 3, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);
207 dc_write_tmpl(dc, 4, WRG, 0, map, NULL_WAVE, 0, 0, 1);
208 dc_write_tmpl(dc, 1, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
210 dc_link_event(dc, DC_EVT_NL, 5, 3);
211 dc_link_event(dc, DC_EVT_EOL, 6, 2);
212 dc_link_event(dc, DC_EVT_NEW_DATA, 8, 1);
213 /* Init template microcode */
214 dc_write_tmpl(dc, 5, WROD(0), 0, map, SYNC_WAVE, 8, 5, 1);
215 dc_write_tmpl(dc, 6, WROD(0), 0, map, SYNC_WAVE, 4, 5, 0);
216 dc_write_tmpl(dc, 7, WRG, 0, map, NULL_WAVE, 0, 0, 1);
217 dc_write_tmpl(dc, 8, WROD(0), 0, map, SYNC_WAVE, 0, 5, 1);
220 dc_link_event(dc, DC_EVT_NF, 0, 0);
221 dc_link_event(dc, DC_EVT_NFIELD, 0, 0);
222 dc_link_event(dc, DC_EVT_EOF, 0, 0);
223 dc_link_event(dc, DC_EVT_EOFIELD, 0, 0);
224 dc_link_event(dc, DC_EVT_NEW_CHAN, 0, 0);
225 dc_link_event(dc, DC_EVT_NEW_ADDR, 0, 0);
227 reg = readl(dc->base + DC_WR_CH_CONF);
229 reg |= DC_WR_CH_CONF_FIELD_MODE;
231 reg &= ~DC_WR_CH_CONF_FIELD_MODE;
232 writel(reg, dc->base + DC_WR_CH_CONF);
234 writel(0x0, dc->base + DC_WR_CH_ADDR);
235 writel(width, priv->dc_reg + DC_DISP_CONF2(dc->di));
239 EXPORT_SYMBOL_GPL(ipu_dc_init_sync);
241 void ipu_dc_enable(struct ipu_soc *ipu)
243 struct ipu_dc_priv *priv = ipu->dc_priv;
245 mutex_lock(&priv->mutex);
247 if (!priv->use_count)
248 ipu_module_enable(priv->ipu, IPU_CONF_DC_EN);
252 mutex_unlock(&priv->mutex);
254 EXPORT_SYMBOL_GPL(ipu_dc_enable);
256 void ipu_dc_enable_channel(struct ipu_dc *dc)
263 reg = readl(dc->base + DC_WR_CH_CONF);
264 reg |= DC_WR_CH_CONF_PROG_TYPE_NORMAL;
265 writel(reg, dc->base + DC_WR_CH_CONF);
267 EXPORT_SYMBOL_GPL(ipu_dc_enable_channel);
269 static irqreturn_t dc_irq_handler(int irq, void *dev_id)
271 struct ipu_dc *dc = dev_id;
274 reg = readl(dc->base + DC_WR_CH_CONF);
275 reg &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
276 writel(reg, dc->base + DC_WR_CH_CONF);
278 /* The Freescale BSP kernel clears DIx_COUNTER_RELEASE here */
280 complete(&dc->priv->comp);
284 void ipu_dc_disable_channel(struct ipu_dc *dc)
286 struct ipu_dc_priv *priv = dc->priv;
291 /* TODO: Handle MEM_FG_SYNC differently from MEM_BG_SYNC */
294 else if (dc->chno == 5)
299 init_completion(&priv->comp);
301 ret = wait_for_completion_timeout(&priv->comp, msecs_to_jiffies(50));
304 dev_warn(priv->dev, "DC stop timeout after 50 ms\n");
306 val = readl(dc->base + DC_WR_CH_CONF);
307 val &= ~DC_WR_CH_CONF_PROG_TYPE_MASK;
308 writel(val, dc->base + DC_WR_CH_CONF);
311 EXPORT_SYMBOL_GPL(ipu_dc_disable_channel);
313 void ipu_dc_disable(struct ipu_soc *ipu)
315 struct ipu_dc_priv *priv = ipu->dc_priv;
317 mutex_lock(&priv->mutex);
320 if (!priv->use_count)
321 ipu_module_disable(priv->ipu, IPU_CONF_DC_EN);
323 if (priv->use_count < 0)
326 mutex_unlock(&priv->mutex);
328 EXPORT_SYMBOL_GPL(ipu_dc_disable);
330 static void ipu_dc_map_config(struct ipu_dc_priv *priv, enum ipu_dc_map map,
331 int byte_num, int offset, int mask)
333 int ptr = map * 3 + byte_num;
336 reg = readl(priv->dc_reg + DC_MAP_CONF_VAL(ptr));
337 reg &= ~(0xffff << (16 * (ptr & 0x1)));
338 reg |= ((offset << 8) | mask) << (16 * (ptr & 0x1));
339 writel(reg, priv->dc_reg + DC_MAP_CONF_VAL(ptr));
341 reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
342 reg &= ~(0x1f << ((16 * (map & 0x1)) + (5 * byte_num)));
343 reg |= ptr << ((16 * (map & 0x1)) + (5 * byte_num));
344 writel(reg, priv->dc_reg + DC_MAP_CONF_PTR(map));
347 static void ipu_dc_map_clear(struct ipu_dc_priv *priv, int map)
349 u32 reg = readl(priv->dc_reg + DC_MAP_CONF_PTR(map));
351 writel(reg & ~(0xffff << (16 * (map & 0x1))),
352 priv->dc_reg + DC_MAP_CONF_PTR(map));
355 struct ipu_dc *ipu_dc_get(struct ipu_soc *ipu, int channel)
357 struct ipu_dc_priv *priv = ipu->dc_priv;
360 if (channel >= IPU_DC_NUM_CHANNELS)
361 return ERR_PTR(-ENODEV);
363 dc = &priv->channels[channel];
365 mutex_lock(&priv->mutex);
368 mutex_unlock(&priv->mutex);
369 return ERR_PTR(-EBUSY);
374 mutex_unlock(&priv->mutex);
378 EXPORT_SYMBOL_GPL(ipu_dc_get);
380 void ipu_dc_put(struct ipu_dc *dc)
382 struct ipu_dc_priv *priv = dc->priv;
384 mutex_lock(&priv->mutex);
386 mutex_unlock(&priv->mutex);
388 EXPORT_SYMBOL_GPL(ipu_dc_put);
390 int ipu_dc_init(struct ipu_soc *ipu, struct device *dev,
391 unsigned long base, unsigned long template_base)
393 struct ipu_dc_priv *priv;
394 static int channel_offsets[] = { 0, 0x1c, 0x38, 0x54, 0x58, 0x5c,
395 0x78, 0, 0x94, 0xb4};
398 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
402 mutex_init(&priv->mutex);
406 priv->dc_reg = devm_ioremap(dev, base, PAGE_SIZE);
407 priv->dc_tmpl_reg = devm_ioremap(dev, template_base, PAGE_SIZE);
408 if (!priv->dc_reg || !priv->dc_tmpl_reg)
411 for (i = 0; i < IPU_DC_NUM_CHANNELS; i++) {
412 priv->channels[i].chno = i;
413 priv->channels[i].priv = priv;
414 priv->channels[i].base = priv->dc_reg + channel_offsets[i];
417 priv->dc_irq = ipu_map_irq(ipu, IPU_IRQ_DC_FC_1);
420 ret = devm_request_irq(dev, priv->dc_irq, dc_irq_handler, 0, NULL,
424 disable_irq(priv->dc_irq);
425 priv->dp_irq = ipu_map_irq(ipu, IPU_IRQ_DP_SF_END);
428 ret = devm_request_irq(dev, priv->dp_irq, dc_irq_handler, 0, NULL,
432 disable_irq(priv->dp_irq);
434 writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(1) |
435 DC_WR_CH_CONF_PROG_DI_ID,
436 priv->channels[1].base + DC_WR_CH_CONF);
437 writel(DC_WR_CH_CONF_WORD_SIZE_24 | DC_WR_CH_CONF_DISP_ID_PARALLEL(0),
438 priv->channels[5].base + DC_WR_CH_CONF);
440 writel(DC_GEN_SYNC_1_6_SYNC | DC_GEN_SYNC_PRIORITY_1,
441 priv->dc_reg + DC_GEN);
445 dev_dbg(dev, "DC base: 0x%08lx template base: 0x%08lx\n",
446 base, template_base);
449 ipu_dc_map_clear(priv, IPU_DC_MAP_RGB24);
450 ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 0, 7, 0xff); /* blue */
451 ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 1, 15, 0xff); /* green */
452 ipu_dc_map_config(priv, IPU_DC_MAP_RGB24, 2, 23, 0xff); /* red */
455 ipu_dc_map_clear(priv, IPU_DC_MAP_RGB565);
456 ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 0, 4, 0xf8); /* blue */
457 ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 1, 10, 0xfc); /* green */
458 ipu_dc_map_config(priv, IPU_DC_MAP_RGB565, 2, 15, 0xf8); /* red */
461 ipu_dc_map_clear(priv, IPU_DC_MAP_GBR24);
462 ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 2, 15, 0xff); /* green */
463 ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 1, 7, 0xff); /* blue */
464 ipu_dc_map_config(priv, IPU_DC_MAP_GBR24, 0, 23, 0xff); /* red */
467 ipu_dc_map_clear(priv, IPU_DC_MAP_BGR666);
468 ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 0, 5, 0xfc); /* blue */
469 ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 1, 11, 0xfc); /* green */
470 ipu_dc_map_config(priv, IPU_DC_MAP_BGR666, 2, 17, 0xfc); /* red */
473 ipu_dc_map_clear(priv, IPU_DC_MAP_LVDS666);
474 ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 0, 5, 0xfc); /* blue */
475 ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 1, 13, 0xfc); /* green */
476 ipu_dc_map_config(priv, IPU_DC_MAP_LVDS666, 2, 21, 0xfc); /* red */
479 ipu_dc_map_clear(priv, IPU_DC_MAP_BGR24);
480 ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 2, 7, 0xff); /* red */
481 ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 1, 15, 0xff); /* green */
482 ipu_dc_map_config(priv, IPU_DC_MAP_BGR24, 0, 23, 0xff); /* blue */
487 void ipu_dc_exit(struct ipu_soc *ipu)