2 * Copyright (c) 2010 Sascha Hauer <s.hauer@pengutronix.de>
3 * Copyright (C) 2005-2009 Freescale Semiconductor, Inc.
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License as published by the
7 * Free Software Foundation; either version 2 of the License, or (at your
8 * option) any later version.
10 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
12 * or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
15 #include <linux/export.h>
16 #include <linux/types.h>
17 #include <linux/errno.h>
20 #include <video/imx-ipu-v3.h>
23 #define DMFC_RD_CHAN 0x0000
24 #define DMFC_WR_CHAN 0x0004
25 #define DMFC_WR_CHAN_DEF 0x0008
26 #define DMFC_DP_CHAN 0x000c
27 #define DMFC_DP_CHAN_DEF 0x0010
28 #define DMFC_GENERAL1 0x0014
29 #define DMFC_GENERAL2 0x0018
30 #define DMFC_IC_CTRL 0x001c
31 #define DMFC_STAT 0x0020
33 #define DMFC_WR_CHAN_1_28 0
34 #define DMFC_WR_CHAN_2_41 8
35 #define DMFC_WR_CHAN_1C_42 16
36 #define DMFC_WR_CHAN_2C_43 24
38 #define DMFC_DP_CHAN_5B_23 0
39 #define DMFC_DP_CHAN_5F_27 8
40 #define DMFC_DP_CHAN_6B_24 16
41 #define DMFC_DP_CHAN_6F_29 24
43 #define DMFC_FIFO_SIZE_64 (3 << 3)
44 #define DMFC_FIFO_SIZE_128 (2 << 3)
45 #define DMFC_FIFO_SIZE_256 (1 << 3)
46 #define DMFC_FIFO_SIZE_512 (0 << 3)
48 #define DMFC_SEGMENT(x) ((x & 0x7) << 0)
49 #define DMFC_BURSTSIZE_128 (0 << 6)
50 #define DMFC_BURSTSIZE_64 (1 << 6)
51 #define DMFC_BURSTSIZE_32 (2 << 6)
52 #define DMFC_BURSTSIZE_16 (3 << 6)
54 struct dmfc_channel_data {
56 unsigned long channel_reg;
59 unsigned max_fifo_lines;
62 static const struct dmfc_channel_data dmfcdata[] = {
64 .ipu_channel = IPUV3_CHANNEL_MEM_BG_SYNC,
65 .channel_reg = DMFC_DP_CHAN,
66 .shift = DMFC_DP_CHAN_5B_23,
71 .channel_reg = DMFC_DP_CHAN,
72 .shift = DMFC_DP_CHAN_6B_24,
76 .ipu_channel = IPUV3_CHANNEL_MEM_FG_SYNC,
77 .channel_reg = DMFC_DP_CHAN,
78 .shift = DMFC_DP_CHAN_5F_27,
82 .ipu_channel = IPUV3_CHANNEL_MEM_DC_SYNC,
83 .channel_reg = DMFC_WR_CHAN,
84 .shift = DMFC_WR_CHAN_1_28,
89 .channel_reg = DMFC_DP_CHAN,
90 .shift = DMFC_DP_CHAN_6F_29,
96 #define DMFC_NUM_CHANNELS ARRAY_SIZE(dmfcdata)
100 struct dmfc_channel {
106 struct ipu_dmfc_priv *priv;
107 const struct dmfc_channel_data *data;
110 struct ipu_dmfc_priv {
113 struct dmfc_channel channels[DMFC_NUM_CHANNELS];
115 unsigned long bandwidth_per_slot;
120 int ipu_dmfc_enable_channel(struct dmfc_channel *dmfc)
122 struct ipu_dmfc_priv *priv = dmfc->priv;
123 mutex_lock(&priv->mutex);
125 if (!priv->use_count)
126 ipu_module_enable(priv->ipu, IPU_CONF_DMFC_EN);
130 mutex_unlock(&priv->mutex);
134 EXPORT_SYMBOL_GPL(ipu_dmfc_enable_channel);
136 void ipu_dmfc_disable_channel(struct dmfc_channel *dmfc)
138 struct ipu_dmfc_priv *priv = dmfc->priv;
140 mutex_lock(&priv->mutex);
144 if (!priv->use_count)
145 ipu_module_disable(priv->ipu, IPU_CONF_DMFC_EN);
147 if (priv->use_count < 0)
150 mutex_unlock(&priv->mutex);
152 EXPORT_SYMBOL_GPL(ipu_dmfc_disable_channel);
154 static int ipu_dmfc_setup_channel(struct dmfc_channel *dmfc, int slots,
155 int segment, int burstsize)
157 struct ipu_dmfc_priv *priv = dmfc->priv;
161 "dmfc: using %d slots starting from segment %d for IPU channel %d\n",
162 slots, segment, dmfc->data->ipu_channel);
166 field = DMFC_FIFO_SIZE_64;
169 field = DMFC_FIFO_SIZE_128;
172 field = DMFC_FIFO_SIZE_256;
175 field = DMFC_FIFO_SIZE_512;
183 field |= DMFC_BURSTSIZE_16;
186 field |= DMFC_BURSTSIZE_32;
189 field |= DMFC_BURSTSIZE_64;
192 field |= DMFC_BURSTSIZE_128;
196 field |= DMFC_SEGMENT(segment);
198 val = readl(priv->base + dmfc->data->channel_reg);
200 val &= ~(0xff << dmfc->data->shift);
201 val |= field << dmfc->data->shift;
203 writel(val, priv->base + dmfc->data->channel_reg);
206 dmfc->segment = segment;
207 dmfc->burstsize = burstsize;
208 dmfc->slotmask = ((1 << slots) - 1) << segment;
213 static int dmfc_bandwidth_to_slots(struct ipu_dmfc_priv *priv,
214 unsigned long bandwidth)
218 while (slots * priv->bandwidth_per_slot < bandwidth)
224 static int dmfc_find_slots(struct ipu_dmfc_priv *priv, int slots)
226 unsigned slotmask_need, slotmask_used = 0;
229 slotmask_need = (1 << slots) - 1;
231 for (i = 0; i < DMFC_NUM_CHANNELS; i++)
232 slotmask_used |= priv->channels[i].slotmask;
234 while (slotmask_need <= 0xff) {
235 if (!(slotmask_used & slotmask_need))
245 void ipu_dmfc_free_bandwidth(struct dmfc_channel *dmfc)
247 struct ipu_dmfc_priv *priv = dmfc->priv;
250 dev_dbg(priv->dev, "dmfc: freeing %d slots starting from segment %d\n",
251 dmfc->slots, dmfc->segment);
253 mutex_lock(&priv->mutex);
262 for (i = 0; i < DMFC_NUM_CHANNELS; i++)
263 priv->channels[i].slotmask = 0;
265 for (i = 0; i < DMFC_NUM_CHANNELS; i++) {
266 if (priv->channels[i].slots > 0) {
267 priv->channels[i].segment =
268 dmfc_find_slots(priv, priv->channels[i].slots);
269 priv->channels[i].slotmask =
270 ((1 << priv->channels[i].slots) - 1) <<
271 priv->channels[i].segment;
275 for (i = 0; i < DMFC_NUM_CHANNELS; i++) {
276 if (priv->channels[i].slots > 0)
277 ipu_dmfc_setup_channel(&priv->channels[i],
278 priv->channels[i].slots,
279 priv->channels[i].segment,
280 priv->channels[i].burstsize);
283 mutex_unlock(&priv->mutex);
285 EXPORT_SYMBOL_GPL(ipu_dmfc_free_bandwidth);
287 int ipu_dmfc_alloc_bandwidth(struct dmfc_channel *dmfc,
288 unsigned long bandwidth_pixel_per_second, int burstsize)
290 struct ipu_dmfc_priv *priv = dmfc->priv;
291 int slots = dmfc_bandwidth_to_slots(priv, bandwidth_pixel_per_second);
292 int segment = -1, ret = 0;
294 dev_dbg(priv->dev, "dmfc: trying to allocate %ldMpixel/s for IPU channel %d\n",
295 bandwidth_pixel_per_second / 1000000,
296 dmfc->data->ipu_channel);
298 ipu_dmfc_free_bandwidth(dmfc);
300 mutex_lock(&priv->mutex);
307 /* For the MEM_BG channel, first try to allocate twice the slots */
308 if (dmfc->data->ipu_channel == IPUV3_CHANNEL_MEM_BG_SYNC)
309 segment = dmfc_find_slots(priv, slots * 2);
311 /* Always allocate at least 128*4 bytes (2 slots) */
317 segment = dmfc_find_slots(priv, slots);
323 ipu_dmfc_setup_channel(dmfc, slots, segment, burstsize);
326 mutex_unlock(&priv->mutex);
330 EXPORT_SYMBOL_GPL(ipu_dmfc_alloc_bandwidth);
332 int ipu_dmfc_init_channel(struct dmfc_channel *dmfc, int width)
334 struct ipu_dmfc_priv *priv = dmfc->priv;
337 dmfc_gen1 = readl(priv->base + DMFC_GENERAL1);
339 if ((dmfc->slots * 64 * 4) / width > dmfc->data->max_fifo_lines)
340 dmfc_gen1 |= 1 << dmfc->data->eot_shift;
342 dmfc_gen1 &= ~(1 << dmfc->data->eot_shift);
344 writel(dmfc_gen1, priv->base + DMFC_GENERAL1);
348 EXPORT_SYMBOL_GPL(ipu_dmfc_init_channel);
350 struct dmfc_channel *ipu_dmfc_get(struct ipu_soc *ipu, int ipu_channel)
352 struct ipu_dmfc_priv *priv = ipu->dmfc_priv;
355 for (i = 0; i < DMFC_NUM_CHANNELS; i++)
356 if (dmfcdata[i].ipu_channel == ipu_channel)
357 return &priv->channels[i];
358 return ERR_PTR(-ENODEV);
360 EXPORT_SYMBOL_GPL(ipu_dmfc_get);
362 void ipu_dmfc_put(struct dmfc_channel *dmfc)
364 ipu_dmfc_free_bandwidth(dmfc);
366 EXPORT_SYMBOL_GPL(ipu_dmfc_put);
368 int ipu_dmfc_init(struct ipu_soc *ipu, struct device *dev, unsigned long base,
371 struct ipu_dmfc_priv *priv;
374 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
378 priv->base = devm_ioremap(dev, base, PAGE_SIZE);
384 mutex_init(&priv->mutex);
386 ipu->dmfc_priv = priv;
388 for (i = 0; i < DMFC_NUM_CHANNELS; i++) {
389 priv->channels[i].priv = priv;
390 priv->channels[i].ipu = ipu;
391 priv->channels[i].data = &dmfcdata[i];
394 writel(0x0, priv->base + DMFC_WR_CHAN);
395 writel(0x0, priv->base + DMFC_DP_CHAN);
398 * We have a total bandwidth of clkrate * 4pixel divided
401 priv->bandwidth_per_slot = clk_get_rate(ipu_clk) * 4 / 8;
403 dev_dbg(dev, "dmfc: 8 slots with %ldMpixel/s bandwidth each\n",
404 priv->bandwidth_per_slot / 1000000);
406 writel(0x202020f6, priv->base + DMFC_WR_CHAN_DEF);
407 writel(0x2020f6f6, priv->base + DMFC_DP_CHAN_DEF);
408 writel(0x00000003, priv->base + DMFC_GENERAL1);
413 void ipu_dmfc_exit(struct ipu_soc *ipu)