2 * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
4 * The code contained herein is licensed under the GNU General Public
5 * License. You may obtain a copy of the GNU General Public License
6 * Version 2 or later at the following locations:
8 * http://www.opensource.org/licenses/gpl-license.html
9 * http://www.gnu.org/copyleft/gpl.html
12 #include <linux/export.h>
13 #include <linux/types.h>
14 #include <linux/init.h>
16 #include <linux/errno.h>
17 #include <linux/spinlock.h>
18 #include <linux/delay.h>
19 #include <linux/clk.h>
20 #include <video/imx-ipu-v3.h>
25 struct ipu_smfc_priv *priv;
30 struct ipu_smfc_priv {
34 struct ipu_smfc channel[4];
39 #define SMFC_MAP 0x0000
40 #define SMFC_WMC 0x0004
41 #define SMFC_BS 0x0008
43 int ipu_smfc_set_burstsize(struct ipu_smfc *smfc, int burstsize)
45 struct ipu_smfc_priv *priv = smfc->priv;
49 spin_lock_irqsave(&priv->lock, flags);
51 shift = smfc->chno * 4;
52 val = readl(priv->base + SMFC_BS);
53 val &= ~(0xf << shift);
54 val |= burstsize << shift;
55 writel(val, priv->base + SMFC_BS);
57 spin_unlock_irqrestore(&priv->lock, flags);
61 EXPORT_SYMBOL_GPL(ipu_smfc_set_burstsize);
63 int ipu_smfc_map_channel(struct ipu_smfc *smfc, int csi_id, int mipi_id)
65 struct ipu_smfc_priv *priv = smfc->priv;
69 spin_lock_irqsave(&priv->lock, flags);
71 shift = smfc->chno * 3;
72 val = readl(priv->base + SMFC_MAP);
73 val &= ~(0x7 << shift);
74 val |= ((csi_id << 2) | mipi_id) << shift;
75 writel(val, priv->base + SMFC_MAP);
77 spin_unlock_irqrestore(&priv->lock, flags);
81 EXPORT_SYMBOL_GPL(ipu_smfc_map_channel);
83 int ipu_smfc_set_watermark(struct ipu_smfc *smfc, u32 set_level, u32 clr_level)
85 struct ipu_smfc_priv *priv = smfc->priv;
89 spin_lock_irqsave(&priv->lock, flags);
91 shift = smfc->chno * 6 + (smfc->chno > 1 ? 4 : 0);
92 val = readl(priv->base + SMFC_WMC);
93 val &= ~(0x3f << shift);
94 val |= ((clr_level << 3) | set_level) << shift;
95 writel(val, priv->base + SMFC_WMC);
97 spin_unlock_irqrestore(&priv->lock, flags);
101 EXPORT_SYMBOL_GPL(ipu_smfc_set_watermark);
103 int ipu_smfc_enable(struct ipu_smfc *smfc)
105 struct ipu_smfc_priv *priv = smfc->priv;
108 spin_lock_irqsave(&priv->lock, flags);
110 if (!priv->use_count)
111 ipu_module_enable(priv->ipu, IPU_CONF_SMFC_EN);
115 spin_unlock_irqrestore(&priv->lock, flags);
119 EXPORT_SYMBOL_GPL(ipu_smfc_enable);
121 int ipu_smfc_disable(struct ipu_smfc *smfc)
123 struct ipu_smfc_priv *priv = smfc->priv;
126 spin_lock_irqsave(&priv->lock, flags);
130 if (!priv->use_count)
131 ipu_module_disable(priv->ipu, IPU_CONF_SMFC_EN);
133 if (priv->use_count < 0)
136 spin_unlock_irqrestore(&priv->lock, flags);
140 EXPORT_SYMBOL_GPL(ipu_smfc_disable);
142 struct ipu_smfc *ipu_smfc_get(struct ipu_soc *ipu, unsigned int chno)
144 struct ipu_smfc_priv *priv = ipu->smfc_priv;
145 struct ipu_smfc *smfc, *ret;
149 return ERR_PTR(-EINVAL);
151 smfc = &priv->channel[chno];
154 spin_lock_irqsave(&priv->lock, flags);
157 ret = ERR_PTR(-EBUSY);
163 spin_unlock_irqrestore(&priv->lock, flags);
166 EXPORT_SYMBOL_GPL(ipu_smfc_get);
168 void ipu_smfc_put(struct ipu_smfc *smfc)
170 struct ipu_smfc_priv *priv = smfc->priv;
173 spin_lock_irqsave(&priv->lock, flags);
175 spin_unlock_irqrestore(&priv->lock, flags);
177 EXPORT_SYMBOL_GPL(ipu_smfc_put);
179 int ipu_smfc_init(struct ipu_soc *ipu, struct device *dev,
182 struct ipu_smfc_priv *priv;
185 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
189 ipu->smfc_priv = priv;
190 spin_lock_init(&priv->lock);
193 priv->base = devm_ioremap(dev, base, PAGE_SIZE);
197 for (i = 0; i < 4; i++) {
198 priv->channel[i].priv = priv;
199 priv->channel[i].chno = i;
202 pr_debug("%s: ioremap 0x%08lx -> %p\n", __func__, base, priv->base);
207 void ipu_smfc_exit(struct ipu_soc *ipu)