1 /*************************************************************************/ /*!
3 @Title RGX META definitions
4 @Copyright Copyright (c) Imagination Technologies Ltd. All Rights Reserved
5 @Description RGX META helper definitions
6 @License Dual MIT/GPLv2
8 The contents of this file are subject to the MIT license as set out below.
10 Permission is hereby granted, free of charge, to any person obtaining a copy
11 of this software and associated documentation files (the "Software"), to deal
12 in the Software without restriction, including without limitation the rights
13 to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
14 copies of the Software, and to permit persons to whom the Software is
15 furnished to do so, subject to the following conditions:
17 The above copyright notice and this permission notice shall be included in
18 all copies or substantial portions of the Software.
20 Alternatively, the contents of this file may be used under the terms of
21 the GNU General Public License Version 2 ("GPL") in which case the provisions
22 of GPL are applicable instead of those above.
24 If you wish to allow use of your version of this file only under the terms of
25 GPL, and not to allow others to use your version of this file under the terms
26 of the MIT license, indicate your decision by deleting the provisions above
27 and replace them with the notice and other provisions required by GPL as set
28 out in the file called "GPL-COPYING" included in this distribution. If you do
29 not delete the provisions above, a recipient may use your version of this file
30 under the terms of either the MIT license or GPL.
32 This License is also included in this distribution in the file called
35 EXCEPT AS OTHERWISE STATED IN A NEGOTIATED AGREEMENT: (A) THE SOFTWARE IS
36 PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
37 BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR
38 PURPOSE AND NONINFRINGEMENT; AND (B) IN NO EVENT SHALL THE AUTHORS OR
39 COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
40 IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
41 CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
42 */ /**************************************************************************/
44 #if !defined (__RGX_META_H__)
45 #define __RGX_META_H__
48 /***** The META HW register definitions in the file are updated manually *****/
53 /************************************************************************
54 * META registers and MACROS
55 ************************************************************************/
56 #define META_CR_CTRLREG_BASE(T) (0x04800000 + 0x1000*(T))
58 #define META_CR_TXPRIVEXT (0x048000E8)
59 #define META_CR_TXPRIVEXT_MINIM_EN (0x1<<7)
61 #define META_CR_SYSC_JTAG_THREAD (0x04830030)
62 #define META_CR_SYSC_JTAG_THREAD_PRIV_EN (0x00000004)
64 #define META_CR_PERF_COUNT0 (0x0480FFE0)
65 #define META_CR_PERF_COUNT1 (0x0480FFE8)
66 #define META_CR_PERF_COUNT_CTRL_SHIFT (28)
67 #define META_CR_PERF_COUNT_CTRL_MASK (0xF0000000)
68 #define META_CR_PERF_COUNT_CTRL_DCACHEHITS (0x8 << META_CR_PERF_COUNT_CTRL_SHIFT)
69 #define META_CR_PERF_COUNT_CTRL_ICACHEHITS (0x9 << META_CR_PERF_COUNT_CTRL_SHIFT)
70 #define META_CR_PERF_COUNT_CTRL_ICACHEMISS (0xA << META_CR_PERF_COUNT_CTRL_SHIFT)
71 #define META_CR_PERF_COUNT_CTRL_ICORE (0xD << META_CR_PERF_COUNT_CTRL_SHIFT)
72 #define META_CR_PERF_COUNT_THR_SHIFT (24)
73 #define META_CR_PERF_COUNT_THR_MASK (0x0F000000)
74 #define META_CR_PERF_COUNT_THR_0 (0x1 << META_CR_PERF_COUNT_THR_SHIFT)
75 #define META_CR_PERF_COUNT_THR_1 (0x2 << META_CR_PERF_COUNT_THR_1)
77 #define META_CR_TxVECINT_BHALT (0x04820500)
78 #define META_CR_PERF_ICORE0 (0x0480FFD0)
79 #define META_CR_PERF_ICORE1 (0x0480FFD8)
80 #define META_CR_PERF_ICORE_DCACHEMISS (0x8)
84 META_PERF_CONF_NONE = 0,
85 META_PERF_CONF_ICACHE = 1,
86 META_PERF_CONF_DCACHE = 2,
87 META_PERF_CONF_POLLS = 3,
90 #define META_CR_PERF_COUNT(CTRL, THR) ((META_CR_PERF_COUNT_CTRL_##CTRL << META_CR_PERF_COUNT_CTRL_SHIFT) | \
91 (THR << META_CR_PERF_COUNT_THR_SHIFT))
93 #define META_CR_TXUXXRXDT_OFFSET (META_CR_CTRLREG_BASE(0) + 0x0000FFF0)
94 #define META_CR_TXUXXRXRQ_OFFSET (META_CR_CTRLREG_BASE(0) + 0x0000FFF8)
96 #define META_CR_TXUXXRXRQ_DREADY_BIT (0x80000000) /* Poll for done */
97 #define META_CR_TXUXXRXRQ_RDnWR_BIT (0x00010000) /* Set for read */
98 #define META_CR_TXUXXRXRQ_TX_S (12)
99 #define META_CR_TXUXXRXRQ_RX_S (4)
100 #define META_CR_TXUXXRXRQ_UXX_S (0)
102 #define META_CR_TXUA0_ID (0x3) /* Address unit regs */
103 #define META_CR_TXUPC_ID (0x5) /* PC registers */
105 /* Macros to calculate register access values */
106 #define META_CR_CORE_REG(Thr, RegNum, Unit) (((Thr) << META_CR_TXUXXRXRQ_TX_S ) | \
107 ((RegNum) << META_CR_TXUXXRXRQ_RX_S ) | \
108 ((Unit) << META_CR_TXUXXRXRQ_UXX_S))
110 #define META_CR_THR0_PC META_CR_CORE_REG(0, 0, META_CR_TXUPC_ID)
111 #define META_CR_THR0_PCX META_CR_CORE_REG(0, 1, META_CR_TXUPC_ID)
112 #define META_CR_THR0_SP META_CR_CORE_REG(0, 0, META_CR_TXUA0_ID)
114 #define META_CR_THR1_PC META_CR_CORE_REG(1, 0, META_CR_TXUPC_ID)
115 #define META_CR_THR1_PCX META_CR_CORE_REG(1, 1, META_CR_TXUPC_ID)
116 #define META_CR_THR1_SP META_CR_CORE_REG(1, 0, META_CR_TXUA0_ID)
118 #define SP_ACCESS(Thread) META_CR_CORE_REG(Thread, 0, META_CR_TXUA0_ID)
119 #define PC_ACCESS(Thread) META_CR_CORE_REG(Thread, 0, META_CR_TXUPC_ID)
121 #define META_CR_COREREG_ENABLE (0x0000000)
122 #define META_CR_COREREG_STATUS (0x0000010)
123 #define META_CR_COREREG_DEFR (0x00000A0)
125 #define META_CR_T0ENABLE_OFFSET (META_CR_CTRLREG_BASE(0) + META_CR_COREREG_ENABLE)
126 #define META_CR_T0STATUS_OFFSET (META_CR_CTRLREG_BASE(0) + META_CR_COREREG_STATUS)
127 #define META_CR_T0DEFR_OFFSET (META_CR_CTRLREG_BASE(0) + META_CR_COREREG_DEFR)
129 #define META_CR_T1ENABLE_OFFSET (META_CR_CTRLREG_BASE(1) + META_CR_COREREG_ENABLE)
130 #define META_CR_T1STATUS_OFFSET (META_CR_CTRLREG_BASE(1) + META_CR_COREREG_STATUS)
131 #define META_CR_T1DEFR_OFFSET (META_CR_CTRLREG_BASE(1) + META_CR_COREREG_DEFR)
133 #define META_CR_TXENABLE_ENABLE_BIT (0x00000001) /* Set if running */
134 #define META_CR_TXSTATUS_PRIV (0x00020000)
136 #define META_MEM_GLOBAL_RANGE_BIT (0x80000000)
139 /************************************************************************
141 ************************************************************************/
142 /* Block header structure */
145 IMG_UINT32 ui32DevID;
146 IMG_UINT32 ui32SLCode;
147 IMG_UINT32 ui32SLData;
148 IMG_UINT16 ui16PLCtrl;
151 } RGX_META_LDR_BLOCK_HDR;
153 /* High level data stream block structure */
157 IMG_UINT16 ui16Length;
159 IMG_UINT32 aui32CmdData[4];
161 } RGX_META_LDR_L1_DATA_BLK;
163 /* High level data stream block structure */
167 IMG_UINT16 ui16Length;
168 IMG_UINT32 aui32BlockData[4];
170 } RGX_META_LDR_L2_DATA_BLK;
172 /* Config command structure */
176 IMG_UINT32 aui32BlockData[4];
178 } RGX_META_LDR_CFG_BLK;
180 /* Block type definitions */
181 #define RGX_META_LDR_COMMENT_TYPE_MASK (0x0010)
182 #define RGX_META_LDR_BLK_IS_COMMENT(X) ((X & RGX_META_LDR_COMMENT_TYPE_MASK) != 0)
184 /* Command definitions
185 Value Name Description
186 0 LoadMem Load memory with binary data.
187 1 LoadCore Load a set of core registers.
188 2 LoadMMReg Load a set of memory mapped registers.
189 3 StartThreads Set each thread PC and SP, then enable threads.
190 4 ZeroMem Zeros a memory region.
191 5 Config Perform a configuration command. */
192 #define RGX_META_LDR_CMD_MASK (0x000F)
194 #define RGX_META_LDR_CMD_LOADMEM (0x0000)
195 #define RGX_META_LDR_CMD_LOADCORE (0x0001)
196 #define RGX_META_LDR_CMD_LOADMMREG (0x0002)
197 #define RGX_META_LDR_CMD_START_THREADS (0x0003)
198 #define RGX_META_LDR_CMD_ZEROMEM (0x0004)
199 #define RGX_META_LDR_CMD_CONFIG (0x0005)
201 /* Config Command definitions
202 Value Name Description
203 0 Pause Pause for x times 100 instructions
204 1 Read Read a value from register - No value return needed.
205 Utilises effects of issuing reads to certain registers
206 2 Write Write to mem location
207 3 MemSet Set mem to value
208 4 MemCheck check mem for specific value.*/
209 #define RGX_META_LDR_CFG_PAUSE (0x0000)
210 #define RGX_META_LDR_CFG_READ (0x0001)
211 #define RGX_META_LDR_CFG_WRITE (0x0002)
212 #define RGX_META_LDR_CFG_MEMSET (0x0003)
213 #define RGX_META_LDR_CFG_MEMCHECK (0x0004)
215 /************************************************************************
216 * RGX FW segmented MMU definitions
217 ************************************************************************/
218 /* All threads can access the segment */
219 #define RGXFW_SEGMMU_ALLTHRS (0xf << 8)
221 #define RGXFW_SEGMMU_WRITEABLE (0x1 << 1)
222 /* All threads can access and writeable */
223 #define RGXFW_SEGMMU_ALLTHRS_WRITEABLE (RGXFW_SEGMMU_ALLTHRS | RGXFW_SEGMMU_WRITEABLE)
225 /* Direct map regions mapping (8-10) */
226 #define RGXFW_SEGMMU_DMAP_ID_START (8)
227 #define RGXFW_SEGMMU_DMAP_ADDR_START (0x06000000U)
228 #define RGXFW_SEGMMU_DMAP_ADDR_META (0x86000000U)
229 #define RGXFW_SEGMMU_DMAP_SIZE (8*1024*1024) /* 8 MB */
231 /* Direct map region 11 used for mapping GPU memory */
232 #define RGXFW_SEGMMU_DMAP_GPU_ID (11)
233 #define RGXFW_SEGMMU_DMAP_GPU_ADDR_START (RGXFW_SEGMMU_DMAP_ADDR_START + 3*RGXFW_SEGMMU_DMAP_SIZE)
236 #define RGXFW_SEGMMU_TEXT_ID (0)
237 #define RGXFW_SEGMMU_SHARED_ID (1)
238 #define RGXFW_SEGMMU_BOOTLDR_ID (2)
239 #define RGXFW_SEGMMU_DATA_ID (3)
241 #define RGXFW_SEGMMU_META_DM_ID (0x7)
243 #if defined(HW_ERN_45914)
244 /* SLC caching strategy is emitted through the segment MMU. All the segments configured
245 through this macro are CACHED in the SLC. The interface has been kept the same to
246 simplify the code changes. The bifdm argument is ignored (no longer relevant). */
247 #define RGXFW_SEGMMU_OUTADDR_TOP_S7(pers, coheren, mmu_ctx) ( (((IMG_UINT64) ((pers) & 0x3)) << 52) | \
248 (((IMG_UINT64) ((mmu_ctx) & 0xFF)) << 44) | \
249 (((IMG_UINT64) ((coheren) & 0x1)) << 40) )
250 #define RGXFW_SEGMMU_OUTADDR_TOP_S7_SLC_CACHED(mmu_ctx) RGXFW_SEGMMU_OUTADDR_TOP_S7(0x3, 0x0, mmu_ctx)
251 #define RGXFW_SEGMMU_OUTADDR_TOP_S7_SLC_UNCACHED(mmu_ctx) RGXFW_SEGMMU_OUTADDR_TOP_S7(0x0, 0x1, mmu_ctx)
253 // Temporarily use uncached for everything:
254 //#define RGXFW_SEGMMU_OUTADDR_TOP(mmu_ctx, bifdm) RGXFW_SEGMMU_OUTADDR_TOP_S7_SLC_CACHED(mmu_ctx)
255 #define RGXFW_SEGMMU_OUTADDR_TOP(mmu_ctx, bifdm) RGXFW_SEGMMU_OUTADDR_TOP_S7_SLC_UNCACHED(mmu_ctx | (bifdm&0x0))
257 /* To configure the Page Catalog and BIF-DM fed into the BIF for Garten accesses through this segment */
258 #define RGXFW_SEGMMU_OUTADDR_TOP(pc, bifdm) ( (((IMG_UINT64) ((pc) & 0xF)) << 44) | \
259 (((IMG_UINT64) ((bifdm) & 0xF)) << 40) )
262 /* META segments have 4kB minimum size */
263 #define RGXFW_SEGMMU_ALIGN (0x1000)
265 /* Segmented MMU registers (n = segment id) */
266 #define META_CR_MMCU_SEGMENTn_BASE(n) (0x04850000 + (n)*0x10)
267 #define META_CR_MMCU_SEGMENTn_LIMIT(n) (0x04850004 + (n)*0x10)
268 #define META_CR_MMCU_SEGMENTn_OUTA0(n) (0x04850008 + (n)*0x10)
269 #define META_CR_MMCU_SEGMENTn_OUTA1(n) (0x0485000C + (n)*0x10)
271 /* Win mode for data cache */
272 #define RGXFW__SEGMMU_DMAP_DC_WIN (0x3)
273 #define RGXFW__SEGMMU_DMAP_DC_SHIFT (0x6)
275 /************************************************************************
276 * RGX FW Bootloader defaults
277 ************************************************************************/
278 #define RGXFW_BOOTLDR_META_ADDR (0x40000000)
279 #define RGXFW_BOOTLDR_DEVV_ADDR_0 (0xC0000000)
280 #if defined(HW_ERN_45914)
281 #define RGXFW_BOOTLDR_DEVV_ADDR_1 (0x003000E1)
283 #define RGXFW_BOOTLDR_DEVV_ADDR_1 (0x000007E1)
285 #define RGXFW_BOOTLDR_DEVV_ADDR ((((IMG_UINT64) RGXFW_BOOTLDR_DEVV_ADDR_1) << 32) | RGXFW_BOOTLDR_DEVV_ADDR_0)
286 #define RGXFW_BOOTLDR_LIMIT (0x1FFFF000)
288 /* Bootloader configuration offset is in dwords (512 bytes) */
289 #define RGXFW_BOOTLDR_CONF_OFFSET (0x80)
291 /************************************************************************
293 ************************************************************************/
294 #define RGX_META_STACK_SIZE (0xC00)
296 /************************************************************************
297 * RGX META Core memory
298 ************************************************************************/
299 #define RGX_META_COREMEM_BSS_SIZE (0x800)
300 #define RGX_META_COREMEM_DATA_SIZE (RGX_META_COREMEM_BSS_SIZE + RGX_META_STACK_SIZE)
301 #define RGX_META_COREMEM_CODE_SIZE (RGX_META_COREMEM_SIZE - RGX_META_COREMEM_DATA_SIZE)
302 /* code and data both map to the same physical memory */
303 #define RGX_META_COREMEM_CODE_ADDR (0x80000000)
304 #define RGX_META_COREMEM_DATA_ADDR (0x82000000)
305 #define RGX_META_COREMEM_STACK_ADDR (RGX_META_COREMEM_DATA_ADDR)
306 #define RGX_META_COREMEM_BSS_ADDR (RGX_META_COREMEM_STACK_ADDR + RGX_META_STACK_SIZE)
307 /* because data and code share the same memory, base address for code is offset by the data */
308 #define RGX_META_COREMEM_CODE_BADDR (RGX_META_COREMEM_CODE_ADDR + RGX_META_COREMEM_DATA_SIZE)
310 #define RGX_META_IS_COREMEM_CODE(A) (((A) >= RGX_META_COREMEM_CODE_BADDR) && ((A) < (RGX_META_COREMEM_CODE_ADDR + RGX_META_COREMEM_SIZE)))
311 #define RGX_META_IS_COREMEM_DATA(A) (((A) >= RGX_META_COREMEM_DATA_ADDR) && ((A) < (RGX_META_COREMEM_DATA_ADDR + RGX_META_COREMEM_DATA_SIZE)))
313 /************************************************************************
315 ************************************************************************/
316 #define RGXFW_THR1_PC (0x18930000)
317 #define RGXFW_THR1_SP (0x78890000)
319 /************************************************************************
321 ************************************************************************/
323 #define META_CR_CORE_ID (0x04831000)
324 #define META_CR_CORE_ID_VER_SHIFT (16U)
325 #define META_CR_CORE_ID_VER_CLRMSK (0XFF00FFFFU)
327 #if (RGX_FEATURE_META == MTP218)
328 #define RGX_CR_META_CORE_ID_VALUE 0x19
329 #elif (RGX_FEATURE_META == MTP219)
330 #define RGX_CR_META_CORE_ID_VALUE 0x1E
331 #elif (RGX_FEATURE_META == LTP218)
332 #define RGX_CR_META_CORE_ID_VALUE 0x1C
333 #elif (RGX_FEATURE_META == LTP217)
334 #define RGX_CR_META_CORE_ID_VALUE 0x1F
336 #error "Unknown META ID"
339 #endif /* __RGX_META_H__ */
341 /******************************************************************************
342 End of file (rgx_meta.h)
343 ******************************************************************************/