drivers/hwtracing/coresight/coresight-etm3x.c

   1 /* Copyright (c) 2011-2012, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/module.h>
  15 #include <linux/init.h>
  16 #include <linux/types.h>
  17 #include <linux/device.h>
  18 #include <linux/io.h>
  19 #include <linux/err.h>
  20 #include <linux/fs.h>
  21 #include <linux/slab.h>
  22 #include <linux/delay.h>
  23 #include <linux/smp.h>
  24 #include <linux/sysfs.h>
  25 #include <linux/stat.h>
  26 #include <linux/pm_runtime.h>
  27 #include <linux/cpu.h>
  28 #include <linux/of.h>
  29 #include <linux/coresight.h>
  30 #include <linux/amba/bus.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/uaccess.h>
  33 #include <linux/clk.h>
  34 #include <asm/sections.h>
  35
  36 #include "coresight-etm.h"
  37
  38 static int boot_enable;
  39 module_param_named(boot_enable, boot_enable, int, S_IRUGO);
  40
  41 /* The number of ETM/PTM currently registered */
  42 static int etm_count;
  43 static struct etm_drvdata *etmdrvdata[NR_CPUS];
  44
  45 static inline void etm_writel(struct etm_drvdata *drvdata,
  46                               u32 val, u32 off)
  47 {
  48         if (drvdata->use_cp14) {
  49                 if (etm_writel_cp14(off, val)) {
  50                         dev_err(drvdata->dev,
  51                                 "invalid CP14 access to ETM reg: %#x", off);
  52                 }
  53         } else {
  54                 writel_relaxed(val, drvdata->base + off);
  55         }
  56 }
  57
  58 static inline unsigned int etm_readl(struct etm_drvdata *drvdata, u32 off)
  59 {
  60         u32 val;
  61
  62         if (drvdata->use_cp14) {
  63                 if (etm_readl_cp14(off, &val)) {
  64                         dev_err(drvdata->dev,
  65                                 "invalid CP14 access to ETM reg: %#x", off);
  66                 }
  67         } else {
  68                 val = readl_relaxed(drvdata->base + off);
  69         }
  70
  71         return val;
  72 }
  73
  74 /*
  75  * Memory mapped writes to clear os lock are not supported on some processors
  76  * and OS lock must be unlocked before any memory mapped access on such
  77  * processors, otherwise memory mapped reads/writes will be invalid.
  78  */
  79 static void etm_os_unlock(void *info)
  80 {
  81         struct etm_drvdata *drvdata = (struct etm_drvdata *)info;
  82         /* Writing any value to ETMOSLAR unlocks the trace registers */
  83         etm_writel(drvdata, 0x0, ETMOSLAR);
  84         isb();
  85 }
  86
  87 static void etm_set_pwrdwn(struct etm_drvdata *drvdata)
  88 {
  89         u32 etmcr;
  90
  91         /* Ensure pending cp14 accesses complete before setting pwrdwn */
  92         mb();
  93         isb();
  94         etmcr = etm_readl(drvdata, ETMCR);
  95         etmcr |= ETMCR_PWD_DWN;
  96         etm_writel(drvdata, etmcr, ETMCR);
  97 }
  98
  99 static void etm_clr_pwrdwn(struct etm_drvdata *drvdata)
 100 {
 101         u32 etmcr;
 102
 103         etmcr = etm_readl(drvdata, ETMCR);
 104         etmcr &= ~ETMCR_PWD_DWN;
 105         etm_writel(drvdata, etmcr, ETMCR);
 106         /* Ensure pwrup completes before subsequent cp14 accesses */
 107         mb();
 108         isb();
 109 }
 110
 111 static void etm_set_pwrup(struct etm_drvdata *drvdata)
 112 {
 113         u32 etmpdcr;
 114
 115         etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
 116         etmpdcr |= ETMPDCR_PWD_UP;
 117         writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
 118         /* Ensure pwrup completes before subsequent cp14 accesses */
 119         mb();
 120         isb();
 121 }
 122
 123 static void etm_clr_pwrup(struct etm_drvdata *drvdata)
 124 {
 125         u32 etmpdcr;
 126
 127         /* Ensure pending cp14 accesses complete before clearing pwrup */
 128         mb();
 129         isb();
 130         etmpdcr = readl_relaxed(drvdata->base + ETMPDCR);
 131         etmpdcr &= ~ETMPDCR_PWD_UP;
 132         writel_relaxed(etmpdcr, drvdata->base + ETMPDCR);
 133 }
 134
 135 /**
 136  * coresight_timeout_etm - loop until a bit has changed to a specific state.
 137  * @drvdata: etm's private data structure.
 138  * @offset: address of a register, starting from @addr.
 139  * @position: the position of the bit of interest.
 140  * @value: the value the bit should have.
 141  *
 142  * Basically the same as @coresight_timeout except for the register access
 143  * method where we have to account for CP14 configurations.
 144
 145  * Return: 0 as soon as the bit has taken the desired state or -EAGAIN if
 146  * TIMEOUT_US has elapsed, which ever happens first.
 147  */
 148
 149 static int coresight_timeout_etm(struct etm_drvdata *drvdata, u32 offset,
 150                                   int position, int value)
 151 {
 152         int i;
 153         u32 val;
 154
 155         for (i = TIMEOUT_US; i > 0; i--) {
 156                 val = etm_readl(drvdata, offset);
 157                 /* Waiting on the bit to go from 0 to 1 */
 158                 if (value) {
 159                         if (val & BIT(position))
 160                                 return 0;
 161                 /* Waiting on the bit to go from 1 to 0 */
 162                 } else {
 163                         if (!(val & BIT(position)))
 164                                 return 0;
 165                 }
 166
 167                 /*
 168                  * Delay is arbitrary - the specification doesn't say how long
 169                  * we are expected to wait.  Extra check required to make sure
 170                  * we don't wait needlessly on the last iteration.
 171                  */
 172                 if (i - 1)
 173                         udelay(1);
 174         }
 175
 176         return -EAGAIN;
 177 }
 178
 179
 180 static void etm_set_prog(struct etm_drvdata *drvdata)
 181 {
 182         u32 etmcr;
 183
 184         etmcr = etm_readl(drvdata, ETMCR);
 185         etmcr |= ETMCR_ETM_PRG;
 186         etm_writel(drvdata, etmcr, ETMCR);
 187         /*
 188          * Recommended by spec for cp14 accesses to ensure etmcr write is
 189          * complete before polling etmsr
 190          */
 191         isb();
 192         if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 1)) {
 193                 dev_err(drvdata->dev,
 194                         "timeout observed when probing at offset %#x\n", ETMSR);
 195         }
 196 }
 197
 198 static void etm_clr_prog(struct etm_drvdata *drvdata)
 199 {
 200         u32 etmcr;
 201
 202         etmcr = etm_readl(drvdata, ETMCR);
 203         etmcr &= ~ETMCR_ETM_PRG;
 204         etm_writel(drvdata, etmcr, ETMCR);
 205         /*
 206          * Recommended by spec for cp14 accesses to ensure etmcr write is
 207          * complete before polling etmsr
 208          */
 209         isb();
 210         if (coresight_timeout_etm(drvdata, ETMSR, ETMSR_PROG_BIT, 0)) {
 211                 dev_err(drvdata->dev,
 212                         "timeout observed when probing at offset %#x\n", ETMSR);
 213         }
 214 }
 215
 216 static void etm_set_default(struct etm_drvdata *drvdata)
 217 {
 218         int i;
 219
 220         drvdata->trigger_event = ETM_DEFAULT_EVENT_VAL;
 221         drvdata->enable_event = ETM_HARD_WIRE_RES_A;
 222
 223         drvdata->seq_12_event = ETM_DEFAULT_EVENT_VAL;
 224         drvdata->seq_21_event = ETM_DEFAULT_EVENT_VAL;
 225         drvdata->seq_23_event = ETM_DEFAULT_EVENT_VAL;
 226         drvdata->seq_31_event = ETM_DEFAULT_EVENT_VAL;
 227         drvdata->seq_32_event = ETM_DEFAULT_EVENT_VAL;
 228         drvdata->seq_13_event = ETM_DEFAULT_EVENT_VAL;
 229         drvdata->timestamp_event = ETM_DEFAULT_EVENT_VAL;
 230
 231         for (i = 0; i < drvdata->nr_cntr; i++) {
 232                 drvdata->cntr_rld_val[i] = 0x0;
 233                 drvdata->cntr_event[i] = ETM_DEFAULT_EVENT_VAL;
 234                 drvdata->cntr_rld_event[i] = ETM_DEFAULT_EVENT_VAL;
 235                 drvdata->cntr_val[i] = 0x0;
 236         }
 237
 238         drvdata->seq_curr_state = 0x0;
 239         drvdata->ctxid_idx = 0x0;
 240         for (i = 0; i < drvdata->nr_ctxid_cmp; i++) {
 241                 drvdata->ctxid_pid[i] = 0x0;
 242                 drvdata->ctxid_vpid[i] = 0x0;
 243         }
 244
 245         drvdata->ctxid_mask = 0x0;
 246 }
 247
 248 static void etm_enable_hw(void *info)
 249 {
 250         int i;
 251         u32 etmcr;
 252         struct etm_drvdata *drvdata = info;
 253
 254         CS_UNLOCK(drvdata->base);
 255
 256         /* Turn engine on */
 257         etm_clr_pwrdwn(drvdata);
 258         /* Apply power to trace registers */
 259         etm_set_pwrup(drvdata);
 260         /* Make sure all registers are accessible */
 261         etm_os_unlock(drvdata);
 262
 263         etm_set_prog(drvdata);
 264
 265         etmcr = etm_readl(drvdata, ETMCR);
 266         etmcr &= (ETMCR_PWD_DWN | ETMCR_ETM_PRG);
 267         etmcr |= drvdata->port_size;
 268         etm_writel(drvdata, drvdata->ctrl | etmcr, ETMCR);
 269         etm_writel(drvdata, drvdata->trigger_event, ETMTRIGGER);
 270         etm_writel(drvdata, drvdata->startstop_ctrl, ETMTSSCR);
 271         etm_writel(drvdata, drvdata->enable_event, ETMTEEVR);
 272         etm_writel(drvdata, drvdata->enable_ctrl1, ETMTECR1);
 273         etm_writel(drvdata, drvdata->fifofull_level, ETMFFLR);
 274         for (i = 0; i < drvdata->nr_addr_cmp; i++) {
 275                 etm_writel(drvdata, drvdata->addr_val[i], ETMACVRn(i));
 276                 etm_writel(drvdata, drvdata->addr_acctype[i], ETMACTRn(i));
 277         }
 278         for (i = 0; i < drvdata->nr_cntr; i++) {
 279                 etm_writel(drvdata, drvdata->cntr_rld_val[i], ETMCNTRLDVRn(i));
 280                 etm_writel(drvdata, drvdata->cntr_event[i], ETMCNTENRn(i));
 281                 etm_writel(drvdata, drvdata->cntr_rld_event[i],
 282                            ETMCNTRLDEVRn(i));
 283                 etm_writel(drvdata, drvdata->cntr_val[i], ETMCNTVRn(i));
 284         }
 285         etm_writel(drvdata, drvdata->seq_12_event, ETMSQ12EVR);
 286         etm_writel(drvdata, drvdata->seq_21_event, ETMSQ21EVR);
 287         etm_writel(drvdata, drvdata->seq_23_event, ETMSQ23EVR);
 288         etm_writel(drvdata, drvdata->seq_31_event, ETMSQ31EVR);
 289         etm_writel(drvdata, drvdata->seq_32_event, ETMSQ32EVR);
 290         etm_writel(drvdata, drvdata->seq_13_event, ETMSQ13EVR);
 291         etm_writel(drvdata, drvdata->seq_curr_state, ETMSQR);
 292         for (i = 0; i < drvdata->nr_ext_out; i++)
 293                 etm_writel(drvdata, ETM_DEFAULT_EVENT_VAL, ETMEXTOUTEVRn(i));
 294         for (i = 0; i < drvdata->nr_ctxid_cmp; i++)
 295                 etm_writel(drvdata, drvdata->ctxid_pid[i], ETMCIDCVRn(i));
 296         etm_writel(drvdata, drvdata->ctxid_mask, ETMCIDCMR);
 297         etm_writel(drvdata, drvdata->sync_freq, ETMSYNCFR);
 298         /* No external input selected */
 299         etm_writel(drvdata, 0x0, ETMEXTINSELR);
 300         etm_writel(drvdata, drvdata->timestamp_event, ETMTSEVR);
 301         /* No auxiliary control selected */
 302         etm_writel(drvdata, 0x0, ETMAUXCR);
 303         etm_writel(drvdata, drvdata->traceid, ETMTRACEIDR);
 304         /* No VMID comparator value selected */
 305         etm_writel(drvdata, 0x0, ETMVMIDCVR);
 306
 307         /* Ensures trace output is enabled from this ETM */
 308         etm_writel(drvdata, drvdata->ctrl | ETMCR_ETM_EN | etmcr, ETMCR);
 309
 310         etm_clr_prog(drvdata);
 311         CS_LOCK(drvdata->base);
 312
 313         dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
 314 }
 315
 316 static int etm_trace_id(struct coresight_device *csdev)
 317 {
 318         struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 319         unsigned long flags;
 320         int trace_id = -1;
 321
 322         if (!drvdata->enable)
 323                 return drvdata->traceid;
 324         pm_runtime_get_sync(csdev->dev.parent);
 325
 326         spin_lock_irqsave(&drvdata->spinlock, flags);
 327
 328         CS_UNLOCK(drvdata->base);
 329         trace_id = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK);
 330         CS_LOCK(drvdata->base);
 331
 332         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 333         pm_runtime_put(csdev->dev.parent);
 334
 335         return trace_id;
 336 }
 337
 338 static int etm_enable(struct coresight_device *csdev)
 339 {
 340         struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 341         int ret;
 342
 343         pm_runtime_get_sync(csdev->dev.parent);
 344         spin_lock(&drvdata->spinlock);
 345
 346         /*
 347          * Configure the ETM only if the CPU is online.  If it isn't online
 348          * hw configuration will take place when 'CPU_STARTING' is received
 349          * in @etm_cpu_callback.
 350          */
 351         if (cpu_online(drvdata->cpu)) {
 352                 ret = smp_call_function_single(drvdata->cpu,
 353                                                etm_enable_hw, drvdata, 1);
 354                 if (ret)
 355                         goto err;
 356         }
 357
 358         drvdata->enable = true;
 359         drvdata->sticky_enable = true;
 360
 361         spin_unlock(&drvdata->spinlock);
 362
 363         dev_info(drvdata->dev, "ETM tracing enabled\n");
 364         return 0;
 365 err:
 366         spin_unlock(&drvdata->spinlock);
 367         pm_runtime_put(csdev->dev.parent);
 368         return ret;
 369 }
 370
 371 static void etm_disable_hw(void *info)
 372 {
 373         int i;
 374         struct etm_drvdata *drvdata = info;
 375
 376         CS_UNLOCK(drvdata->base);
 377         etm_set_prog(drvdata);
 378
 379         /* Program trace enable to low by using always false event */
 380         etm_writel(drvdata, ETM_HARD_WIRE_RES_A | ETM_EVENT_NOT_A, ETMTEEVR);
 381
 382         /* Read back sequencer and counters for post trace analysis */
 383         drvdata->seq_curr_state = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
 384
 385         for (i = 0; i < drvdata->nr_cntr; i++)
 386                 drvdata->cntr_val[i] = etm_readl(drvdata, ETMCNTVRn(i));
 387
 388         etm_set_pwrdwn(drvdata);
 389         CS_LOCK(drvdata->base);
 390
 391         dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
 392 }
 393
 394 static void etm_disable(struct coresight_device *csdev)
 395 {
 396         struct etm_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 397
 398         /*
 399          * Taking hotplug lock here protects from clocks getting disabled
 400          * with tracing being left on (crash scenario) if user disable occurs
 401          * after cpu online mask indicates the cpu is offline but before the
 402          * DYING hotplug callback is serviced by the ETM driver.
 403          */
 404         get_online_cpus();
 405         spin_lock(&drvdata->spinlock);
 406
 407         /*
 408          * Executing etm_disable_hw on the cpu whose ETM is being disabled
 409          * ensures that register writes occur when cpu is powered.
 410          */
 411         smp_call_function_single(drvdata->cpu, etm_disable_hw, drvdata, 1);
 412         drvdata->enable = false;
 413
 414         spin_unlock(&drvdata->spinlock);
 415         put_online_cpus();
 416         pm_runtime_put(csdev->dev.parent);
 417
 418         dev_info(drvdata->dev, "ETM tracing disabled\n");
 419 }
 420
 421 static const struct coresight_ops_source etm_source_ops = {
 422         .trace_id       = etm_trace_id,
 423         .enable         = etm_enable,
 424         .disable        = etm_disable,
 425 };
 426
 427 static const struct coresight_ops etm_cs_ops = {
 428         .source_ops     = &etm_source_ops,
 429 };
 430
 431 static ssize_t nr_addr_cmp_show(struct device *dev,
 432                                 struct device_attribute *attr, char *buf)
 433 {
 434         unsigned long val;
 435         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 436
 437         val = drvdata->nr_addr_cmp;
 438         return sprintf(buf, "%#lx\n", val);
 439 }
 440 static DEVICE_ATTR_RO(nr_addr_cmp);
 441
 442 static ssize_t nr_cntr_show(struct device *dev,
 443                             struct device_attribute *attr, char *buf)
 444 {       unsigned long val;
 445         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 446
 447         val = drvdata->nr_cntr;
 448         return sprintf(buf, "%#lx\n", val);
 449 }
 450 static DEVICE_ATTR_RO(nr_cntr);
 451
 452 static ssize_t nr_ctxid_cmp_show(struct device *dev,
 453                                  struct device_attribute *attr, char *buf)
 454 {
 455         unsigned long val;
 456         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 457
 458         val = drvdata->nr_ctxid_cmp;
 459         return sprintf(buf, "%#lx\n", val);
 460 }
 461 static DEVICE_ATTR_RO(nr_ctxid_cmp);
 462
 463 static ssize_t etmsr_show(struct device *dev,
 464                           struct device_attribute *attr, char *buf)
 465 {
 466         unsigned long flags, val;
 467         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 468
 469         pm_runtime_get_sync(drvdata->dev);
 470         spin_lock_irqsave(&drvdata->spinlock, flags);
 471         CS_UNLOCK(drvdata->base);
 472
 473         val = etm_readl(drvdata, ETMSR);
 474
 475         CS_LOCK(drvdata->base);
 476         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 477         pm_runtime_put(drvdata->dev);
 478
 479         return sprintf(buf, "%#lx\n", val);
 480 }
 481 static DEVICE_ATTR_RO(etmsr);
 482
 483 static ssize_t reset_store(struct device *dev,
 484                            struct device_attribute *attr,
 485                            const char *buf, size_t size)
 486 {
 487         int i, ret;
 488         unsigned long val;
 489         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 490
 491         ret = kstrtoul(buf, 16, &val);
 492         if (ret)
 493                 return ret;
 494
 495         if (val) {
 496                 spin_lock(&drvdata->spinlock);
 497                 drvdata->mode = ETM_MODE_EXCLUDE;
 498                 drvdata->ctrl = 0x0;
 499                 drvdata->trigger_event = ETM_DEFAULT_EVENT_VAL;
 500                 drvdata->startstop_ctrl = 0x0;
 501                 drvdata->addr_idx = 0x0;
 502                 for (i = 0; i < drvdata->nr_addr_cmp; i++) {
 503                         drvdata->addr_val[i] = 0x0;
 504                         drvdata->addr_acctype[i] = 0x0;
 505                         drvdata->addr_type[i] = ETM_ADDR_TYPE_NONE;
 506                 }
 507                 drvdata->cntr_idx = 0x0;
 508
 509                 etm_set_default(drvdata);
 510                 spin_unlock(&drvdata->spinlock);
 511         }
 512
 513         return size;
 514 }
 515 static DEVICE_ATTR_WO(reset);
 516
 517 static ssize_t mode_show(struct device *dev,
 518                          struct device_attribute *attr, char *buf)
 519 {
 520         unsigned long val;
 521         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 522
 523         val = drvdata->mode;
 524         return sprintf(buf, "%#lx\n", val);
 525 }
 526
 527 static ssize_t mode_store(struct device *dev,
 528                           struct device_attribute *attr,
 529                           const char *buf, size_t size)
 530 {
 531         int ret;
 532         unsigned long val;
 533         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 534
 535         ret = kstrtoul(buf, 16, &val);
 536         if (ret)
 537                 return ret;
 538
 539         spin_lock(&drvdata->spinlock);
 540         drvdata->mode = val & ETM_MODE_ALL;
 541
 542         if (drvdata->mode & ETM_MODE_EXCLUDE)
 543                 drvdata->enable_ctrl1 |= ETMTECR1_INC_EXC;
 544         else
 545                 drvdata->enable_ctrl1 &= ~ETMTECR1_INC_EXC;
 546
 547         if (drvdata->mode & ETM_MODE_CYCACC)
 548                 drvdata->ctrl |= ETMCR_CYC_ACC;
 549         else
 550                 drvdata->ctrl &= ~ETMCR_CYC_ACC;
 551
 552         if (drvdata->mode & ETM_MODE_STALL) {
 553                 if (!(drvdata->etmccr & ETMCCR_FIFOFULL)) {
 554                         dev_warn(drvdata->dev, "stall mode not supported\n");
 555                         ret = -EINVAL;
 556                         goto err_unlock;
 557                 }
 558                 drvdata->ctrl |= ETMCR_STALL_MODE;
 559          } else
 560                 drvdata->ctrl &= ~ETMCR_STALL_MODE;
 561
 562         if (drvdata->mode & ETM_MODE_TIMESTAMP) {
 563                 if (!(drvdata->etmccer & ETMCCER_TIMESTAMP)) {
 564                         dev_warn(drvdata->dev, "timestamp not supported\n");
 565                         ret = -EINVAL;
 566                         goto err_unlock;
 567                 }
 568                 drvdata->ctrl |= ETMCR_TIMESTAMP_EN;
 569         } else
 570                 drvdata->ctrl &= ~ETMCR_TIMESTAMP_EN;
 571
 572         if (drvdata->mode & ETM_MODE_CTXID)
 573                 drvdata->ctrl |= ETMCR_CTXID_SIZE;
 574         else
 575                 drvdata->ctrl &= ~ETMCR_CTXID_SIZE;
 576         spin_unlock(&drvdata->spinlock);
 577
 578         return size;
 579
 580 err_unlock:
 581         spin_unlock(&drvdata->spinlock);
 582         return ret;
 583 }
 584 static DEVICE_ATTR_RW(mode);
 585
 586 static ssize_t trigger_event_show(struct device *dev,
 587                                   struct device_attribute *attr, char *buf)
 588 {
 589         unsigned long val;
 590         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 591
 592         val = drvdata->trigger_event;
 593         return sprintf(buf, "%#lx\n", val);
 594 }
 595
 596 static ssize_t trigger_event_store(struct device *dev,
 597                                    struct device_attribute *attr,
 598                                    const char *buf, size_t size)
 599 {
 600         int ret;
 601         unsigned long val;
 602         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 603
 604         ret = kstrtoul(buf, 16, &val);
 605         if (ret)
 606                 return ret;
 607
 608         drvdata->trigger_event = val & ETM_EVENT_MASK;
 609
 610         return size;
 611 }
 612 static DEVICE_ATTR_RW(trigger_event);
 613
 614 static ssize_t enable_event_show(struct device *dev,
 615                                  struct device_attribute *attr, char *buf)
 616 {
 617         unsigned long val;
 618         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 619
 620         val = drvdata->enable_event;
 621         return sprintf(buf, "%#lx\n", val);
 622 }
 623
 624 static ssize_t enable_event_store(struct device *dev,
 625                                   struct device_attribute *attr,
 626                                   const char *buf, size_t size)
 627 {
 628         int ret;
 629         unsigned long val;
 630         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 631
 632         ret = kstrtoul(buf, 16, &val);
 633         if (ret)
 634                 return ret;
 635
 636         drvdata->enable_event = val & ETM_EVENT_MASK;
 637
 638         return size;
 639 }
 640 static DEVICE_ATTR_RW(enable_event);
 641
 642 static ssize_t fifofull_level_show(struct device *dev,
 643                                    struct device_attribute *attr, char *buf)
 644 {
 645         unsigned long val;
 646         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 647
 648         val = drvdata->fifofull_level;
 649         return sprintf(buf, "%#lx\n", val);
 650 }
 651
 652 static ssize_t fifofull_level_store(struct device *dev,
 653                                     struct device_attribute *attr,
 654                                     const char *buf, size_t size)
 655 {
 656         int ret;
 657         unsigned long val;
 658         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 659
 660         ret = kstrtoul(buf, 16, &val);
 661         if (ret)
 662                 return ret;
 663
 664         drvdata->fifofull_level = val;
 665
 666         return size;
 667 }
 668 static DEVICE_ATTR_RW(fifofull_level);
 669
 670 static ssize_t addr_idx_show(struct device *dev,
 671                              struct device_attribute *attr, char *buf)
 672 {
 673         unsigned long val;
 674         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 675
 676         val = drvdata->addr_idx;
 677         return sprintf(buf, "%#lx\n", val);
 678 }
 679
 680 static ssize_t addr_idx_store(struct device *dev,
 681                               struct device_attribute *attr,
 682                               const char *buf, size_t size)
 683 {
 684         int ret;
 685         unsigned long val;
 686         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 687
 688         ret = kstrtoul(buf, 16, &val);
 689         if (ret)
 690                 return ret;
 691
 692         if (val >= drvdata->nr_addr_cmp)
 693                 return -EINVAL;
 694
 695         /*
 696          * Use spinlock to ensure index doesn't change while it gets
 697          * dereferenced multiple times within a spinlock block elsewhere.
 698          */
 699         spin_lock(&drvdata->spinlock);
 700         drvdata->addr_idx = val;
 701         spin_unlock(&drvdata->spinlock);
 702
 703         return size;
 704 }
 705 static DEVICE_ATTR_RW(addr_idx);
 706
 707 static ssize_t addr_single_show(struct device *dev,
 708                                 struct device_attribute *attr, char *buf)
 709 {
 710         u8 idx;
 711         unsigned long val;
 712         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 713
 714         spin_lock(&drvdata->spinlock);
 715         idx = drvdata->addr_idx;
 716         if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
 717               drvdata->addr_type[idx] == ETM_ADDR_TYPE_SINGLE)) {
 718                 spin_unlock(&drvdata->spinlock);
 719                 return -EINVAL;
 720         }
 721
 722         val = drvdata->addr_val[idx];
 723         spin_unlock(&drvdata->spinlock);
 724
 725         return sprintf(buf, "%#lx\n", val);
 726 }
 727
 728 static ssize_t addr_single_store(struct device *dev,
 729                                  struct device_attribute *attr,
 730                                  const char *buf, size_t size)
 731 {
 732         u8 idx;
 733         int ret;
 734         unsigned long val;
 735         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 736
 737         ret = kstrtoul(buf, 16, &val);
 738         if (ret)
 739                 return ret;
 740
 741         spin_lock(&drvdata->spinlock);
 742         idx = drvdata->addr_idx;
 743         if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
 744               drvdata->addr_type[idx] == ETM_ADDR_TYPE_SINGLE)) {
 745                 spin_unlock(&drvdata->spinlock);
 746                 return -EINVAL;
 747         }
 748
 749         drvdata->addr_val[idx] = val;
 750         drvdata->addr_type[idx] = ETM_ADDR_TYPE_SINGLE;
 751         spin_unlock(&drvdata->spinlock);
 752
 753         return size;
 754 }
 755 static DEVICE_ATTR_RW(addr_single);
 756
 757 static ssize_t addr_range_show(struct device *dev,
 758                                struct device_attribute *attr, char *buf)
 759 {
 760         u8 idx;
 761         unsigned long val1, val2;
 762         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 763
 764         spin_lock(&drvdata->spinlock);
 765         idx = drvdata->addr_idx;
 766         if (idx % 2 != 0) {
 767                 spin_unlock(&drvdata->spinlock);
 768                 return -EPERM;
 769         }
 770         if (!((drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE &&
 771                drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_NONE) ||
 772               (drvdata->addr_type[idx] == ETM_ADDR_TYPE_RANGE &&
 773                drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_RANGE))) {
 774                 spin_unlock(&drvdata->spinlock);
 775                 return -EPERM;
 776         }
 777
 778         val1 = drvdata->addr_val[idx];
 779         val2 = drvdata->addr_val[idx + 1];
 780         spin_unlock(&drvdata->spinlock);
 781
 782         return sprintf(buf, "%#lx %#lx\n", val1, val2);
 783 }
 784
 785 static ssize_t addr_range_store(struct device *dev,
 786                               struct device_attribute *attr,
 787                               const char *buf, size_t size)
 788 {
 789         u8 idx;
 790         unsigned long val1, val2;
 791         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 792
 793         if (sscanf(buf, "%lx %lx", &val1, &val2) != 2)
 794                 return -EINVAL;
 795         /* Lower address comparator cannot have a higher address value */
 796         if (val1 > val2)
 797                 return -EINVAL;
 798
 799         spin_lock(&drvdata->spinlock);
 800         idx = drvdata->addr_idx;
 801         if (idx % 2 != 0) {
 802                 spin_unlock(&drvdata->spinlock);
 803                 return -EPERM;
 804         }
 805         if (!((drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE &&
 806                drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_NONE) ||
 807               (drvdata->addr_type[idx] == ETM_ADDR_TYPE_RANGE &&
 808                drvdata->addr_type[idx + 1] == ETM_ADDR_TYPE_RANGE))) {
 809                 spin_unlock(&drvdata->spinlock);
 810                 return -EPERM;
 811         }
 812
 813         drvdata->addr_val[idx] = val1;
 814         drvdata->addr_type[idx] = ETM_ADDR_TYPE_RANGE;
 815         drvdata->addr_val[idx + 1] = val2;
 816         drvdata->addr_type[idx + 1] = ETM_ADDR_TYPE_RANGE;
 817         drvdata->enable_ctrl1 |= (1 << (idx/2));
 818         spin_unlock(&drvdata->spinlock);
 819
 820         return size;
 821 }
 822 static DEVICE_ATTR_RW(addr_range);
 823
 824 static ssize_t addr_start_show(struct device *dev,
 825                                struct device_attribute *attr, char *buf)
 826 {
 827         u8 idx;
 828         unsigned long val;
 829         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 830
 831         spin_lock(&drvdata->spinlock);
 832         idx = drvdata->addr_idx;
 833         if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
 834               drvdata->addr_type[idx] == ETM_ADDR_TYPE_START)) {
 835                 spin_unlock(&drvdata->spinlock);
 836                 return -EPERM;
 837         }
 838
 839         val = drvdata->addr_val[idx];
 840         spin_unlock(&drvdata->spinlock);
 841
 842         return sprintf(buf, "%#lx\n", val);
 843 }
 844
 845 static ssize_t addr_start_store(struct device *dev,
 846                                 struct device_attribute *attr,
 847                                 const char *buf, size_t size)
 848 {
 849         u8 idx;
 850         int ret;
 851         unsigned long val;
 852         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 853
 854         ret = kstrtoul(buf, 16, &val);
 855         if (ret)
 856                 return ret;
 857
 858         spin_lock(&drvdata->spinlock);
 859         idx = drvdata->addr_idx;
 860         if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
 861               drvdata->addr_type[idx] == ETM_ADDR_TYPE_START)) {
 862                 spin_unlock(&drvdata->spinlock);
 863                 return -EPERM;
 864         }
 865
 866         drvdata->addr_val[idx] = val;
 867         drvdata->addr_type[idx] = ETM_ADDR_TYPE_START;
 868         drvdata->startstop_ctrl |= (1 << idx);
 869         drvdata->enable_ctrl1 |= BIT(25);
 870         spin_unlock(&drvdata->spinlock);
 871
 872         return size;
 873 }
 874 static DEVICE_ATTR_RW(addr_start);
 875
 876 static ssize_t addr_stop_show(struct device *dev,
 877                               struct device_attribute *attr, char *buf)
 878 {
 879         u8 idx;
 880         unsigned long val;
 881         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 882
 883         spin_lock(&drvdata->spinlock);
 884         idx = drvdata->addr_idx;
 885         if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
 886               drvdata->addr_type[idx] == ETM_ADDR_TYPE_STOP)) {
 887                 spin_unlock(&drvdata->spinlock);
 888                 return -EPERM;
 889         }
 890
 891         val = drvdata->addr_val[idx];
 892         spin_unlock(&drvdata->spinlock);
 893
 894         return sprintf(buf, "%#lx\n", val);
 895 }
 896
 897 static ssize_t addr_stop_store(struct device *dev,
 898                                struct device_attribute *attr,
 899                                const char *buf, size_t size)
 900 {
 901         u8 idx;
 902         int ret;
 903         unsigned long val;
 904         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 905
 906         ret = kstrtoul(buf, 16, &val);
 907         if (ret)
 908                 return ret;
 909
 910         spin_lock(&drvdata->spinlock);
 911         idx = drvdata->addr_idx;
 912         if (!(drvdata->addr_type[idx] == ETM_ADDR_TYPE_NONE ||
 913               drvdata->addr_type[idx] == ETM_ADDR_TYPE_STOP)) {
 914                 spin_unlock(&drvdata->spinlock);
 915                 return -EPERM;
 916         }
 917
 918         drvdata->addr_val[idx] = val;
 919         drvdata->addr_type[idx] = ETM_ADDR_TYPE_STOP;
 920         drvdata->startstop_ctrl |= (1 << (idx + 16));
 921         drvdata->enable_ctrl1 |= ETMTECR1_START_STOP;
 922         spin_unlock(&drvdata->spinlock);
 923
 924         return size;
 925 }
 926 static DEVICE_ATTR_RW(addr_stop);
 927
 928 static ssize_t addr_acctype_show(struct device *dev,
 929                                  struct device_attribute *attr, char *buf)
 930 {
 931         unsigned long val;
 932         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 933
 934         spin_lock(&drvdata->spinlock);
 935         val = drvdata->addr_acctype[drvdata->addr_idx];
 936         spin_unlock(&drvdata->spinlock);
 937
 938         return sprintf(buf, "%#lx\n", val);
 939 }
 940
 941 static ssize_t addr_acctype_store(struct device *dev,
 942                                   struct device_attribute *attr,
 943                                   const char *buf, size_t size)
 944 {
 945         int ret;
 946         unsigned long val;
 947         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 948
 949         ret = kstrtoul(buf, 16, &val);
 950         if (ret)
 951                 return ret;
 952
 953         spin_lock(&drvdata->spinlock);
 954         drvdata->addr_acctype[drvdata->addr_idx] = val;
 955         spin_unlock(&drvdata->spinlock);
 956
 957         return size;
 958 }
 959 static DEVICE_ATTR_RW(addr_acctype);
 960
 961 static ssize_t cntr_idx_show(struct device *dev,
 962                              struct device_attribute *attr, char *buf)
 963 {
 964         unsigned long val;
 965         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 966
 967         val = drvdata->cntr_idx;
 968         return sprintf(buf, "%#lx\n", val);
 969 }
 970
 971 static ssize_t cntr_idx_store(struct device *dev,
 972                               struct device_attribute *attr,
 973                               const char *buf, size_t size)
 974 {
 975         int ret;
 976         unsigned long val;
 977         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
 978
 979         ret = kstrtoul(buf, 16, &val);
 980         if (ret)
 981                 return ret;
 982
 983         if (val >= drvdata->nr_cntr)
 984                 return -EINVAL;
 985         /*
 986          * Use spinlock to ensure index doesn't change while it gets
 987          * dereferenced multiple times within a spinlock block elsewhere.
 988          */
 989         spin_lock(&drvdata->spinlock);
 990         drvdata->cntr_idx = val;
 991         spin_unlock(&drvdata->spinlock);
 992
 993         return size;
 994 }
 995 static DEVICE_ATTR_RW(cntr_idx);
 996
 997 static ssize_t cntr_rld_val_show(struct device *dev,
 998                                  struct device_attribute *attr, char *buf)
 999 {
1000         unsigned long val;
1001         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1002
1003         spin_lock(&drvdata->spinlock);
1004         val = drvdata->cntr_rld_val[drvdata->cntr_idx];
1005         spin_unlock(&drvdata->spinlock);
1006
1007         return sprintf(buf, "%#lx\n", val);
1008 }
1009
1010 static ssize_t cntr_rld_val_store(struct device *dev,
1011                                   struct device_attribute *attr,
1012                                   const char *buf, size_t size)
1013 {
1014         int ret;
1015         unsigned long val;
1016         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1017
1018         ret = kstrtoul(buf, 16, &val);
1019         if (ret)
1020                 return ret;
1021
1022         spin_lock(&drvdata->spinlock);
1023         drvdata->cntr_rld_val[drvdata->cntr_idx] = val;
1024         spin_unlock(&drvdata->spinlock);
1025
1026         return size;
1027 }
1028 static DEVICE_ATTR_RW(cntr_rld_val);
1029
1030 static ssize_t cntr_event_show(struct device *dev,
1031                                struct device_attribute *attr, char *buf)
1032 {
1033         unsigned long val;
1034         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1035
1036         spin_lock(&drvdata->spinlock);
1037         val = drvdata->cntr_event[drvdata->cntr_idx];
1038         spin_unlock(&drvdata->spinlock);
1039
1040         return sprintf(buf, "%#lx\n", val);
1041 }
1042
1043 static ssize_t cntr_event_store(struct device *dev,
1044                                 struct device_attribute *attr,
1045                                 const char *buf, size_t size)
1046 {
1047         int ret;
1048         unsigned long val;
1049         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1050
1051         ret = kstrtoul(buf, 16, &val);
1052         if (ret)
1053                 return ret;
1054
1055         spin_lock(&drvdata->spinlock);
1056         drvdata->cntr_event[drvdata->cntr_idx] = val & ETM_EVENT_MASK;
1057         spin_unlock(&drvdata->spinlock);
1058
1059         return size;
1060 }
1061 static DEVICE_ATTR_RW(cntr_event);
1062
1063 static ssize_t cntr_rld_event_show(struct device *dev,
1064                                    struct device_attribute *attr, char *buf)
1065 {
1066         unsigned long val;
1067         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1068
1069         spin_lock(&drvdata->spinlock);
1070         val = drvdata->cntr_rld_event[drvdata->cntr_idx];
1071         spin_unlock(&drvdata->spinlock);
1072
1073         return sprintf(buf, "%#lx\n", val);
1074 }
1075
1076 static ssize_t cntr_rld_event_store(struct device *dev,
1077                                     struct device_attribute *attr,
1078                                     const char *buf, size_t size)
1079 {
1080         int ret;
1081         unsigned long val;
1082         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1083
1084         ret = kstrtoul(buf, 16, &val);
1085         if (ret)
1086                 return ret;
1087
1088         spin_lock(&drvdata->spinlock);
1089         drvdata->cntr_rld_event[drvdata->cntr_idx] = val & ETM_EVENT_MASK;
1090         spin_unlock(&drvdata->spinlock);
1091
1092         return size;
1093 }
1094 static DEVICE_ATTR_RW(cntr_rld_event);
1095
1096 static ssize_t cntr_val_show(struct device *dev,
1097                              struct device_attribute *attr, char *buf)
1098 {
1099         int i, ret = 0;
1100         u32 val;
1101         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1102
1103         if (!drvdata->enable) {
1104                 spin_lock(&drvdata->spinlock);
1105                 for (i = 0; i < drvdata->nr_cntr; i++)
1106                         ret += sprintf(buf, "counter %d: %x\n",
1107                                        i, drvdata->cntr_val[i]);
1108                 spin_unlock(&drvdata->spinlock);
1109                 return ret;
1110         }
1111
1112         for (i = 0; i < drvdata->nr_cntr; i++) {
1113                 val = etm_readl(drvdata, ETMCNTVRn(i));
1114                 ret += sprintf(buf, "counter %d: %x\n", i, val);
1115         }
1116
1117         return ret;
1118 }
1119
1120 static ssize_t cntr_val_store(struct device *dev,
1121                               struct device_attribute *attr,
1122                               const char *buf, size_t size)
1123 {
1124         int ret;
1125         unsigned long val;
1126         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1127
1128         ret = kstrtoul(buf, 16, &val);
1129         if (ret)
1130                 return ret;
1131
1132         spin_lock(&drvdata->spinlock);
1133         drvdata->cntr_val[drvdata->cntr_idx] = val;
1134         spin_unlock(&drvdata->spinlock);
1135
1136         return size;
1137 }
1138 static DEVICE_ATTR_RW(cntr_val);
1139
1140 static ssize_t seq_12_event_show(struct device *dev,
1141                                  struct device_attribute *attr, char *buf)
1142 {
1143         unsigned long val;
1144         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1145
1146         val = drvdata->seq_12_event;
1147         return sprintf(buf, "%#lx\n", val);
1148 }
1149
1150 static ssize_t seq_12_event_store(struct device *dev,
1151                                   struct device_attribute *attr,
1152                                   const char *buf, size_t size)
1153 {
1154         int ret;
1155         unsigned long val;
1156         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1157
1158         ret = kstrtoul(buf, 16, &val);
1159         if (ret)
1160                 return ret;
1161
1162         drvdata->seq_12_event = val & ETM_EVENT_MASK;
1163         return size;
1164 }
1165 static DEVICE_ATTR_RW(seq_12_event);
1166
1167 static ssize_t seq_21_event_show(struct device *dev,
1168                                  struct device_attribute *attr, char *buf)
1169 {
1170         unsigned long val;
1171         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1172
1173         val = drvdata->seq_21_event;
1174         return sprintf(buf, "%#lx\n", val);
1175 }
1176
1177 static ssize_t seq_21_event_store(struct device *dev,
1178                                   struct device_attribute *attr,
1179                                   const char *buf, size_t size)
1180 {
1181         int ret;
1182         unsigned long val;
1183         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1184
1185         ret = kstrtoul(buf, 16, &val);
1186         if (ret)
1187                 return ret;
1188
1189         drvdata->seq_21_event = val & ETM_EVENT_MASK;
1190         return size;
1191 }
1192 static DEVICE_ATTR_RW(seq_21_event);
1193
1194 static ssize_t seq_23_event_show(struct device *dev,
1195                                  struct device_attribute *attr, char *buf)
1196 {
1197         unsigned long val;
1198         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1199
1200         val = drvdata->seq_23_event;
1201         return sprintf(buf, "%#lx\n", val);
1202 }
1203
1204 static ssize_t seq_23_event_store(struct device *dev,
1205                                   struct device_attribute *attr,
1206                                   const char *buf, size_t size)
1207 {
1208         int ret;
1209         unsigned long val;
1210         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1211
1212         ret = kstrtoul(buf, 16, &val);
1213         if (ret)
1214                 return ret;
1215
1216         drvdata->seq_23_event = val & ETM_EVENT_MASK;
1217         return size;
1218 }
1219 static DEVICE_ATTR_RW(seq_23_event);
1220
1221 static ssize_t seq_31_event_show(struct device *dev,
1222                                  struct device_attribute *attr, char *buf)
1223 {
1224         unsigned long val;
1225         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1226
1227         val = drvdata->seq_31_event;
1228         return sprintf(buf, "%#lx\n", val);
1229 }
1230
1231 static ssize_t seq_31_event_store(struct device *dev,
1232                                   struct device_attribute *attr,
1233                                   const char *buf, size_t size)
1234 {
1235         int ret;
1236         unsigned long val;
1237         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1238
1239         ret = kstrtoul(buf, 16, &val);
1240         if (ret)
1241                 return ret;
1242
1243         drvdata->seq_31_event = val & ETM_EVENT_MASK;
1244         return size;
1245 }
1246 static DEVICE_ATTR_RW(seq_31_event);
1247
1248 static ssize_t seq_32_event_show(struct device *dev,
1249                                  struct device_attribute *attr, char *buf)
1250 {
1251         unsigned long val;
1252         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1253
1254         val = drvdata->seq_32_event;
1255         return sprintf(buf, "%#lx\n", val);
1256 }
1257
1258 static ssize_t seq_32_event_store(struct device *dev,
1259                                   struct device_attribute *attr,
1260                                   const char *buf, size_t size)
1261 {
1262         int ret;
1263         unsigned long val;
1264         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1265
1266         ret = kstrtoul(buf, 16, &val);
1267         if (ret)
1268                 return ret;
1269
1270         drvdata->seq_32_event = val & ETM_EVENT_MASK;
1271         return size;
1272 }
1273 static DEVICE_ATTR_RW(seq_32_event);
1274
1275 static ssize_t seq_13_event_show(struct device *dev,
1276                                  struct device_attribute *attr, char *buf)
1277 {
1278         unsigned long val;
1279         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1280
1281         val = drvdata->seq_13_event;
1282         return sprintf(buf, "%#lx\n", val);
1283 }
1284
1285 static ssize_t seq_13_event_store(struct device *dev,
1286                                   struct device_attribute *attr,
1287                                   const char *buf, size_t size)
1288 {
1289         int ret;
1290         unsigned long val;
1291         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1292
1293         ret = kstrtoul(buf, 16, &val);
1294         if (ret)
1295                 return ret;
1296
1297         drvdata->seq_13_event = val & ETM_EVENT_MASK;
1298         return size;
1299 }
1300 static DEVICE_ATTR_RW(seq_13_event);
1301
1302 static ssize_t seq_curr_state_show(struct device *dev,
1303                                    struct device_attribute *attr, char *buf)
1304 {
1305         unsigned long val, flags;
1306         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1307
1308         if (!drvdata->enable) {
1309                 val = drvdata->seq_curr_state;
1310                 goto out;
1311         }
1312
1313         pm_runtime_get_sync(drvdata->dev);
1314         spin_lock_irqsave(&drvdata->spinlock, flags);
1315
1316         CS_UNLOCK(drvdata->base);
1317         val = (etm_readl(drvdata, ETMSQR) & ETM_SQR_MASK);
1318         CS_LOCK(drvdata->base);
1319
1320         spin_unlock_irqrestore(&drvdata->spinlock, flags);
1321         pm_runtime_put(drvdata->dev);
1322 out:
1323         return sprintf(buf, "%#lx\n", val);
1324 }
1325
1326 static ssize_t seq_curr_state_store(struct device *dev,
1327                                     struct device_attribute *attr,
1328                                     const char *buf, size_t size)
1329 {
1330         int ret;
1331         unsigned long val;
1332         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1333
1334         ret = kstrtoul(buf, 16, &val);
1335         if (ret)
1336                 return ret;
1337
1338         if (val > ETM_SEQ_STATE_MAX_VAL)
1339                 return -EINVAL;
1340
1341         drvdata->seq_curr_state = val;
1342
1343         return size;
1344 }
1345 static DEVICE_ATTR_RW(seq_curr_state);
1346
1347 static ssize_t ctxid_idx_show(struct device *dev,
1348                               struct device_attribute *attr, char *buf)
1349 {
1350         unsigned long val;
1351         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1352
1353         val = drvdata->ctxid_idx;
1354         return sprintf(buf, "%#lx\n", val);
1355 }
1356
1357 static ssize_t ctxid_idx_store(struct device *dev,
1358                                 struct device_attribute *attr,
1359                                 const char *buf, size_t size)
1360 {
1361         int ret;
1362         unsigned long val;
1363         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1364
1365         ret = kstrtoul(buf, 16, &val);
1366         if (ret)
1367                 return ret;
1368
1369         if (val >= drvdata->nr_ctxid_cmp)
1370                 return -EINVAL;
1371
1372         /*
1373          * Use spinlock to ensure index doesn't change while it gets
1374          * dereferenced multiple times within a spinlock block elsewhere.
1375          */
1376         spin_lock(&drvdata->spinlock);
1377         drvdata->ctxid_idx = val;
1378         spin_unlock(&drvdata->spinlock);
1379
1380         return size;
1381 }
1382 static DEVICE_ATTR_RW(ctxid_idx);
1383
1384 static ssize_t ctxid_pid_show(struct device *dev,
1385                               struct device_attribute *attr, char *buf)
1386 {
1387         unsigned long val;
1388         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1389
1390         spin_lock(&drvdata->spinlock);
1391         val = drvdata->ctxid_vpid[drvdata->ctxid_idx];
1392         spin_unlock(&drvdata->spinlock);
1393
1394         return sprintf(buf, "%#lx\n", val);
1395 }
1396
1397 static ssize_t ctxid_pid_store(struct device *dev,
1398                                struct device_attribute *attr,
1399                                const char *buf, size_t size)
1400 {
1401         int ret;
1402         unsigned long vpid, pid;
1403         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1404
1405         ret = kstrtoul(buf, 16, &vpid);
1406         if (ret)
1407                 return ret;
1408
1409         pid = coresight_vpid_to_pid(vpid);
1410
1411         spin_lock(&drvdata->spinlock);
1412         drvdata->ctxid_pid[drvdata->ctxid_idx] = pid;
1413         drvdata->ctxid_vpid[drvdata->ctxid_idx] = vpid;
1414         spin_unlock(&drvdata->spinlock);
1415
1416         return size;
1417 }
1418 static DEVICE_ATTR_RW(ctxid_pid);
1419
1420 static ssize_t ctxid_mask_show(struct device *dev,
1421                                struct device_attribute *attr, char *buf)
1422 {
1423         unsigned long val;
1424         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1425
1426         val = drvdata->ctxid_mask;
1427         return sprintf(buf, "%#lx\n", val);
1428 }
1429
1430 static ssize_t ctxid_mask_store(struct device *dev,
1431                                 struct device_attribute *attr,
1432                                 const char *buf, size_t size)
1433 {
1434         int ret;
1435         unsigned long val;
1436         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1437
1438         ret = kstrtoul(buf, 16, &val);
1439         if (ret)
1440                 return ret;
1441
1442         drvdata->ctxid_mask = val;
1443         return size;
1444 }
1445 static DEVICE_ATTR_RW(ctxid_mask);
1446
1447 static ssize_t sync_freq_show(struct device *dev,
1448                               struct device_attribute *attr, char *buf)
1449 {
1450         unsigned long val;
1451         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1452
1453         val = drvdata->sync_freq;
1454         return sprintf(buf, "%#lx\n", val);
1455 }
1456
1457 static ssize_t sync_freq_store(struct device *dev,
1458                                struct device_attribute *attr,
1459                                const char *buf, size_t size)
1460 {
1461         int ret;
1462         unsigned long val;
1463         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1464
1465         ret = kstrtoul(buf, 16, &val);
1466         if (ret)
1467                 return ret;
1468
1469         drvdata->sync_freq = val & ETM_SYNC_MASK;
1470         return size;
1471 }
1472 static DEVICE_ATTR_RW(sync_freq);
1473
1474 static ssize_t timestamp_event_show(struct device *dev,
1475                                     struct device_attribute *attr, char *buf)
1476 {
1477         unsigned long val;
1478         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1479
1480         val = drvdata->timestamp_event;
1481         return sprintf(buf, "%#lx\n", val);
1482 }
1483
1484 static ssize_t timestamp_event_store(struct device *dev,
1485                                      struct device_attribute *attr,
1486                                      const char *buf, size_t size)
1487 {
1488         int ret;
1489         unsigned long val;
1490         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1491
1492         ret = kstrtoul(buf, 16, &val);
1493         if (ret)
1494                 return ret;
1495
1496         drvdata->timestamp_event = val & ETM_EVENT_MASK;
1497         return size;
1498 }
1499 static DEVICE_ATTR_RW(timestamp_event);
1500
1501 static ssize_t cpu_show(struct device *dev,
1502                         struct device_attribute *attr, char *buf)
1503 {
1504         int val;
1505         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1506
1507         val = drvdata->cpu;
1508         return scnprintf(buf, PAGE_SIZE, "%d\n", val);
1509
1510 }
1511 static DEVICE_ATTR_RO(cpu);
1512
1513 static ssize_t traceid_show(struct device *dev,
1514                             struct device_attribute *attr, char *buf)
1515 {
1516         unsigned long val, flags;
1517         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1518
1519         if (!drvdata->enable) {
1520                 val = drvdata->traceid;
1521                 goto out;
1522         }
1523
1524         pm_runtime_get_sync(drvdata->dev);
1525         spin_lock_irqsave(&drvdata->spinlock, flags);
1526         CS_UNLOCK(drvdata->base);
1527
1528         val = (etm_readl(drvdata, ETMTRACEIDR) & ETM_TRACEID_MASK);
1529
1530         CS_LOCK(drvdata->base);
1531         spin_unlock_irqrestore(&drvdata->spinlock, flags);
1532         pm_runtime_put(drvdata->dev);
1533 out:
1534         return sprintf(buf, "%#lx\n", val);
1535 }
1536
1537 static ssize_t traceid_store(struct device *dev,
1538                              struct device_attribute *attr,
1539                              const char *buf, size_t size)
1540 {
1541         int ret;
1542         unsigned long val;
1543         struct etm_drvdata *drvdata = dev_get_drvdata(dev->parent);
1544
1545         ret = kstrtoul(buf, 16, &val);
1546         if (ret)
1547                 return ret;
1548
1549         drvdata->traceid = val & ETM_TRACEID_MASK;
1550         return size;
1551 }
1552 static DEVICE_ATTR_RW(traceid);
1553
1554 static struct attribute *coresight_etm_attrs[] = {
1555         &dev_attr_nr_addr_cmp.attr,
1556         &dev_attr_nr_cntr.attr,
1557         &dev_attr_nr_ctxid_cmp.attr,
1558         &dev_attr_etmsr.attr,
1559         &dev_attr_reset.attr,
1560         &dev_attr_mode.attr,
1561         &dev_attr_trigger_event.attr,
1562         &dev_attr_enable_event.attr,
1563         &dev_attr_fifofull_level.attr,
1564         &dev_attr_addr_idx.attr,
1565         &dev_attr_addr_single.attr,
1566         &dev_attr_addr_range.attr,
1567         &dev_attr_addr_start.attr,
1568         &dev_attr_addr_stop.attr,
1569         &dev_attr_addr_acctype.attr,
1570         &dev_attr_cntr_idx.attr,
1571         &dev_attr_cntr_rld_val.attr,
1572         &dev_attr_cntr_event.attr,
1573         &dev_attr_cntr_rld_event.attr,
1574         &dev_attr_cntr_val.attr,
1575         &dev_attr_seq_12_event.attr,
1576         &dev_attr_seq_21_event.attr,
1577         &dev_attr_seq_23_event.attr,
1578         &dev_attr_seq_31_event.attr,
1579         &dev_attr_seq_32_event.attr,
1580         &dev_attr_seq_13_event.attr,
1581         &dev_attr_seq_curr_state.attr,
1582         &dev_attr_ctxid_idx.attr,
1583         &dev_attr_ctxid_pid.attr,
1584         &dev_attr_ctxid_mask.attr,
1585         &dev_attr_sync_freq.attr,
1586         &dev_attr_timestamp_event.attr,
1587         &dev_attr_traceid.attr,
1588         &dev_attr_cpu.attr,
1589         NULL,
1590 };
1591
1592 #define coresight_simple_func(name, offset)                             \
1593 static ssize_t name##_show(struct device *_dev,                         \
1594                            struct device_attribute *attr, char *buf)    \
1595 {                                                                       \
1596         struct etm_drvdata *drvdata = dev_get_drvdata(_dev->parent);    \
1597         return scnprintf(buf, PAGE_SIZE, "0x%x\n",                      \
1598                          readl_relaxed(drvdata->base + offset));        \
1599 }                                                                       \
1600 DEVICE_ATTR_RO(name)
1601
1602 coresight_simple_func(etmccr, ETMCCR);
1603 coresight_simple_func(etmccer, ETMCCER);
1604 coresight_simple_func(etmscr, ETMSCR);
1605 coresight_simple_func(etmidr, ETMIDR);
1606 coresight_simple_func(etmcr, ETMCR);
1607 coresight_simple_func(etmtraceidr, ETMTRACEIDR);
1608 coresight_simple_func(etmteevr, ETMTEEVR);
1609 coresight_simple_func(etmtssvr, ETMTSSCR);
1610 coresight_simple_func(etmtecr1, ETMTECR1);
1611 coresight_simple_func(etmtecr2, ETMTECR2);
1612
1613 static struct attribute *coresight_etm_mgmt_attrs[] = {
1614         &dev_attr_etmccr.attr,
1615         &dev_attr_etmccer.attr,
1616         &dev_attr_etmscr.attr,
1617         &dev_attr_etmidr.attr,
1618         &dev_attr_etmcr.attr,
1619         &dev_attr_etmtraceidr.attr,
1620         &dev_attr_etmteevr.attr,
1621         &dev_attr_etmtssvr.attr,
1622         &dev_attr_etmtecr1.attr,
1623         &dev_attr_etmtecr2.attr,
1624         NULL,
1625 };
1626
1627 static const struct attribute_group coresight_etm_group = {
1628         .attrs = coresight_etm_attrs,
1629 };
1630
1631
1632 static const struct attribute_group coresight_etm_mgmt_group = {
1633         .attrs = coresight_etm_mgmt_attrs,
1634         .name = "mgmt",
1635 };
1636
1637 static const struct attribute_group *coresight_etm_groups[] = {
1638         &coresight_etm_group,
1639         &coresight_etm_mgmt_group,
1640         NULL,
1641 };
1642
1643 static int etm_cpu_callback(struct notifier_block *nfb, unsigned long action,
1644                             void *hcpu)
1645 {
1646         unsigned int cpu = (unsigned long)hcpu;
1647
1648         if (!etmdrvdata[cpu])
1649                 goto out;
1650
1651         switch (action & (~CPU_TASKS_FROZEN)) {
1652         case CPU_STARTING:
1653                 spin_lock(&etmdrvdata[cpu]->spinlock);
1654                 if (!etmdrvdata[cpu]->os_unlock) {
1655                         etm_os_unlock(etmdrvdata[cpu]);
1656                         etmdrvdata[cpu]->os_unlock = true;
1657                 }
1658
1659                 if (etmdrvdata[cpu]->enable)
1660                         etm_enable_hw(etmdrvdata[cpu]);
1661                 spin_unlock(&etmdrvdata[cpu]->spinlock);
1662                 break;
1663
1664         case CPU_ONLINE:
1665                 if (etmdrvdata[cpu]->boot_enable &&
1666                     !etmdrvdata[cpu]->sticky_enable)
1667                         coresight_enable(etmdrvdata[cpu]->csdev);
1668                 break;
1669
1670         case CPU_DYING:
1671                 spin_lock(&etmdrvdata[cpu]->spinlock);
1672                 if (etmdrvdata[cpu]->enable)
1673                         etm_disable_hw(etmdrvdata[cpu]);
1674                 spin_unlock(&etmdrvdata[cpu]->spinlock);
1675                 break;
1676         }
1677 out:
1678         return NOTIFY_OK;
1679 }
1680
1681 static struct notifier_block etm_cpu_notifier = {
1682         .notifier_call = etm_cpu_callback,
1683 };
1684
1685 static bool etm_arch_supported(u8 arch)
1686 {
1687         switch (arch) {
1688         case ETM_ARCH_V3_3:
1689                 break;
1690         case ETM_ARCH_V3_5:
1691                 break;
1692         case PFT_ARCH_V1_0:
1693                 break;
1694         case PFT_ARCH_V1_1:
1695                 break;
1696         default:
1697                 return false;
1698         }
1699         return true;
1700 }
1701
1702 static void etm_init_arch_data(void *info)
1703 {
1704         u32 etmidr;
1705         u32 etmccr;
1706         struct etm_drvdata *drvdata = info;
1707
1708         CS_UNLOCK(drvdata->base);
1709
1710         /* First dummy read */
1711         (void)etm_readl(drvdata, ETMPDSR);
1712         /* Provide power to ETM: ETMPDCR[3] == 1 */
1713         etm_set_pwrup(drvdata);
1714         /*
1715          * Clear power down bit since when this bit is set writes to
1716          * certain registers might be ignored.
1717          */
1718         etm_clr_pwrdwn(drvdata);
1719         /*
1720          * Set prog bit. It will be set from reset but this is included to
1721          * ensure it is set
1722          */
1723         etm_set_prog(drvdata);
1724
1725         /* Find all capabilities */
1726         etmidr = etm_readl(drvdata, ETMIDR);
1727         drvdata->arch = BMVAL(etmidr, 4, 11);
1728         drvdata->port_size = etm_readl(drvdata, ETMCR) & PORT_SIZE_MASK;
1729
1730         drvdata->etmccer = etm_readl(drvdata, ETMCCER);
1731         etmccr = etm_readl(drvdata, ETMCCR);
1732         drvdata->etmccr = etmccr;
1733         drvdata->nr_addr_cmp = BMVAL(etmccr, 0, 3) * 2;
1734         drvdata->nr_cntr = BMVAL(etmccr, 13, 15);
1735         drvdata->nr_ext_inp = BMVAL(etmccr, 17, 19);
1736         drvdata->nr_ext_out = BMVAL(etmccr, 20, 22);
1737         drvdata->nr_ctxid_cmp = BMVAL(etmccr, 24, 25);
1738
1739         etm_set_pwrdwn(drvdata);
1740         etm_clr_pwrup(drvdata);
1741         CS_LOCK(drvdata->base);
1742 }
1743
1744 static void etm_init_default_data(struct etm_drvdata *drvdata)
1745 {
1746         /*
1747          * A trace ID of value 0 is invalid, so let's start at some
1748          * random value that fits in 7 bits and will be just as good.
1749          */
1750         static int etm3x_traceid = 0x10;
1751
1752         u32 flags = (1 << 0 | /* instruction execute*/
1753                      3 << 3 | /* ARM instruction */
1754                      0 << 5 | /* No data value comparison */
1755                      0 << 7 | /* No exact mach */
1756                      0 << 8 | /* Ignore context ID */
1757                      0 << 10); /* Security ignored */
1758
1759         /*
1760          * Initial configuration only - guarantees sources handled by
1761          * this driver have a unique ID at startup time but not between
1762          * all other types of sources.  For that we lean on the core
1763          * framework.
1764          */
1765         drvdata->traceid = etm3x_traceid++;
1766         drvdata->ctrl = (ETMCR_CYC_ACC | ETMCR_TIMESTAMP_EN);
1767         drvdata->enable_ctrl1 = ETMTECR1_ADDR_COMP_1;
1768         if (drvdata->nr_addr_cmp >= 2) {
1769                 drvdata->addr_val[0] = (u32) _stext;
1770                 drvdata->addr_val[1] = (u32) _etext;
1771                 drvdata->addr_acctype[0] = flags;
1772                 drvdata->addr_acctype[1] = flags;
1773                 drvdata->addr_type[0] = ETM_ADDR_TYPE_RANGE;
1774                 drvdata->addr_type[1] = ETM_ADDR_TYPE_RANGE;
1775         }
1776
1777         etm_set_default(drvdata);
1778 }
1779
1780 static int etm_probe(struct amba_device *adev, const struct amba_id *id)
1781 {
1782         int ret;
1783         void __iomem *base;
1784         struct device *dev = &adev->dev;
1785         struct coresight_platform_data *pdata = NULL;
1786         struct etm_drvdata *drvdata;
1787         struct resource *res = &adev->res;
1788         struct coresight_desc *desc;
1789         struct device_node *np = adev->dev.of_node;
1790
1791         desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
1792         if (!desc)
1793                 return -ENOMEM;
1794
1795         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
1796         if (!drvdata)
1797                 return -ENOMEM;
1798
1799         if (np) {
1800                 pdata = of_get_coresight_platform_data(dev, np);
1801                 if (IS_ERR(pdata))
1802                         return PTR_ERR(pdata);
1803
1804                 adev->dev.platform_data = pdata;
1805                 drvdata->use_cp14 = of_property_read_bool(np, "arm,cp14");
1806         }
1807
1808         drvdata->dev = &adev->dev;
1809         dev_set_drvdata(dev, drvdata);
1810
1811         /* Validity for the resource is already checked by the AMBA core */
1812         base = devm_ioremap_resource(dev, res);
1813         if (IS_ERR(base))
1814                 return PTR_ERR(base);
1815
1816         drvdata->base = base;
1817
1818         spin_lock_init(&drvdata->spinlock);
1819
1820         drvdata->atclk = devm_clk_get(&adev->dev, "atclk"); /* optional */
1821         if (!IS_ERR(drvdata->atclk)) {
1822                 ret = clk_prepare_enable(drvdata->atclk);
1823                 if (ret)
1824                         return ret;
1825         }
1826
1827         drvdata->cpu = pdata ? pdata->cpu : 0;
1828
1829         get_online_cpus();
1830         etmdrvdata[drvdata->cpu] = drvdata;
1831
1832         if (!smp_call_function_single(drvdata->cpu, etm_os_unlock, drvdata, 1))
1833                 drvdata->os_unlock = true;
1834
1835         if (smp_call_function_single(drvdata->cpu,
1836                                      etm_init_arch_data,  drvdata, 1))
1837                 dev_err(dev, "ETM arch init failed\n");
1838
1839         if (!etm_count++)
1840                 register_hotcpu_notifier(&etm_cpu_notifier);
1841
1842         put_online_cpus();
1843
1844         if (etm_arch_supported(drvdata->arch) == false) {
1845                 ret = -EINVAL;
1846                 goto err_arch_supported;
1847         }
1848         etm_init_default_data(drvdata);
1849
1850         desc->type = CORESIGHT_DEV_TYPE_SOURCE;
1851         desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
1852         desc->ops = &etm_cs_ops;
1853         desc->pdata = pdata;
1854         desc->dev = dev;
1855         desc->groups = coresight_etm_groups;
1856         drvdata->csdev = coresight_register(desc);
1857         if (IS_ERR(drvdata->csdev)) {
1858                 ret = PTR_ERR(drvdata->csdev);
1859                 goto err_arch_supported;
1860         }
1861
1862         pm_runtime_put(&adev->dev);
1863         dev_info(dev, "%s initialized\n", (char *)id->data);
1864
1865         if (boot_enable) {
1866                 coresight_enable(drvdata->csdev);
1867                 drvdata->boot_enable = true;
1868         }
1869
1870         return 0;
1871
1872 err_arch_supported:
1873         if (--etm_count == 0)
1874                 unregister_hotcpu_notifier(&etm_cpu_notifier);
1875         return ret;
1876 }
1877
1878 static int etm_remove(struct amba_device *adev)
1879 {
1880         struct etm_drvdata *drvdata = amba_get_drvdata(adev);
1881
1882         coresight_unregister(drvdata->csdev);
1883         if (--etm_count == 0)
1884                 unregister_hotcpu_notifier(&etm_cpu_notifier);
1885
1886         return 0;
1887 }
1888
1889 #ifdef CONFIG_PM
1890 static int etm_runtime_suspend(struct device *dev)
1891 {
1892         struct etm_drvdata *drvdata = dev_get_drvdata(dev);
1893
1894         if (drvdata && !IS_ERR(drvdata->atclk))
1895                 clk_disable_unprepare(drvdata->atclk);
1896
1897         return 0;
1898 }
1899
1900 static int etm_runtime_resume(struct device *dev)
1901 {
1902         struct etm_drvdata *drvdata = dev_get_drvdata(dev);
1903
1904         if (drvdata && !IS_ERR(drvdata->atclk))
1905                 clk_prepare_enable(drvdata->atclk);
1906
1907         return 0;
1908 }
1909 #endif
1910
1911 static const struct dev_pm_ops etm_dev_pm_ops = {
1912         SET_RUNTIME_PM_OPS(etm_runtime_suspend, etm_runtime_resume, NULL)
1913 };
1914
1915 static struct amba_id etm_ids[] = {
1916         {       /* ETM 3.3 */
1917                 .id     = 0x0003b921,
1918                 .mask   = 0x0003ffff,
1919                 .data   = "ETM 3.3",
1920         },
1921         {       /* ETM 3.5 */
1922                 .id     = 0x0003b956,
1923                 .mask   = 0x0003ffff,
1924                 .data   = "ETM 3.5",
1925         },
1926         {       /* PTM 1.0 */
1927                 .id     = 0x0003b950,
1928                 .mask   = 0x0003ffff,
1929                 .data   = "PTM 1.0",
1930         },
1931         {       /* PTM 1.1 */
1932                 .id     = 0x0003b95f,
1933                 .mask   = 0x0003ffff,
1934                 .data   = "PTM 1.1",
1935         },
1936         {       /* PTM 1.1 Qualcomm */
1937                 .id     = 0x0003006f,
1938                 .mask   = 0x0003ffff,
1939                 .data   = "PTM 1.1",
1940         },
1941         { 0, 0},
1942 };
1943
1944 static struct amba_driver etm_driver = {
1945         .drv = {
1946                 .name   = "coresight-etm3x",
1947                 .owner  = THIS_MODULE,
1948                 .pm     = &etm_dev_pm_ops,
1949         },
1950         .probe          = etm_probe,
1951         .remove         = etm_remove,
1952         .id_table       = etm_ids,
1953 };
1954
1955 module_amba_driver(etm_driver);
1956
1957 MODULE_LICENSE("GPL v2");
1958 MODULE_DESCRIPTION("CoreSight Program Flow Trace driver");