drivers/hwtracing/coresight/coresight-etm4x.c

   1 /* Copyright (c) 2014, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/moduleparam.h>
  15 #include <linux/init.h>
  16 #include <linux/types.h>
  17 #include <linux/device.h>
  18 #include <linux/io.h>
  19 #include <linux/err.h>
  20 #include <linux/fs.h>
  21 #include <linux/slab.h>
  22 #include <linux/delay.h>
  23 #include <linux/smp.h>
  24 #include <linux/sysfs.h>
  25 #include <linux/stat.h>
  26 #include <linux/clk.h>
  27 #include <linux/cpu.h>
  28 #include <linux/coresight.h>
  29 #include <linux/pm_wakeup.h>
  30 #include <linux/amba/bus.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/uaccess.h>
  33 #include <linux/pm_runtime.h>
  34 #include <asm/sections.h>
  35
  36 #include "coresight-etm4x.h"
  37
  38 static int boot_enable;
  39 module_param_named(boot_enable, boot_enable, int, S_IRUGO);
  40
  41 /* The number of ETMv4 currently registered */
  42 static int etm4_count;
  43 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
  44
  45 static void etm4_os_unlock(void *info)
  46 {
  47         struct etmv4_drvdata *drvdata = (struct etmv4_drvdata *)info;
  48
  49         /* Writing any value to ETMOSLAR unlocks the trace registers */
  50         writel_relaxed(0x0, drvdata->base + TRCOSLAR);
  51         isb();
  52 }
  53
  54 static bool etm4_arch_supported(u8 arch)
  55 {
  56         switch (arch) {
  57         case ETM_ARCH_V4:
  58                 break;
  59         default:
  60                 return false;
  61         }
  62         return true;
  63 }
  64
  65 static int etm4_trace_id(struct coresight_device *csdev)
  66 {
  67         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  68         unsigned long flags;
  69         int trace_id = -1;
  70
  71         if (!drvdata->enable)
  72                 return drvdata->trcid;
  73
  74         pm_runtime_get_sync(drvdata->dev);
  75         spin_lock_irqsave(&drvdata->spinlock, flags);
  76
  77         CS_UNLOCK(drvdata->base);
  78         trace_id = readl_relaxed(drvdata->base + TRCTRACEIDR);
  79         trace_id &= ETM_TRACEID_MASK;
  80         CS_LOCK(drvdata->base);
  81
  82         spin_unlock_irqrestore(&drvdata->spinlock, flags);
  83         pm_runtime_put(drvdata->dev);
  84
  85         return trace_id;
  86 }
  87
  88 static void etm4_enable_hw(void *info)
  89 {
  90         int i;
  91         struct etmv4_drvdata *drvdata = info;
  92
  93         CS_UNLOCK(drvdata->base);
  94
  95         etm4_os_unlock(drvdata);
  96
  97         /* Disable the trace unit before programming trace registers */
  98         writel_relaxed(0, drvdata->base + TRCPRGCTLR);
  99
 100         /* wait for TRCSTATR.IDLE to go up */
 101         if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
 102                 dev_err(drvdata->dev,
 103                         "timeout observed when probing at offset %#x\n",
 104                         TRCSTATR);
 105
 106         writel_relaxed(drvdata->pe_sel, drvdata->base + TRCPROCSELR);
 107         writel_relaxed(drvdata->cfg, drvdata->base + TRCCONFIGR);
 108         /* nothing specific implemented */
 109         writel_relaxed(0x0, drvdata->base + TRCAUXCTLR);
 110         writel_relaxed(drvdata->eventctrl0, drvdata->base + TRCEVENTCTL0R);
 111         writel_relaxed(drvdata->eventctrl1, drvdata->base + TRCEVENTCTL1R);
 112         writel_relaxed(drvdata->stall_ctrl, drvdata->base + TRCSTALLCTLR);
 113         writel_relaxed(drvdata->ts_ctrl, drvdata->base + TRCTSCTLR);
 114         writel_relaxed(drvdata->syncfreq, drvdata->base + TRCSYNCPR);
 115         writel_relaxed(drvdata->ccctlr, drvdata->base + TRCCCCTLR);
 116         writel_relaxed(drvdata->bb_ctrl, drvdata->base + TRCBBCTLR);
 117         writel_relaxed(drvdata->trcid, drvdata->base + TRCTRACEIDR);
 118         writel_relaxed(drvdata->vinst_ctrl, drvdata->base + TRCVICTLR);
 119         writel_relaxed(drvdata->viiectlr, drvdata->base + TRCVIIECTLR);
 120         writel_relaxed(drvdata->vissctlr,
 121                        drvdata->base + TRCVISSCTLR);
 122         writel_relaxed(drvdata->vipcssctlr,
 123                        drvdata->base + TRCVIPCSSCTLR);
 124         for (i = 0; i < drvdata->nrseqstate - 1; i++)
 125                 writel_relaxed(drvdata->seq_ctrl[i],
 126                                drvdata->base + TRCSEQEVRn(i));
 127         writel_relaxed(drvdata->seq_rst, drvdata->base + TRCSEQRSTEVR);
 128         writel_relaxed(drvdata->seq_state, drvdata->base + TRCSEQSTR);
 129         writel_relaxed(drvdata->ext_inp, drvdata->base + TRCEXTINSELR);
 130         for (i = 0; i < drvdata->nr_cntr; i++) {
 131                 writel_relaxed(drvdata->cntrldvr[i],
 132                                drvdata->base + TRCCNTRLDVRn(i));
 133                 writel_relaxed(drvdata->cntr_ctrl[i],
 134                                drvdata->base + TRCCNTCTLRn(i));
 135                 writel_relaxed(drvdata->cntr_val[i],
 136                                drvdata->base + TRCCNTVRn(i));
 137         }
 138         for (i = 0; i < drvdata->nr_resource; i++)
 139                 writel_relaxed(drvdata->res_ctrl[i],
 140                                drvdata->base + TRCRSCTLRn(i));
 141
 142         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 143                 writel_relaxed(drvdata->ss_ctrl[i],
 144                                drvdata->base + TRCSSCCRn(i));
 145                 writel_relaxed(drvdata->ss_status[i],
 146                                drvdata->base + TRCSSCSRn(i));
 147                 writel_relaxed(drvdata->ss_pe_cmp[i],
 148                                drvdata->base + TRCSSPCICRn(i));
 149         }
 150         for (i = 0; i < drvdata->nr_addr_cmp; i++) {
 151                 writeq_relaxed(drvdata->addr_val[i],
 152                                drvdata->base + TRCACVRn(i));
 153                 writeq_relaxed(drvdata->addr_acc[i],
 154                                drvdata->base + TRCACATRn(i));
 155         }
 156         for (i = 0; i < drvdata->numcidc; i++)
 157                 writeq_relaxed(drvdata->ctxid_val[i],
 158                                drvdata->base + TRCCIDCVRn(i));
 159         writel_relaxed(drvdata->ctxid_mask0, drvdata->base + TRCCIDCCTLR0);
 160         writel_relaxed(drvdata->ctxid_mask1, drvdata->base + TRCCIDCCTLR1);
 161
 162         for (i = 0; i < drvdata->numvmidc; i++)
 163                 writeq_relaxed(drvdata->vmid_val[i],
 164                                drvdata->base + TRCVMIDCVRn(i));
 165         writel_relaxed(drvdata->vmid_mask0, drvdata->base + TRCVMIDCCTLR0);
 166         writel_relaxed(drvdata->vmid_mask1, drvdata->base + TRCVMIDCCTLR1);
 167
 168         /* Enable the trace unit */
 169         writel_relaxed(1, drvdata->base + TRCPRGCTLR);
 170
 171         /* wait for TRCSTATR.IDLE to go back down to '0' */
 172         if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
 173                 dev_err(drvdata->dev,
 174                         "timeout observed when probing at offset %#x\n",
 175                         TRCSTATR);
 176
 177         CS_LOCK(drvdata->base);
 178
 179         dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
 180 }
 181
 182 static int etm4_enable(struct coresight_device *csdev)
 183 {
 184         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 185         int ret;
 186
 187         pm_runtime_get_sync(drvdata->dev);
 188         spin_lock(&drvdata->spinlock);
 189
 190         /*
 191          * Executing etm4_enable_hw on the cpu whose ETM is being enabled
 192          * ensures that register writes occur when cpu is powered.
 193          */
 194         ret = smp_call_function_single(drvdata->cpu,
 195                                        etm4_enable_hw, drvdata, 1);
 196         if (ret)
 197                 goto err;
 198         drvdata->enable = true;
 199         drvdata->sticky_enable = true;
 200
 201         spin_unlock(&drvdata->spinlock);
 202
 203         dev_info(drvdata->dev, "ETM tracing enabled\n");
 204         return 0;
 205 err:
 206         spin_unlock(&drvdata->spinlock);
 207         pm_runtime_put(drvdata->dev);
 208         return ret;
 209 }
 210
 211 static void etm4_disable_hw(void *info)
 212 {
 213         u32 control;
 214         struct etmv4_drvdata *drvdata = info;
 215
 216         CS_UNLOCK(drvdata->base);
 217
 218         control = readl_relaxed(drvdata->base + TRCPRGCTLR);
 219
 220         /* EN, bit[0] Trace unit enable bit */
 221         control &= ~0x1;
 222
 223         /* make sure everything completes before disabling */
 224         mb();
 225         isb();
 226         writel_relaxed(control, drvdata->base + TRCPRGCTLR);
 227
 228         CS_LOCK(drvdata->base);
 229
 230         dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
 231 }
 232
 233 static void etm4_disable(struct coresight_device *csdev)
 234 {
 235         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 236
 237         /*
 238          * Taking hotplug lock here protects from clocks getting disabled
 239          * with tracing being left on (crash scenario) if user disable occurs
 240          * after cpu online mask indicates the cpu is offline but before the
 241          * DYING hotplug callback is serviced by the ETM driver.
 242          */
 243         get_online_cpus();
 244         spin_lock(&drvdata->spinlock);
 245
 246         /*
 247          * Executing etm4_disable_hw on the cpu whose ETM is being disabled
 248          * ensures that register writes occur when cpu is powered.
 249          */
 250         smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
 251         drvdata->enable = false;
 252
 253         spin_unlock(&drvdata->spinlock);
 254         put_online_cpus();
 255
 256         pm_runtime_put(drvdata->dev);
 257
 258         dev_info(drvdata->dev, "ETM tracing disabled\n");
 259 }
 260
 261 static const struct coresight_ops_source etm4_source_ops = {
 262         .trace_id       = etm4_trace_id,
 263         .enable         = etm4_enable,
 264         .disable        = etm4_disable,
 265 };
 266
 267 static const struct coresight_ops etm4_cs_ops = {
 268         .source_ops     = &etm4_source_ops,
 269 };
 270
 271 static ssize_t cpu_show(struct device *dev,
 272                         struct device_attribute *attr, char *buf)
 273 {
 274         int val;
 275         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 276
 277         val = drvdata->cpu;
 278         return scnprintf(buf, PAGE_SIZE, "%d\n", val);
 279
 280 }
 281 static DEVICE_ATTR_RO(cpu);
 282
 283 static struct attribute *coresight_etmv4_attrs[] = {
 284         &dev_attr_cpu.attr,
 285         NULL,
 286 };
 287 ATTRIBUTE_GROUPS(coresight_etmv4);
 288
 289 static void etm4_init_arch_data(void *info)
 290 {
 291         u32 etmidr0;
 292         u32 etmidr1;
 293         u32 etmidr2;
 294         u32 etmidr3;
 295         u32 etmidr4;
 296         u32 etmidr5;
 297         struct etmv4_drvdata *drvdata = info;
 298
 299         CS_UNLOCK(drvdata->base);
 300
 301         /* find all capabilities of the tracing unit */
 302         etmidr0 = readl_relaxed(drvdata->base + TRCIDR0);
 303
 304         /* INSTP0, bits[2:1] P0 tracing support field */
 305         if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
 306                 drvdata->instrp0 = true;
 307         else
 308                 drvdata->instrp0 = false;
 309
 310         /* TRCBB, bit[5] Branch broadcast tracing support bit */
 311         if (BMVAL(etmidr0, 5, 5))
 312                 drvdata->trcbb = true;
 313         else
 314                 drvdata->trcbb = false;
 315
 316         /* TRCCOND, bit[6] Conditional instruction tracing support bit */
 317         if (BMVAL(etmidr0, 6, 6))
 318                 drvdata->trccond = true;
 319         else
 320                 drvdata->trccond = false;
 321
 322         /* TRCCCI, bit[7] Cycle counting instruction bit */
 323         if (BMVAL(etmidr0, 7, 7))
 324                 drvdata->trccci = true;
 325         else
 326                 drvdata->trccci = false;
 327
 328         /* RETSTACK, bit[9] Return stack bit */
 329         if (BMVAL(etmidr0, 9, 9))
 330                 drvdata->retstack = true;
 331         else
 332                 drvdata->retstack = false;
 333
 334         /* NUMEVENT, bits[11:10] Number of events field */
 335         drvdata->nr_event = BMVAL(etmidr0, 10, 11);
 336         /* QSUPP, bits[16:15] Q element support field */
 337         drvdata->q_support = BMVAL(etmidr0, 15, 16);
 338         /* TSSIZE, bits[28:24] Global timestamp size field */
 339         drvdata->ts_size = BMVAL(etmidr0, 24, 28);
 340
 341         /* base architecture of trace unit */
 342         etmidr1 = readl_relaxed(drvdata->base + TRCIDR1);
 343         /*
 344          * TRCARCHMIN, bits[7:4] architecture the minor version number
 345          * TRCARCHMAJ, bits[11:8] architecture major versin number
 346          */
 347         drvdata->arch = BMVAL(etmidr1, 4, 11);
 348
 349         /* maximum size of resources */
 350         etmidr2 = readl_relaxed(drvdata->base + TRCIDR2);
 351         /* CIDSIZE, bits[9:5] Indicates the Context ID size */
 352         drvdata->ctxid_size = BMVAL(etmidr2, 5, 9);
 353         /* VMIDSIZE, bits[14:10] Indicates the VMID size */
 354         drvdata->vmid_size = BMVAL(etmidr2, 10, 14);
 355         /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
 356         drvdata->ccsize = BMVAL(etmidr2, 25, 28);
 357
 358         etmidr3 = readl_relaxed(drvdata->base + TRCIDR3);
 359         /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
 360         drvdata->ccitmin = BMVAL(etmidr3, 0, 11);
 361         /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
 362         drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);
 363         /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
 364         drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
 365
 366         /*
 367          * TRCERR, bit[24] whether a trace unit can trace a
 368          * system error exception.
 369          */
 370         if (BMVAL(etmidr3, 24, 24))
 371                 drvdata->trc_error = true;
 372         else
 373                 drvdata->trc_error = false;
 374
 375         /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
 376         if (BMVAL(etmidr3, 25, 25))
 377                 drvdata->syncpr = true;
 378         else
 379                 drvdata->syncpr = false;
 380
 381         /* STALLCTL, bit[26] is stall control implemented? */
 382         if (BMVAL(etmidr3, 26, 26))
 383                 drvdata->stallctl = true;
 384         else
 385                 drvdata->stallctl = false;
 386
 387         /* SYSSTALL, bit[27] implementation can support stall control? */
 388         if (BMVAL(etmidr3, 27, 27))
 389                 drvdata->sysstall = true;
 390         else
 391                 drvdata->sysstall = false;
 392
 393         /* NUMPROC, bits[30:28] the number of PEs available for tracing */
 394         drvdata->nr_pe = BMVAL(etmidr3, 28, 30);
 395
 396         /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
 397         if (BMVAL(etmidr3, 31, 31))
 398                 drvdata->nooverflow = true;
 399         else
 400                 drvdata->nooverflow = false;
 401
 402         /* number of resources trace unit supports */
 403         etmidr4 = readl_relaxed(drvdata->base + TRCIDR4);
 404         /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
 405         drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3);
 406         /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
 407         drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15);
 408         /* NUMRSPAIR, bits[19:16] the number of resource pairs for tracing */
 409         drvdata->nr_resource = BMVAL(etmidr4, 16, 19);
 410         /*
 411          * NUMSSCC, bits[23:20] the number of single-shot
 412          * comparator control for tracing
 413          */
 414         drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
 415         /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
 416         drvdata->numcidc = BMVAL(etmidr4, 24, 27);
 417         /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
 418         drvdata->numvmidc = BMVAL(etmidr4, 28, 31);
 419
 420         etmidr5 = readl_relaxed(drvdata->base + TRCIDR5);
 421         /* NUMEXTIN, bits[8:0] number of external inputs implemented */
 422         drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8);
 423         /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
 424         drvdata->trcid_size = BMVAL(etmidr5, 16, 21);
 425         /* ATBTRIG, bit[22] implementation can support ATB triggers? */
 426         if (BMVAL(etmidr5, 22, 22))
 427                 drvdata->atbtrig = true;
 428         else
 429                 drvdata->atbtrig = false;
 430         /*
 431          * LPOVERRIDE, bit[23] implementation supports
 432          * low-power state override
 433          */
 434         if (BMVAL(etmidr5, 23, 23))
 435                 drvdata->lpoverride = true;
 436         else
 437                 drvdata->lpoverride = false;
 438         /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
 439         drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
 440         /* NUMCNTR, bits[30:28] number of counters available for tracing */
 441         drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
 442         CS_LOCK(drvdata->base);
 443 }
 444
 445 static void etm4_init_default_data(struct etmv4_drvdata *drvdata)
 446 {
 447         int i;
 448
 449         drvdata->pe_sel = 0x0;
 450         drvdata->cfg = (ETMv4_MODE_CTXID | ETM_MODE_VMID |
 451                         ETMv4_MODE_TIMESTAMP | ETM_MODE_RETURNSTACK);
 452
 453         /* disable all events tracing */
 454         drvdata->eventctrl0 = 0x0;
 455         drvdata->eventctrl1 = 0x0;
 456
 457         /* disable stalling */
 458         drvdata->stall_ctrl = 0x0;
 459
 460         /* disable timestamp event */
 461         drvdata->ts_ctrl = 0x0;
 462
 463         /* enable trace synchronization every 4096 bytes for trace */
 464         if (drvdata->syncpr == false)
 465                 drvdata->syncfreq = 0xC;
 466
 467         /*
 468          *  enable viewInst to trace everything with start-stop logic in
 469          *  started state
 470          */
 471         drvdata->vinst_ctrl |= BIT(0);
 472         /* set initial state of start-stop logic */
 473         if (drvdata->nr_addr_cmp)
 474                 drvdata->vinst_ctrl |= BIT(9);
 475
 476         /* no address range filtering for ViewInst */
 477         drvdata->viiectlr = 0x0;
 478         /* no start-stop filtering for ViewInst */
 479         drvdata->vissctlr = 0x0;
 480
 481         /* disable seq events */
 482         for (i = 0; i < drvdata->nrseqstate-1; i++)
 483                 drvdata->seq_ctrl[i] = 0x0;
 484         drvdata->seq_rst = 0x0;
 485         drvdata->seq_state = 0x0;
 486
 487         /* disable external input events */
 488         drvdata->ext_inp = 0x0;
 489
 490         for (i = 0; i < drvdata->nr_cntr; i++) {
 491                 drvdata->cntrldvr[i] = 0x0;
 492                 drvdata->cntr_ctrl[i] = 0x0;
 493                 drvdata->cntr_val[i] = 0x0;
 494         }
 495
 496         for (i = 2; i < drvdata->nr_resource * 2; i++)
 497                 drvdata->res_ctrl[i] = 0x0;
 498
 499         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 500                 drvdata->ss_ctrl[i] = 0x0;
 501                 drvdata->ss_pe_cmp[i] = 0x0;
 502         }
 503
 504         if (drvdata->nr_addr_cmp >= 1) {
 505                 drvdata->addr_val[0] = (unsigned long)_stext;
 506                 drvdata->addr_val[1] = (unsigned long)_etext;
 507                 drvdata->addr_type[0] = ETM_ADDR_TYPE_RANGE;
 508                 drvdata->addr_type[1] = ETM_ADDR_TYPE_RANGE;
 509         }
 510
 511         for (i = 0; i < drvdata->numcidc; i++)
 512                 drvdata->ctxid_val[i] = 0x0;
 513         drvdata->ctxid_mask0 = 0x0;
 514         drvdata->ctxid_mask1 = 0x0;
 515
 516         for (i = 0; i < drvdata->numvmidc; i++)
 517                 drvdata->vmid_val[i] = 0x0;
 518         drvdata->vmid_mask0 = 0x0;
 519         drvdata->vmid_mask1 = 0x0;
 520
 521         /*
 522          * A trace ID value of 0 is invalid, so let's start at some
 523          * random value that fits in 7 bits.  ETMv3.x has 0x10 so let's
 524          * start at 0x20.
 525          */
 526         drvdata->trcid = 0x20 + drvdata->cpu;
 527 }
 528
 529 static int etm4_cpu_callback(struct notifier_block *nfb, unsigned long action,
 530                             void *hcpu)
 531 {
 532         unsigned int cpu = (unsigned long)hcpu;
 533
 534         if (!etmdrvdata[cpu])
 535                 goto out;
 536
 537         switch (action & (~CPU_TASKS_FROZEN)) {
 538         case CPU_STARTING:
 539                 spin_lock(&etmdrvdata[cpu]->spinlock);
 540                 if (!etmdrvdata[cpu]->os_unlock) {
 541                         etm4_os_unlock(etmdrvdata[cpu]);
 542                         etmdrvdata[cpu]->os_unlock = true;
 543                 }
 544
 545                 if (etmdrvdata[cpu]->enable)
 546                         etm4_enable_hw(etmdrvdata[cpu]);
 547                 spin_unlock(&etmdrvdata[cpu]->spinlock);
 548                 break;
 549
 550         case CPU_ONLINE:
 551                 if (etmdrvdata[cpu]->boot_enable &&
 552                         !etmdrvdata[cpu]->sticky_enable)
 553                         coresight_enable(etmdrvdata[cpu]->csdev);
 554                 break;
 555
 556         case CPU_DYING:
 557                 spin_lock(&etmdrvdata[cpu]->spinlock);
 558                 if (etmdrvdata[cpu]->enable)
 559                         etm4_disable_hw(etmdrvdata[cpu]);
 560                 spin_unlock(&etmdrvdata[cpu]->spinlock);
 561                 break;
 562         }
 563 out:
 564         return NOTIFY_OK;
 565 }
 566
 567 static struct notifier_block etm4_cpu_notifier = {
 568         .notifier_call = etm4_cpu_callback,
 569 };
 570
 571 static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
 572 {
 573         int ret;
 574         void __iomem *base;
 575         struct device *dev = &adev->dev;
 576         struct coresight_platform_data *pdata = NULL;
 577         struct etmv4_drvdata *drvdata;
 578         struct resource *res = &adev->res;
 579         struct coresight_desc *desc;
 580         struct device_node *np = adev->dev.of_node;
 581
 582         desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
 583         if (!desc)
 584                 return -ENOMEM;
 585
 586         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
 587         if (!drvdata)
 588                 return -ENOMEM;
 589
 590         if (np) {
 591                 pdata = of_get_coresight_platform_data(dev, np);
 592                 if (IS_ERR(pdata))
 593                         return PTR_ERR(pdata);
 594                 adev->dev.platform_data = pdata;
 595         }
 596
 597         drvdata->dev = &adev->dev;
 598         dev_set_drvdata(dev, drvdata);
 599
 600         /* Validity for the resource is already checked by the AMBA core */
 601         base = devm_ioremap_resource(dev, res);
 602         if (IS_ERR(base))
 603                 return PTR_ERR(base);
 604
 605         drvdata->base = base;
 606
 607         spin_lock_init(&drvdata->spinlock);
 608
 609         drvdata->cpu = pdata ? pdata->cpu : 0;
 610
 611         get_online_cpus();
 612         etmdrvdata[drvdata->cpu] = drvdata;
 613
 614         if (!smp_call_function_single(drvdata->cpu, etm4_os_unlock, drvdata, 1))
 615                 drvdata->os_unlock = true;
 616
 617         if (smp_call_function_single(drvdata->cpu,
 618                                 etm4_init_arch_data,  drvdata, 1))
 619                 dev_err(dev, "ETM arch init failed\n");
 620
 621         if (!etm4_count++)
 622                 register_hotcpu_notifier(&etm4_cpu_notifier);
 623
 624         put_online_cpus();
 625
 626         if (etm4_arch_supported(drvdata->arch) == false) {
 627                 ret = -EINVAL;
 628                 goto err_arch_supported;
 629         }
 630         etm4_init_default_data(drvdata);
 631
 632         pm_runtime_put(&adev->dev);
 633
 634         desc->type = CORESIGHT_DEV_TYPE_SOURCE;
 635         desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
 636         desc->ops = &etm4_cs_ops;
 637         desc->pdata = pdata;
 638         desc->dev = dev;
 639         desc->groups = coresight_etmv4_groups;
 640         drvdata->csdev = coresight_register(desc);
 641         if (IS_ERR(drvdata->csdev)) {
 642                 ret = PTR_ERR(drvdata->csdev);
 643                 goto err_coresight_register;
 644         }
 645
 646         dev_info(dev, "%s initialized\n", (char *)id->data);
 647
 648         if (boot_enable) {
 649                 coresight_enable(drvdata->csdev);
 650                 drvdata->boot_enable = true;
 651         }
 652
 653         return 0;
 654
 655 err_arch_supported:
 656         pm_runtime_put(&adev->dev);
 657 err_coresight_register:
 658         if (--etm4_count == 0)
 659                 unregister_hotcpu_notifier(&etm4_cpu_notifier);
 660         return ret;
 661 }
 662
 663 static int etm4_remove(struct amba_device *adev)
 664 {
 665         struct etmv4_drvdata *drvdata = amba_get_drvdata(adev);
 666
 667         coresight_unregister(drvdata->csdev);
 668         if (--etm4_count == 0)
 669                 unregister_hotcpu_notifier(&etm4_cpu_notifier);
 670
 671         return 0;
 672 }
 673
 674 static struct amba_id etm4_ids[] = {
 675         {       /* ETM 4.0 - Qualcomm */
 676                 .id     = 0x0003b95d,
 677                 .mask   = 0x0003ffff,
 678                 .data   = "ETM 4.0",
 679         },
 680         {       /* ETM 4.0 - Juno board */
 681                 .id     = 0x000bb95e,
 682                 .mask   = 0x000fffff,
 683                 .data   = "ETM 4.0",
 684         },
 685         { 0, 0},
 686 };
 687
 688 static struct amba_driver etm4x_driver = {
 689         .drv = {
 690                 .name   = "coresight-etm4x",
 691         },
 692         .probe          = etm4_probe,
 693         .remove         = etm4_remove,
 694         .id_table       = etm4_ids,
 695 };
 696
 697 module_amba_driver(etm4x_driver);