drivers/hwtracing/coresight/coresight-etm4x.c

   1 /* Copyright (c) 2014, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/moduleparam.h>
  15 #include <linux/init.h>
  16 #include <linux/types.h>
  17 #include <linux/device.h>
  18 #include <linux/io.h>
  19 #include <linux/err.h>
  20 #include <linux/fs.h>
  21 #include <linux/slab.h>
  22 #include <linux/delay.h>
  23 #include <linux/smp.h>
  24 #include <linux/sysfs.h>
  25 #include <linux/stat.h>
  26 #include <linux/clk.h>
  27 #include <linux/cpu.h>
  28 #include <linux/coresight.h>
  29 #include <linux/pm_wakeup.h>
  30 #include <linux/amba/bus.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/uaccess.h>
  33 #include <linux/pm_runtime.h>
  34 #include <asm/sections.h>
  35
  36 #include "coresight-etm4x.h"
  37
  38 static int boot_enable;
  39 module_param_named(boot_enable, boot_enable, int, S_IRUGO);
  40
  41 /* The number of ETMv4 currently registered */
  42 static int etm4_count;
  43 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
  44
  45 static void etm4_os_unlock(void *info)
  46 {
  47         struct etmv4_drvdata *drvdata = (struct etmv4_drvdata *)info;
  48
  49         /* Writing any value to ETMOSLAR unlocks the trace registers */
  50         writel_relaxed(0x0, drvdata->base + TRCOSLAR);
  51         isb();
  52 }
  53
  54 static bool etm4_arch_supported(u8 arch)
  55 {
  56         switch (arch) {
  57         case ETM_ARCH_V4:
  58                 break;
  59         default:
  60                 return false;
  61         }
  62         return true;
  63 }
  64
  65 static int etm4_trace_id(struct coresight_device *csdev)
  66 {
  67         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  68         unsigned long flags;
  69         int trace_id = -1;
  70
  71         if (!drvdata->enable)
  72                 return drvdata->trcid;
  73
  74         pm_runtime_get_sync(drvdata->dev);
  75         spin_lock_irqsave(&drvdata->spinlock, flags);
  76
  77         CS_UNLOCK(drvdata->base);
  78         trace_id = readl_relaxed(drvdata->base + TRCTRACEIDR);
  79         trace_id &= ETM_TRACEID_MASK;
  80         CS_LOCK(drvdata->base);
  81
  82         spin_unlock_irqrestore(&drvdata->spinlock, flags);
  83         pm_runtime_put(drvdata->dev);
  84
  85         return trace_id;
  86 }
  87
  88 static void etm4_enable_hw(void *info)
  89 {
  90         int i;
  91         struct etmv4_drvdata *drvdata = info;
  92
  93         CS_UNLOCK(drvdata->base);
  94
  95         etm4_os_unlock(drvdata);
  96
  97         /* Disable the trace unit before programming trace registers */
  98         writel_relaxed(0, drvdata->base + TRCPRGCTLR);
  99
 100         /* wait for TRCSTATR.IDLE to go up */
 101         if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
 102                 dev_err(drvdata->dev,
 103                         "timeout observed when probing at offset %#x\n",
 104                         TRCSTATR);
 105
 106         writel_relaxed(drvdata->pe_sel, drvdata->base + TRCPROCSELR);
 107         writel_relaxed(drvdata->cfg, drvdata->base + TRCCONFIGR);
 108         /* nothing specific implemented */
 109         writel_relaxed(0x0, drvdata->base + TRCAUXCTLR);
 110         writel_relaxed(drvdata->eventctrl0, drvdata->base + TRCEVENTCTL0R);
 111         writel_relaxed(drvdata->eventctrl1, drvdata->base + TRCEVENTCTL1R);
 112         writel_relaxed(drvdata->stall_ctrl, drvdata->base + TRCSTALLCTLR);
 113         writel_relaxed(drvdata->ts_ctrl, drvdata->base + TRCTSCTLR);
 114         writel_relaxed(drvdata->syncfreq, drvdata->base + TRCSYNCPR);
 115         writel_relaxed(drvdata->ccctlr, drvdata->base + TRCCCCTLR);
 116         writel_relaxed(drvdata->bb_ctrl, drvdata->base + TRCBBCTLR);
 117         writel_relaxed(drvdata->trcid, drvdata->base + TRCTRACEIDR);
 118         writel_relaxed(drvdata->vinst_ctrl, drvdata->base + TRCVICTLR);
 119         writel_relaxed(drvdata->viiectlr, drvdata->base + TRCVIIECTLR);
 120         writel_relaxed(drvdata->vissctlr,
 121                        drvdata->base + TRCVISSCTLR);
 122         writel_relaxed(drvdata->vipcssctlr,
 123                        drvdata->base + TRCVIPCSSCTLR);
 124         for (i = 0; i < drvdata->nrseqstate - 1; i++)
 125                 writel_relaxed(drvdata->seq_ctrl[i],
 126                                drvdata->base + TRCSEQEVRn(i));
 127         writel_relaxed(drvdata->seq_rst, drvdata->base + TRCSEQRSTEVR);
 128         writel_relaxed(drvdata->seq_state, drvdata->base + TRCSEQSTR);
 129         writel_relaxed(drvdata->ext_inp, drvdata->base + TRCEXTINSELR);
 130         for (i = 0; i < drvdata->nr_cntr; i++) {
 131                 writel_relaxed(drvdata->cntrldvr[i],
 132                                drvdata->base + TRCCNTRLDVRn(i));
 133                 writel_relaxed(drvdata->cntr_ctrl[i],
 134                                drvdata->base + TRCCNTCTLRn(i));
 135                 writel_relaxed(drvdata->cntr_val[i],
 136                                drvdata->base + TRCCNTVRn(i));
 137         }
 138         for (i = 0; i < drvdata->nr_resource; i++)
 139                 writel_relaxed(drvdata->res_ctrl[i],
 140                                drvdata->base + TRCRSCTLRn(i));
 141
 142         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 143                 writel_relaxed(drvdata->ss_ctrl[i],
 144                                drvdata->base + TRCSSCCRn(i));
 145                 writel_relaxed(drvdata->ss_status[i],
 146                                drvdata->base + TRCSSCSRn(i));
 147                 writel_relaxed(drvdata->ss_pe_cmp[i],
 148                                drvdata->base + TRCSSPCICRn(i));
 149         }
 150         for (i = 0; i < drvdata->nr_addr_cmp; i++) {
 151                 writeq_relaxed(drvdata->addr_val[i],
 152                                drvdata->base + TRCACVRn(i));
 153                 writeq_relaxed(drvdata->addr_acc[i],
 154                                drvdata->base + TRCACATRn(i));
 155         }
 156         for (i = 0; i < drvdata->numcidc; i++)
 157                 writeq_relaxed(drvdata->ctxid_val[i],
 158                                drvdata->base + TRCCIDCVRn(i));
 159         writel_relaxed(drvdata->ctxid_mask0, drvdata->base + TRCCIDCCTLR0);
 160         writel_relaxed(drvdata->ctxid_mask1, drvdata->base + TRCCIDCCTLR1);
 161
 162         for (i = 0; i < drvdata->numvmidc; i++)
 163                 writeq_relaxed(drvdata->vmid_val[i],
 164                                drvdata->base + TRCVMIDCVRn(i));
 165         writel_relaxed(drvdata->vmid_mask0, drvdata->base + TRCVMIDCCTLR0);
 166         writel_relaxed(drvdata->vmid_mask1, drvdata->base + TRCVMIDCCTLR1);
 167
 168         /* Enable the trace unit */
 169         writel_relaxed(1, drvdata->base + TRCPRGCTLR);
 170
 171         /* wait for TRCSTATR.IDLE to go back down to '0' */
 172         if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
 173                 dev_err(drvdata->dev,
 174                         "timeout observed when probing at offset %#x\n",
 175                         TRCSTATR);
 176
 177         CS_LOCK(drvdata->base);
 178
 179         dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
 180 }
 181
 182 static int etm4_enable(struct coresight_device *csdev)
 183 {
 184         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 185         int ret;
 186
 187         pm_runtime_get_sync(drvdata->dev);
 188         spin_lock(&drvdata->spinlock);
 189
 190         /*
 191          * Executing etm4_enable_hw on the cpu whose ETM is being enabled
 192          * ensures that register writes occur when cpu is powered.
 193          */
 194         ret = smp_call_function_single(drvdata->cpu,
 195                                        etm4_enable_hw, drvdata, 1);
 196         if (ret)
 197                 goto err;
 198         drvdata->enable = true;
 199         drvdata->sticky_enable = true;
 200
 201         spin_unlock(&drvdata->spinlock);
 202
 203         dev_info(drvdata->dev, "ETM tracing enabled\n");
 204         return 0;
 205 err:
 206         spin_unlock(&drvdata->spinlock);
 207         pm_runtime_put(drvdata->dev);
 208         return ret;
 209 }
 210
 211 static void etm4_disable_hw(void *info)
 212 {
 213         u32 control;
 214         struct etmv4_drvdata *drvdata = info;
 215
 216         CS_UNLOCK(drvdata->base);
 217
 218         control = readl_relaxed(drvdata->base + TRCPRGCTLR);
 219
 220         /* EN, bit[0] Trace unit enable bit */
 221         control &= ~0x1;
 222
 223         /* make sure everything completes before disabling */
 224         mb();
 225         isb();
 226         writel_relaxed(control, drvdata->base + TRCPRGCTLR);
 227
 228         CS_LOCK(drvdata->base);
 229
 230         dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
 231 }
 232
 233 static void etm4_disable(struct coresight_device *csdev)
 234 {
 235         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 236
 237         /*
 238          * Taking hotplug lock here protects from clocks getting disabled
 239          * with tracing being left on (crash scenario) if user disable occurs
 240          * after cpu online mask indicates the cpu is offline but before the
 241          * DYING hotplug callback is serviced by the ETM driver.
 242          */
 243         get_online_cpus();
 244         spin_lock(&drvdata->spinlock);
 245
 246         /*
 247          * Executing etm4_disable_hw on the cpu whose ETM is being disabled
 248          * ensures that register writes occur when cpu is powered.
 249          */
 250         smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
 251         drvdata->enable = false;
 252
 253         spin_unlock(&drvdata->spinlock);
 254         put_online_cpus();
 255
 256         pm_runtime_put(drvdata->dev);
 257
 258         dev_info(drvdata->dev, "ETM tracing disabled\n");
 259 }
 260
 261 static const struct coresight_ops_source etm4_source_ops = {
 262         .trace_id       = etm4_trace_id,
 263         .enable         = etm4_enable,
 264         .disable        = etm4_disable,
 265 };
 266
 267 static const struct coresight_ops etm4_cs_ops = {
 268         .source_ops     = &etm4_source_ops,
 269 };
 270
 271 static ssize_t nr_pe_cmp_show(struct device *dev,
 272                               struct device_attribute *attr,
 273                               char *buf)
 274 {
 275         unsigned long val;
 276         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 277
 278         val = drvdata->nr_pe_cmp;
 279         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 280 }
 281 static DEVICE_ATTR_RO(nr_pe_cmp);
 282
 283 static ssize_t nr_addr_cmp_show(struct device *dev,
 284                                 struct device_attribute *attr,
 285                                 char *buf)
 286 {
 287         unsigned long val;
 288         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 289
 290         val = drvdata->nr_addr_cmp;
 291         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 292 }
 293 static DEVICE_ATTR_RO(nr_addr_cmp);
 294
 295 static ssize_t nr_cntr_show(struct device *dev,
 296                             struct device_attribute *attr,
 297                             char *buf)
 298 {
 299         unsigned long val;
 300         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 301
 302         val = drvdata->nr_cntr;
 303         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 304 }
 305 static DEVICE_ATTR_RO(nr_cntr);
 306
 307 static ssize_t nr_ext_inp_show(struct device *dev,
 308                                struct device_attribute *attr,
 309                                char *buf)
 310 {
 311         unsigned long val;
 312         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 313
 314         val = drvdata->nr_ext_inp;
 315         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 316 }
 317 static DEVICE_ATTR_RO(nr_ext_inp);
 318
 319 static ssize_t numcidc_show(struct device *dev,
 320                             struct device_attribute *attr,
 321                             char *buf)
 322 {
 323         unsigned long val;
 324         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 325
 326         val = drvdata->numcidc;
 327         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 328 }
 329 static DEVICE_ATTR_RO(numcidc);
 330
 331 static ssize_t numvmidc_show(struct device *dev,
 332                              struct device_attribute *attr,
 333                              char *buf)
 334 {
 335         unsigned long val;
 336         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 337
 338         val = drvdata->numvmidc;
 339         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 340 }
 341 static DEVICE_ATTR_RO(numvmidc);
 342
 343 static ssize_t nrseqstate_show(struct device *dev,
 344                                struct device_attribute *attr,
 345                                char *buf)
 346 {
 347         unsigned long val;
 348         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 349
 350         val = drvdata->nrseqstate;
 351         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 352 }
 353 static DEVICE_ATTR_RO(nrseqstate);
 354
 355 static ssize_t nr_resource_show(struct device *dev,
 356                                 struct device_attribute *attr,
 357                                 char *buf)
 358 {
 359         unsigned long val;
 360         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 361
 362         val = drvdata->nr_resource;
 363         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 364 }
 365 static DEVICE_ATTR_RO(nr_resource);
 366
 367 static ssize_t nr_ss_cmp_show(struct device *dev,
 368                               struct device_attribute *attr,
 369                               char *buf)
 370 {
 371         unsigned long val;
 372         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 373
 374         val = drvdata->nr_ss_cmp;
 375         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 376 }
 377 static DEVICE_ATTR_RO(nr_ss_cmp);
 378
 379 static ssize_t cpu_show(struct device *dev,
 380                         struct device_attribute *attr, char *buf)
 381 {
 382         int val;
 383         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 384
 385         val = drvdata->cpu;
 386         return scnprintf(buf, PAGE_SIZE, "%d\n", val);
 387
 388 }
 389 static DEVICE_ATTR_RO(cpu);
 390
 391 static struct attribute *coresight_etmv4_attrs[] = {
 392         &dev_attr_nr_pe_cmp.attr,
 393         &dev_attr_nr_addr_cmp.attr,
 394         &dev_attr_nr_cntr.attr,
 395         &dev_attr_nr_ext_inp.attr,
 396         &dev_attr_numcidc.attr,
 397         &dev_attr_numvmidc.attr,
 398         &dev_attr_nrseqstate.attr,
 399         &dev_attr_nr_resource.attr,
 400         &dev_attr_nr_ss_cmp.attr,
 401         &dev_attr_cpu.attr,
 402         NULL,
 403 };
 404 ATTRIBUTE_GROUPS(coresight_etmv4);
 405
 406 static void etm4_init_arch_data(void *info)
 407 {
 408         u32 etmidr0;
 409         u32 etmidr1;
 410         u32 etmidr2;
 411         u32 etmidr3;
 412         u32 etmidr4;
 413         u32 etmidr5;
 414         struct etmv4_drvdata *drvdata = info;
 415
 416         CS_UNLOCK(drvdata->base);
 417
 418         /* find all capabilities of the tracing unit */
 419         etmidr0 = readl_relaxed(drvdata->base + TRCIDR0);
 420
 421         /* INSTP0, bits[2:1] P0 tracing support field */
 422         if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
 423                 drvdata->instrp0 = true;
 424         else
 425                 drvdata->instrp0 = false;
 426
 427         /* TRCBB, bit[5] Branch broadcast tracing support bit */
 428         if (BMVAL(etmidr0, 5, 5))
 429                 drvdata->trcbb = true;
 430         else
 431                 drvdata->trcbb = false;
 432
 433         /* TRCCOND, bit[6] Conditional instruction tracing support bit */
 434         if (BMVAL(etmidr0, 6, 6))
 435                 drvdata->trccond = true;
 436         else
 437                 drvdata->trccond = false;
 438
 439         /* TRCCCI, bit[7] Cycle counting instruction bit */
 440         if (BMVAL(etmidr0, 7, 7))
 441                 drvdata->trccci = true;
 442         else
 443                 drvdata->trccci = false;
 444
 445         /* RETSTACK, bit[9] Return stack bit */
 446         if (BMVAL(etmidr0, 9, 9))
 447                 drvdata->retstack = true;
 448         else
 449                 drvdata->retstack = false;
 450
 451         /* NUMEVENT, bits[11:10] Number of events field */
 452         drvdata->nr_event = BMVAL(etmidr0, 10, 11);
 453         /* QSUPP, bits[16:15] Q element support field */
 454         drvdata->q_support = BMVAL(etmidr0, 15, 16);
 455         /* TSSIZE, bits[28:24] Global timestamp size field */
 456         drvdata->ts_size = BMVAL(etmidr0, 24, 28);
 457
 458         /* base architecture of trace unit */
 459         etmidr1 = readl_relaxed(drvdata->base + TRCIDR1);
 460         /*
 461          * TRCARCHMIN, bits[7:4] architecture the minor version number
 462          * TRCARCHMAJ, bits[11:8] architecture major versin number
 463          */
 464         drvdata->arch = BMVAL(etmidr1, 4, 11);
 465
 466         /* maximum size of resources */
 467         etmidr2 = readl_relaxed(drvdata->base + TRCIDR2);
 468         /* CIDSIZE, bits[9:5] Indicates the Context ID size */
 469         drvdata->ctxid_size = BMVAL(etmidr2, 5, 9);
 470         /* VMIDSIZE, bits[14:10] Indicates the VMID size */
 471         drvdata->vmid_size = BMVAL(etmidr2, 10, 14);
 472         /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
 473         drvdata->ccsize = BMVAL(etmidr2, 25, 28);
 474
 475         etmidr3 = readl_relaxed(drvdata->base + TRCIDR3);
 476         /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
 477         drvdata->ccitmin = BMVAL(etmidr3, 0, 11);
 478         /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
 479         drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);
 480         /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
 481         drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
 482
 483         /*
 484          * TRCERR, bit[24] whether a trace unit can trace a
 485          * system error exception.
 486          */
 487         if (BMVAL(etmidr3, 24, 24))
 488                 drvdata->trc_error = true;
 489         else
 490                 drvdata->trc_error = false;
 491
 492         /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
 493         if (BMVAL(etmidr3, 25, 25))
 494                 drvdata->syncpr = true;
 495         else
 496                 drvdata->syncpr = false;
 497
 498         /* STALLCTL, bit[26] is stall control implemented? */
 499         if (BMVAL(etmidr3, 26, 26))
 500                 drvdata->stallctl = true;
 501         else
 502                 drvdata->stallctl = false;
 503
 504         /* SYSSTALL, bit[27] implementation can support stall control? */
 505         if (BMVAL(etmidr3, 27, 27))
 506                 drvdata->sysstall = true;
 507         else
 508                 drvdata->sysstall = false;
 509
 510         /* NUMPROC, bits[30:28] the number of PEs available for tracing */
 511         drvdata->nr_pe = BMVAL(etmidr3, 28, 30);
 512
 513         /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
 514         if (BMVAL(etmidr3, 31, 31))
 515                 drvdata->nooverflow = true;
 516         else
 517                 drvdata->nooverflow = false;
 518
 519         /* number of resources trace unit supports */
 520         etmidr4 = readl_relaxed(drvdata->base + TRCIDR4);
 521         /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
 522         drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3);
 523         /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
 524         drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15);
 525         /* NUMRSPAIR, bits[19:16] the number of resource pairs for tracing */
 526         drvdata->nr_resource = BMVAL(etmidr4, 16, 19);
 527         /*
 528          * NUMSSCC, bits[23:20] the number of single-shot
 529          * comparator control for tracing
 530          */
 531         drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
 532         /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
 533         drvdata->numcidc = BMVAL(etmidr4, 24, 27);
 534         /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
 535         drvdata->numvmidc = BMVAL(etmidr4, 28, 31);
 536
 537         etmidr5 = readl_relaxed(drvdata->base + TRCIDR5);
 538         /* NUMEXTIN, bits[8:0] number of external inputs implemented */
 539         drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8);
 540         /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
 541         drvdata->trcid_size = BMVAL(etmidr5, 16, 21);
 542         /* ATBTRIG, bit[22] implementation can support ATB triggers? */
 543         if (BMVAL(etmidr5, 22, 22))
 544                 drvdata->atbtrig = true;
 545         else
 546                 drvdata->atbtrig = false;
 547         /*
 548          * LPOVERRIDE, bit[23] implementation supports
 549          * low-power state override
 550          */
 551         if (BMVAL(etmidr5, 23, 23))
 552                 drvdata->lpoverride = true;
 553         else
 554                 drvdata->lpoverride = false;
 555         /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
 556         drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
 557         /* NUMCNTR, bits[30:28] number of counters available for tracing */
 558         drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
 559         CS_LOCK(drvdata->base);
 560 }
 561
 562 static void etm4_init_default_data(struct etmv4_drvdata *drvdata)
 563 {
 564         int i;
 565
 566         drvdata->pe_sel = 0x0;
 567         drvdata->cfg = (ETMv4_MODE_CTXID | ETM_MODE_VMID |
 568                         ETMv4_MODE_TIMESTAMP | ETM_MODE_RETURNSTACK);
 569
 570         /* disable all events tracing */
 571         drvdata->eventctrl0 = 0x0;
 572         drvdata->eventctrl1 = 0x0;
 573
 574         /* disable stalling */
 575         drvdata->stall_ctrl = 0x0;
 576
 577         /* disable timestamp event */
 578         drvdata->ts_ctrl = 0x0;
 579
 580         /* enable trace synchronization every 4096 bytes for trace */
 581         if (drvdata->syncpr == false)
 582                 drvdata->syncfreq = 0xC;
 583
 584         /*
 585          *  enable viewInst to trace everything with start-stop logic in
 586          *  started state
 587          */
 588         drvdata->vinst_ctrl |= BIT(0);
 589         /* set initial state of start-stop logic */
 590         if (drvdata->nr_addr_cmp)
 591                 drvdata->vinst_ctrl |= BIT(9);
 592
 593         /* no address range filtering for ViewInst */
 594         drvdata->viiectlr = 0x0;
 595         /* no start-stop filtering for ViewInst */
 596         drvdata->vissctlr = 0x0;
 597
 598         /* disable seq events */
 599         for (i = 0; i < drvdata->nrseqstate-1; i++)
 600                 drvdata->seq_ctrl[i] = 0x0;
 601         drvdata->seq_rst = 0x0;
 602         drvdata->seq_state = 0x0;
 603
 604         /* disable external input events */
 605         drvdata->ext_inp = 0x0;
 606
 607         for (i = 0; i < drvdata->nr_cntr; i++) {
 608                 drvdata->cntrldvr[i] = 0x0;
 609                 drvdata->cntr_ctrl[i] = 0x0;
 610                 drvdata->cntr_val[i] = 0x0;
 611         }
 612
 613         for (i = 2; i < drvdata->nr_resource * 2; i++)
 614                 drvdata->res_ctrl[i] = 0x0;
 615
 616         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 617                 drvdata->ss_ctrl[i] = 0x0;
 618                 drvdata->ss_pe_cmp[i] = 0x0;
 619         }
 620
 621         if (drvdata->nr_addr_cmp >= 1) {
 622                 drvdata->addr_val[0] = (unsigned long)_stext;
 623                 drvdata->addr_val[1] = (unsigned long)_etext;
 624                 drvdata->addr_type[0] = ETM_ADDR_TYPE_RANGE;
 625                 drvdata->addr_type[1] = ETM_ADDR_TYPE_RANGE;
 626         }
 627
 628         for (i = 0; i < drvdata->numcidc; i++)
 629                 drvdata->ctxid_val[i] = 0x0;
 630         drvdata->ctxid_mask0 = 0x0;
 631         drvdata->ctxid_mask1 = 0x0;
 632
 633         for (i = 0; i < drvdata->numvmidc; i++)
 634                 drvdata->vmid_val[i] = 0x0;
 635         drvdata->vmid_mask0 = 0x0;
 636         drvdata->vmid_mask1 = 0x0;
 637
 638         /*
 639          * A trace ID value of 0 is invalid, so let's start at some
 640          * random value that fits in 7 bits.  ETMv3.x has 0x10 so let's
 641          * start at 0x20.
 642          */
 643         drvdata->trcid = 0x20 + drvdata->cpu;
 644 }
 645
 646 static int etm4_cpu_callback(struct notifier_block *nfb, unsigned long action,
 647                             void *hcpu)
 648 {
 649         unsigned int cpu = (unsigned long)hcpu;
 650
 651         if (!etmdrvdata[cpu])
 652                 goto out;
 653
 654         switch (action & (~CPU_TASKS_FROZEN)) {
 655         case CPU_STARTING:
 656                 spin_lock(&etmdrvdata[cpu]->spinlock);
 657                 if (!etmdrvdata[cpu]->os_unlock) {
 658                         etm4_os_unlock(etmdrvdata[cpu]);
 659                         etmdrvdata[cpu]->os_unlock = true;
 660                 }
 661
 662                 if (etmdrvdata[cpu]->enable)
 663                         etm4_enable_hw(etmdrvdata[cpu]);
 664                 spin_unlock(&etmdrvdata[cpu]->spinlock);
 665                 break;
 666
 667         case CPU_ONLINE:
 668                 if (etmdrvdata[cpu]->boot_enable &&
 669                         !etmdrvdata[cpu]->sticky_enable)
 670                         coresight_enable(etmdrvdata[cpu]->csdev);
 671                 break;
 672
 673         case CPU_DYING:
 674                 spin_lock(&etmdrvdata[cpu]->spinlock);
 675                 if (etmdrvdata[cpu]->enable)
 676                         etm4_disable_hw(etmdrvdata[cpu]);
 677                 spin_unlock(&etmdrvdata[cpu]->spinlock);
 678                 break;
 679         }
 680 out:
 681         return NOTIFY_OK;
 682 }
 683
 684 static struct notifier_block etm4_cpu_notifier = {
 685         .notifier_call = etm4_cpu_callback,
 686 };
 687
 688 static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
 689 {
 690         int ret;
 691         void __iomem *base;
 692         struct device *dev = &adev->dev;
 693         struct coresight_platform_data *pdata = NULL;
 694         struct etmv4_drvdata *drvdata;
 695         struct resource *res = &adev->res;
 696         struct coresight_desc *desc;
 697         struct device_node *np = adev->dev.of_node;
 698
 699         desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
 700         if (!desc)
 701                 return -ENOMEM;
 702
 703         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
 704         if (!drvdata)
 705                 return -ENOMEM;
 706
 707         if (np) {
 708                 pdata = of_get_coresight_platform_data(dev, np);
 709                 if (IS_ERR(pdata))
 710                         return PTR_ERR(pdata);
 711                 adev->dev.platform_data = pdata;
 712         }
 713
 714         drvdata->dev = &adev->dev;
 715         dev_set_drvdata(dev, drvdata);
 716
 717         /* Validity for the resource is already checked by the AMBA core */
 718         base = devm_ioremap_resource(dev, res);
 719         if (IS_ERR(base))
 720                 return PTR_ERR(base);
 721
 722         drvdata->base = base;
 723
 724         spin_lock_init(&drvdata->spinlock);
 725
 726         drvdata->cpu = pdata ? pdata->cpu : 0;
 727
 728         get_online_cpus();
 729         etmdrvdata[drvdata->cpu] = drvdata;
 730
 731         if (!smp_call_function_single(drvdata->cpu, etm4_os_unlock, drvdata, 1))
 732                 drvdata->os_unlock = true;
 733
 734         if (smp_call_function_single(drvdata->cpu,
 735                                 etm4_init_arch_data,  drvdata, 1))
 736                 dev_err(dev, "ETM arch init failed\n");
 737
 738         if (!etm4_count++)
 739                 register_hotcpu_notifier(&etm4_cpu_notifier);
 740
 741         put_online_cpus();
 742
 743         if (etm4_arch_supported(drvdata->arch) == false) {
 744                 ret = -EINVAL;
 745                 goto err_arch_supported;
 746         }
 747         etm4_init_default_data(drvdata);
 748
 749         pm_runtime_put(&adev->dev);
 750
 751         desc->type = CORESIGHT_DEV_TYPE_SOURCE;
 752         desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
 753         desc->ops = &etm4_cs_ops;
 754         desc->pdata = pdata;
 755         desc->dev = dev;
 756         desc->groups = coresight_etmv4_groups;
 757         drvdata->csdev = coresight_register(desc);
 758         if (IS_ERR(drvdata->csdev)) {
 759                 ret = PTR_ERR(drvdata->csdev);
 760                 goto err_coresight_register;
 761         }
 762
 763         dev_info(dev, "%s initialized\n", (char *)id->data);
 764
 765         if (boot_enable) {
 766                 coresight_enable(drvdata->csdev);
 767                 drvdata->boot_enable = true;
 768         }
 769
 770         return 0;
 771
 772 err_arch_supported:
 773         pm_runtime_put(&adev->dev);
 774 err_coresight_register:
 775         if (--etm4_count == 0)
 776                 unregister_hotcpu_notifier(&etm4_cpu_notifier);
 777         return ret;
 778 }
 779
 780 static int etm4_remove(struct amba_device *adev)
 781 {
 782         struct etmv4_drvdata *drvdata = amba_get_drvdata(adev);
 783
 784         coresight_unregister(drvdata->csdev);
 785         if (--etm4_count == 0)
 786                 unregister_hotcpu_notifier(&etm4_cpu_notifier);
 787
 788         return 0;
 789 }
 790
 791 static struct amba_id etm4_ids[] = {
 792         {       /* ETM 4.0 - Qualcomm */
 793                 .id     = 0x0003b95d,
 794                 .mask   = 0x0003ffff,
 795                 .data   = "ETM 4.0",
 796         },
 797         {       /* ETM 4.0 - Juno board */
 798                 .id     = 0x000bb95e,
 799                 .mask   = 0x000fffff,
 800                 .data   = "ETM 4.0",
 801         },
 802         { 0, 0},
 803 };
 804
 805 static struct amba_driver etm4x_driver = {
 806         .drv = {
 807                 .name   = "coresight-etm4x",
 808         },
 809         .probe          = etm4_probe,
 810         .remove         = etm4_remove,
 811         .id_table       = etm4_ids,
 812 };
 813
 814 module_amba_driver(etm4x_driver);