drivers/hwtracing/coresight/coresight-etm4x.c

   1 /* Copyright (c) 2014, The Linux Foundation. All rights reserved.
   2  *
   3  * This program is free software; you can redistribute it and/or modify
   4  * it under the terms of the GNU General Public License version 2 and
   5  * only version 2 as published by the Free Software Foundation.
   6  *
   7  * This program is distributed in the hope that it will be useful,
   8  * but WITHOUT ANY WARRANTY; without even the implied warranty of
   9  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  10  * GNU General Public License for more details.
  11  */
  12
  13 #include <linux/kernel.h>
  14 #include <linux/moduleparam.h>
  15 #include <linux/init.h>
  16 #include <linux/types.h>
  17 #include <linux/device.h>
  18 #include <linux/io.h>
  19 #include <linux/err.h>
  20 #include <linux/fs.h>
  21 #include <linux/slab.h>
  22 #include <linux/delay.h>
  23 #include <linux/smp.h>
  24 #include <linux/sysfs.h>
  25 #include <linux/stat.h>
  26 #include <linux/clk.h>
  27 #include <linux/cpu.h>
  28 #include <linux/coresight.h>
  29 #include <linux/pm_wakeup.h>
  30 #include <linux/amba/bus.h>
  31 #include <linux/seq_file.h>
  32 #include <linux/uaccess.h>
  33 #include <linux/pm_runtime.h>
  34 #include <asm/sections.h>
  35
  36 #include "coresight-etm4x.h"
  37
  38 static int boot_enable;
  39 module_param_named(boot_enable, boot_enable, int, S_IRUGO);
  40
  41 /* The number of ETMv4 currently registered */
  42 static int etm4_count;
  43 static struct etmv4_drvdata *etmdrvdata[NR_CPUS];
  44
  45 static void etm4_os_unlock(void *info)
  46 {
  47         struct etmv4_drvdata *drvdata = (struct etmv4_drvdata *)info;
  48
  49         /* Writing any value to ETMOSLAR unlocks the trace registers */
  50         writel_relaxed(0x0, drvdata->base + TRCOSLAR);
  51         isb();
  52 }
  53
  54 static bool etm4_arch_supported(u8 arch)
  55 {
  56         switch (arch) {
  57         case ETM_ARCH_V4:
  58                 break;
  59         default:
  60                 return false;
  61         }
  62         return true;
  63 }
  64
  65 static int etm4_trace_id(struct coresight_device *csdev)
  66 {
  67         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
  68         unsigned long flags;
  69         int trace_id = -1;
  70
  71         if (!drvdata->enable)
  72                 return drvdata->trcid;
  73
  74         pm_runtime_get_sync(drvdata->dev);
  75         spin_lock_irqsave(&drvdata->spinlock, flags);
  76
  77         CS_UNLOCK(drvdata->base);
  78         trace_id = readl_relaxed(drvdata->base + TRCTRACEIDR);
  79         trace_id &= ETM_TRACEID_MASK;
  80         CS_LOCK(drvdata->base);
  81
  82         spin_unlock_irqrestore(&drvdata->spinlock, flags);
  83         pm_runtime_put(drvdata->dev);
  84
  85         return trace_id;
  86 }
  87
  88 static void etm4_enable_hw(void *info)
  89 {
  90         int i;
  91         struct etmv4_drvdata *drvdata = info;
  92
  93         CS_UNLOCK(drvdata->base);
  94
  95         etm4_os_unlock(drvdata);
  96
  97         /* Disable the trace unit before programming trace registers */
  98         writel_relaxed(0, drvdata->base + TRCPRGCTLR);
  99
 100         /* wait for TRCSTATR.IDLE to go up */
 101         if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
 102                 dev_err(drvdata->dev,
 103                         "timeout observed when probing at offset %#x\n",
 104                         TRCSTATR);
 105
 106         writel_relaxed(drvdata->pe_sel, drvdata->base + TRCPROCSELR);
 107         writel_relaxed(drvdata->cfg, drvdata->base + TRCCONFIGR);
 108         /* nothing specific implemented */
 109         writel_relaxed(0x0, drvdata->base + TRCAUXCTLR);
 110         writel_relaxed(drvdata->eventctrl0, drvdata->base + TRCEVENTCTL0R);
 111         writel_relaxed(drvdata->eventctrl1, drvdata->base + TRCEVENTCTL1R);
 112         writel_relaxed(drvdata->stall_ctrl, drvdata->base + TRCSTALLCTLR);
 113         writel_relaxed(drvdata->ts_ctrl, drvdata->base + TRCTSCTLR);
 114         writel_relaxed(drvdata->syncfreq, drvdata->base + TRCSYNCPR);
 115         writel_relaxed(drvdata->ccctlr, drvdata->base + TRCCCCTLR);
 116         writel_relaxed(drvdata->bb_ctrl, drvdata->base + TRCBBCTLR);
 117         writel_relaxed(drvdata->trcid, drvdata->base + TRCTRACEIDR);
 118         writel_relaxed(drvdata->vinst_ctrl, drvdata->base + TRCVICTLR);
 119         writel_relaxed(drvdata->viiectlr, drvdata->base + TRCVIIECTLR);
 120         writel_relaxed(drvdata->vissctlr,
 121                        drvdata->base + TRCVISSCTLR);
 122         writel_relaxed(drvdata->vipcssctlr,
 123                        drvdata->base + TRCVIPCSSCTLR);
 124         for (i = 0; i < drvdata->nrseqstate - 1; i++)
 125                 writel_relaxed(drvdata->seq_ctrl[i],
 126                                drvdata->base + TRCSEQEVRn(i));
 127         writel_relaxed(drvdata->seq_rst, drvdata->base + TRCSEQRSTEVR);
 128         writel_relaxed(drvdata->seq_state, drvdata->base + TRCSEQSTR);
 129         writel_relaxed(drvdata->ext_inp, drvdata->base + TRCEXTINSELR);
 130         for (i = 0; i < drvdata->nr_cntr; i++) {
 131                 writel_relaxed(drvdata->cntrldvr[i],
 132                                drvdata->base + TRCCNTRLDVRn(i));
 133                 writel_relaxed(drvdata->cntr_ctrl[i],
 134                                drvdata->base + TRCCNTCTLRn(i));
 135                 writel_relaxed(drvdata->cntr_val[i],
 136                                drvdata->base + TRCCNTVRn(i));
 137         }
 138         for (i = 0; i < drvdata->nr_resource; i++)
 139                 writel_relaxed(drvdata->res_ctrl[i],
 140                                drvdata->base + TRCRSCTLRn(i));
 141
 142         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 143                 writel_relaxed(drvdata->ss_ctrl[i],
 144                                drvdata->base + TRCSSCCRn(i));
 145                 writel_relaxed(drvdata->ss_status[i],
 146                                drvdata->base + TRCSSCSRn(i));
 147                 writel_relaxed(drvdata->ss_pe_cmp[i],
 148                                drvdata->base + TRCSSPCICRn(i));
 149         }
 150         for (i = 0; i < drvdata->nr_addr_cmp; i++) {
 151                 writeq_relaxed(drvdata->addr_val[i],
 152                                drvdata->base + TRCACVRn(i));
 153                 writeq_relaxed(drvdata->addr_acc[i],
 154                                drvdata->base + TRCACATRn(i));
 155         }
 156         for (i = 0; i < drvdata->numcidc; i++)
 157                 writeq_relaxed(drvdata->ctxid_val[i],
 158                                drvdata->base + TRCCIDCVRn(i));
 159         writel_relaxed(drvdata->ctxid_mask0, drvdata->base + TRCCIDCCTLR0);
 160         writel_relaxed(drvdata->ctxid_mask1, drvdata->base + TRCCIDCCTLR1);
 161
 162         for (i = 0; i < drvdata->numvmidc; i++)
 163                 writeq_relaxed(drvdata->vmid_val[i],
 164                                drvdata->base + TRCVMIDCVRn(i));
 165         writel_relaxed(drvdata->vmid_mask0, drvdata->base + TRCVMIDCCTLR0);
 166         writel_relaxed(drvdata->vmid_mask1, drvdata->base + TRCVMIDCCTLR1);
 167
 168         /* Enable the trace unit */
 169         writel_relaxed(1, drvdata->base + TRCPRGCTLR);
 170
 171         /* wait for TRCSTATR.IDLE to go back down to '0' */
 172         if (coresight_timeout(drvdata->base, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
 173                 dev_err(drvdata->dev,
 174                         "timeout observed when probing at offset %#x\n",
 175                         TRCSTATR);
 176
 177         CS_LOCK(drvdata->base);
 178
 179         dev_dbg(drvdata->dev, "cpu: %d enable smp call done\n", drvdata->cpu);
 180 }
 181
 182 static int etm4_enable(struct coresight_device *csdev)
 183 {
 184         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 185         int ret;
 186
 187         pm_runtime_get_sync(drvdata->dev);
 188         spin_lock(&drvdata->spinlock);
 189
 190         /*
 191          * Executing etm4_enable_hw on the cpu whose ETM is being enabled
 192          * ensures that register writes occur when cpu is powered.
 193          */
 194         ret = smp_call_function_single(drvdata->cpu,
 195                                        etm4_enable_hw, drvdata, 1);
 196         if (ret)
 197                 goto err;
 198         drvdata->enable = true;
 199         drvdata->sticky_enable = true;
 200
 201         spin_unlock(&drvdata->spinlock);
 202
 203         dev_info(drvdata->dev, "ETM tracing enabled\n");
 204         return 0;
 205 err:
 206         spin_unlock(&drvdata->spinlock);
 207         pm_runtime_put(drvdata->dev);
 208         return ret;
 209 }
 210
 211 static void etm4_disable_hw(void *info)
 212 {
 213         u32 control;
 214         struct etmv4_drvdata *drvdata = info;
 215
 216         CS_UNLOCK(drvdata->base);
 217
 218         control = readl_relaxed(drvdata->base + TRCPRGCTLR);
 219
 220         /* EN, bit[0] Trace unit enable bit */
 221         control &= ~0x1;
 222
 223         /* make sure everything completes before disabling */
 224         mb();
 225         isb();
 226         writel_relaxed(control, drvdata->base + TRCPRGCTLR);
 227
 228         CS_LOCK(drvdata->base);
 229
 230         dev_dbg(drvdata->dev, "cpu: %d disable smp call done\n", drvdata->cpu);
 231 }
 232
 233 static void etm4_disable(struct coresight_device *csdev)
 234 {
 235         struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 236
 237         /*
 238          * Taking hotplug lock here protects from clocks getting disabled
 239          * with tracing being left on (crash scenario) if user disable occurs
 240          * after cpu online mask indicates the cpu is offline but before the
 241          * DYING hotplug callback is serviced by the ETM driver.
 242          */
 243         get_online_cpus();
 244         spin_lock(&drvdata->spinlock);
 245
 246         /*
 247          * Executing etm4_disable_hw on the cpu whose ETM is being disabled
 248          * ensures that register writes occur when cpu is powered.
 249          */
 250         smp_call_function_single(drvdata->cpu, etm4_disable_hw, drvdata, 1);
 251         drvdata->enable = false;
 252
 253         spin_unlock(&drvdata->spinlock);
 254         put_online_cpus();
 255
 256         pm_runtime_put(drvdata->dev);
 257
 258         dev_info(drvdata->dev, "ETM tracing disabled\n");
 259 }
 260
 261 static const struct coresight_ops_source etm4_source_ops = {
 262         .trace_id       = etm4_trace_id,
 263         .enable         = etm4_enable,
 264         .disable        = etm4_disable,
 265 };
 266
 267 static const struct coresight_ops etm4_cs_ops = {
 268         .source_ops     = &etm4_source_ops,
 269 };
 270
 271 static int etm4_set_mode_exclude(struct etmv4_drvdata *drvdata, bool exclude)
 272 {
 273         u8 idx = drvdata->addr_idx;
 274
 275         /*
 276          * TRCACATRn.TYPE bit[1:0]: type of comparison
 277          * the trace unit performs
 278          */
 279         if (BMVAL(drvdata->addr_acc[idx], 0, 1) == ETM_INSTR_ADDR) {
 280                 if (idx % 2 != 0)
 281                         return -EINVAL;
 282
 283                 /*
 284                  * We are performing instruction address comparison. Set the
 285                  * relevant bit of ViewInst Include/Exclude Control register
 286                  * for corresponding address comparator pair.
 287                  */
 288                 if (drvdata->addr_type[idx] != ETM_ADDR_TYPE_RANGE ||
 289                     drvdata->addr_type[idx + 1] != ETM_ADDR_TYPE_RANGE)
 290                         return -EINVAL;
 291
 292                 if (exclude == true) {
 293                         /*
 294                          * Set exclude bit and unset the include bit
 295                          * corresponding to comparator pair
 296                          */
 297                         drvdata->viiectlr |= BIT(idx / 2 + 16);
 298                         drvdata->viiectlr &= ~BIT(idx / 2);
 299                 } else {
 300                         /*
 301                          * Set include bit and unset exclude bit
 302                          * corresponding to comparator pair
 303                          */
 304                         drvdata->viiectlr |= BIT(idx / 2);
 305                         drvdata->viiectlr &= ~BIT(idx / 2 + 16);
 306                 }
 307         }
 308         return 0;
 309 }
 310
 311 static ssize_t nr_pe_cmp_show(struct device *dev,
 312                               struct device_attribute *attr,
 313                               char *buf)
 314 {
 315         unsigned long val;
 316         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 317
 318         val = drvdata->nr_pe_cmp;
 319         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 320 }
 321 static DEVICE_ATTR_RO(nr_pe_cmp);
 322
 323 static ssize_t nr_addr_cmp_show(struct device *dev,
 324                                 struct device_attribute *attr,
 325                                 char *buf)
 326 {
 327         unsigned long val;
 328         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 329
 330         val = drvdata->nr_addr_cmp;
 331         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 332 }
 333 static DEVICE_ATTR_RO(nr_addr_cmp);
 334
 335 static ssize_t nr_cntr_show(struct device *dev,
 336                             struct device_attribute *attr,
 337                             char *buf)
 338 {
 339         unsigned long val;
 340         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 341
 342         val = drvdata->nr_cntr;
 343         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 344 }
 345 static DEVICE_ATTR_RO(nr_cntr);
 346
 347 static ssize_t nr_ext_inp_show(struct device *dev,
 348                                struct device_attribute *attr,
 349                                char *buf)
 350 {
 351         unsigned long val;
 352         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 353
 354         val = drvdata->nr_ext_inp;
 355         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 356 }
 357 static DEVICE_ATTR_RO(nr_ext_inp);
 358
 359 static ssize_t numcidc_show(struct device *dev,
 360                             struct device_attribute *attr,
 361                             char *buf)
 362 {
 363         unsigned long val;
 364         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 365
 366         val = drvdata->numcidc;
 367         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 368 }
 369 static DEVICE_ATTR_RO(numcidc);
 370
 371 static ssize_t numvmidc_show(struct device *dev,
 372                              struct device_attribute *attr,
 373                              char *buf)
 374 {
 375         unsigned long val;
 376         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 377
 378         val = drvdata->numvmidc;
 379         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 380 }
 381 static DEVICE_ATTR_RO(numvmidc);
 382
 383 static ssize_t nrseqstate_show(struct device *dev,
 384                                struct device_attribute *attr,
 385                                char *buf)
 386 {
 387         unsigned long val;
 388         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 389
 390         val = drvdata->nrseqstate;
 391         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 392 }
 393 static DEVICE_ATTR_RO(nrseqstate);
 394
 395 static ssize_t nr_resource_show(struct device *dev,
 396                                 struct device_attribute *attr,
 397                                 char *buf)
 398 {
 399         unsigned long val;
 400         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 401
 402         val = drvdata->nr_resource;
 403         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 404 }
 405 static DEVICE_ATTR_RO(nr_resource);
 406
 407 static ssize_t nr_ss_cmp_show(struct device *dev,
 408                               struct device_attribute *attr,
 409                               char *buf)
 410 {
 411         unsigned long val;
 412         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 413
 414         val = drvdata->nr_ss_cmp;
 415         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 416 }
 417 static DEVICE_ATTR_RO(nr_ss_cmp);
 418
 419 static ssize_t reset_store(struct device *dev,
 420                            struct device_attribute *attr,
 421                            const char *buf, size_t size)
 422 {
 423         int i;
 424         unsigned long val;
 425         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 426
 427         if (kstrtoul(buf, 16, &val))
 428                 return -EINVAL;
 429
 430         spin_lock(&drvdata->spinlock);
 431         if (val)
 432                 drvdata->mode = 0x0;
 433
 434         /* Disable data tracing: do not trace load and store data transfers */
 435         drvdata->mode &= ~(ETM_MODE_LOAD | ETM_MODE_STORE);
 436         drvdata->cfg &= ~(BIT(1) | BIT(2));
 437
 438         /* Disable data value and data address tracing */
 439         drvdata->mode &= ~(ETM_MODE_DATA_TRACE_ADDR |
 440                            ETM_MODE_DATA_TRACE_VAL);
 441         drvdata->cfg &= ~(BIT(16) | BIT(17));
 442
 443         /* Disable all events tracing */
 444         drvdata->eventctrl0 = 0x0;
 445         drvdata->eventctrl1 = 0x0;
 446
 447         /* Disable timestamp event */
 448         drvdata->ts_ctrl = 0x0;
 449
 450         /* Disable stalling */
 451         drvdata->stall_ctrl = 0x0;
 452
 453         /* Reset trace synchronization period  to 2^8 = 256 bytes*/
 454         if (drvdata->syncpr == false)
 455                 drvdata->syncfreq = 0x8;
 456
 457         /*
 458          * Enable ViewInst to trace everything with start-stop logic in
 459          * started state. ARM recommends start-stop logic is set before
 460          * each trace run.
 461          */
 462         drvdata->vinst_ctrl |= BIT(0);
 463         if (drvdata->nr_addr_cmp == true) {
 464                 drvdata->mode |= ETM_MODE_VIEWINST_STARTSTOP;
 465                 /* SSSTATUS, bit[9] */
 466                 drvdata->vinst_ctrl |= BIT(9);
 467         }
 468
 469         /* No address range filtering for ViewInst */
 470         drvdata->viiectlr = 0x0;
 471
 472         /* No start-stop filtering for ViewInst */
 473         drvdata->vissctlr = 0x0;
 474
 475         /* Disable seq events */
 476         for (i = 0; i < drvdata->nrseqstate-1; i++)
 477                 drvdata->seq_ctrl[i] = 0x0;
 478         drvdata->seq_rst = 0x0;
 479         drvdata->seq_state = 0x0;
 480
 481         /* Disable external input events */
 482         drvdata->ext_inp = 0x0;
 483
 484         drvdata->cntr_idx = 0x0;
 485         for (i = 0; i < drvdata->nr_cntr; i++) {
 486                 drvdata->cntrldvr[i] = 0x0;
 487                 drvdata->cntr_ctrl[i] = 0x0;
 488                 drvdata->cntr_val[i] = 0x0;
 489         }
 490
 491         drvdata->res_idx = 0x0;
 492         for (i = 0; i < drvdata->nr_resource; i++)
 493                 drvdata->res_ctrl[i] = 0x0;
 494
 495         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
 496                 drvdata->ss_ctrl[i] = 0x0;
 497                 drvdata->ss_pe_cmp[i] = 0x0;
 498         }
 499
 500         drvdata->addr_idx = 0x0;
 501         for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
 502                 drvdata->addr_val[i] = 0x0;
 503                 drvdata->addr_acc[i] = 0x0;
 504                 drvdata->addr_type[i] = ETM_ADDR_TYPE_NONE;
 505         }
 506
 507         drvdata->ctxid_idx = 0x0;
 508         for (i = 0; i < drvdata->numcidc; i++)
 509                 drvdata->ctxid_val[i] = 0x0;
 510         drvdata->ctxid_mask0 = 0x0;
 511         drvdata->ctxid_mask1 = 0x0;
 512
 513         drvdata->vmid_idx = 0x0;
 514         for (i = 0; i < drvdata->numvmidc; i++)
 515                 drvdata->vmid_val[i] = 0x0;
 516         drvdata->vmid_mask0 = 0x0;
 517         drvdata->vmid_mask1 = 0x0;
 518
 519         drvdata->trcid = drvdata->cpu + 1;
 520         spin_unlock(&drvdata->spinlock);
 521         return size;
 522 }
 523 static DEVICE_ATTR_WO(reset);
 524
 525 static ssize_t mode_show(struct device *dev,
 526                          struct device_attribute *attr,
 527                          char *buf)
 528 {
 529         unsigned long val;
 530         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 531
 532         val = drvdata->mode;
 533         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 534 }
 535
 536 static ssize_t mode_store(struct device *dev,
 537                           struct device_attribute *attr,
 538                           const char *buf, size_t size)
 539 {
 540         unsigned long val, mode;
 541         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 542
 543         if (kstrtoul(buf, 16, &val))
 544                 return -EINVAL;
 545
 546         spin_lock(&drvdata->spinlock);
 547         drvdata->mode = val & ETMv4_MODE_ALL;
 548
 549         if (drvdata->mode & ETM_MODE_EXCLUDE)
 550                 etm4_set_mode_exclude(drvdata, true);
 551         else
 552                 etm4_set_mode_exclude(drvdata, false);
 553
 554         if (drvdata->instrp0 == true) {
 555                 /* start by clearing instruction P0 field */
 556                 drvdata->cfg  &= ~(BIT(1) | BIT(2));
 557                 if (drvdata->mode & ETM_MODE_LOAD)
 558                         /* 0b01 Trace load instructions as P0 instructions */
 559                         drvdata->cfg  |= BIT(1);
 560                 if (drvdata->mode & ETM_MODE_STORE)
 561                         /* 0b10 Trace store instructions as P0 instructions */
 562                         drvdata->cfg  |= BIT(2);
 563                 if (drvdata->mode & ETM_MODE_LOAD_STORE)
 564                         /*
 565                          * 0b11 Trace load and store instructions
 566                          * as P0 instructions
 567                          */
 568                         drvdata->cfg  |= BIT(1) | BIT(2);
 569         }
 570
 571         /* bit[3], Branch broadcast mode */
 572         if ((drvdata->mode & ETM_MODE_BB) && (drvdata->trcbb == true))
 573                 drvdata->cfg |= BIT(3);
 574         else
 575                 drvdata->cfg &= ~BIT(3);
 576
 577         /* bit[4], Cycle counting instruction trace bit */
 578         if ((drvdata->mode & ETMv4_MODE_CYCACC) &&
 579                 (drvdata->trccci == true))
 580                 drvdata->cfg |= BIT(4);
 581         else
 582                 drvdata->cfg &= ~BIT(4);
 583
 584         /* bit[6], Context ID tracing bit */
 585         if ((drvdata->mode & ETMv4_MODE_CTXID) && (drvdata->ctxid_size))
 586                 drvdata->cfg |= BIT(6);
 587         else
 588                 drvdata->cfg &= ~BIT(6);
 589
 590         if ((drvdata->mode & ETM_MODE_VMID) && (drvdata->vmid_size))
 591                 drvdata->cfg |= BIT(7);
 592         else
 593                 drvdata->cfg &= ~BIT(7);
 594
 595         /* bits[10:8], Conditional instruction tracing bit */
 596         mode = ETM_MODE_COND(drvdata->mode);
 597         if (drvdata->trccond == true) {
 598                 drvdata->cfg &= ~(BIT(8) | BIT(9) | BIT(10));
 599                 drvdata->cfg |= mode << 8;
 600         }
 601
 602         /* bit[11], Global timestamp tracing bit */
 603         if ((drvdata->mode & ETMv4_MODE_TIMESTAMP) && (drvdata->ts_size))
 604                 drvdata->cfg |= BIT(11);
 605         else
 606                 drvdata->cfg &= ~BIT(11);
 607
 608         /* bit[12], Return stack enable bit */
 609         if ((drvdata->mode & ETM_MODE_RETURNSTACK) &&
 610                 (drvdata->retstack == true))
 611                 drvdata->cfg |= BIT(12);
 612         else
 613                 drvdata->cfg &= ~BIT(12);
 614
 615         /* bits[14:13], Q element enable field */
 616         mode = ETM_MODE_QELEM(drvdata->mode);
 617         /* start by clearing QE bits */
 618         drvdata->cfg &= ~(BIT(13) | BIT(14));
 619         /* if supported, Q elements with instruction counts are enabled */
 620         if ((mode & BIT(0)) && (drvdata->q_support & BIT(0)))
 621                 drvdata->cfg |= BIT(13);
 622         /*
 623          * if supported, Q elements with and without instruction
 624          * counts are enabled
 625          */
 626         if ((mode & BIT(1)) && (drvdata->q_support & BIT(1)))
 627                 drvdata->cfg |= BIT(14);
 628
 629         /* bit[11], AMBA Trace Bus (ATB) trigger enable bit */
 630         if ((drvdata->mode & ETM_MODE_ATB_TRIGGER) &&
 631             (drvdata->atbtrig == true))
 632                 drvdata->eventctrl1 |= BIT(11);
 633         else
 634                 drvdata->eventctrl1 &= ~BIT(11);
 635
 636         /* bit[12], Low-power state behavior override bit */
 637         if ((drvdata->mode & ETM_MODE_LPOVERRIDE) &&
 638             (drvdata->lpoverride == true))
 639                 drvdata->eventctrl1 |= BIT(12);
 640         else
 641                 drvdata->eventctrl1 &= ~BIT(12);
 642
 643         /* bit[8], Instruction stall bit */
 644         if (drvdata->mode & ETM_MODE_ISTALL_EN)
 645                 drvdata->stall_ctrl |= BIT(8);
 646         else
 647                 drvdata->stall_ctrl &= ~BIT(8);
 648
 649         /* bit[10], Prioritize instruction trace bit */
 650         if (drvdata->mode & ETM_MODE_INSTPRIO)
 651                 drvdata->stall_ctrl |= BIT(10);
 652         else
 653                 drvdata->stall_ctrl &= ~BIT(10);
 654
 655         /* bit[13], Trace overflow prevention bit */
 656         if ((drvdata->mode & ETM_MODE_NOOVERFLOW) &&
 657                 (drvdata->nooverflow == true))
 658                 drvdata->stall_ctrl |= BIT(13);
 659         else
 660                 drvdata->stall_ctrl &= ~BIT(13);
 661
 662         /* bit[9] Start/stop logic control bit */
 663         if (drvdata->mode & ETM_MODE_VIEWINST_STARTSTOP)
 664                 drvdata->vinst_ctrl |= BIT(9);
 665         else
 666                 drvdata->vinst_ctrl &= ~BIT(9);
 667
 668         /* bit[10], Whether a trace unit must trace a Reset exception */
 669         if (drvdata->mode & ETM_MODE_TRACE_RESET)
 670                 drvdata->vinst_ctrl |= BIT(10);
 671         else
 672                 drvdata->vinst_ctrl &= ~BIT(10);
 673
 674         /* bit[11], Whether a trace unit must trace a system error exception */
 675         if ((drvdata->mode & ETM_MODE_TRACE_ERR) &&
 676                 (drvdata->trc_error == true))
 677                 drvdata->vinst_ctrl |= BIT(11);
 678         else
 679                 drvdata->vinst_ctrl &= ~BIT(11);
 680
 681         spin_unlock(&drvdata->spinlock);
 682         return size;
 683 }
 684 static DEVICE_ATTR_RW(mode);
 685
 686 static ssize_t pe_show(struct device *dev,
 687                        struct device_attribute *attr,
 688                        char *buf)
 689 {
 690         unsigned long val;
 691         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 692
 693         val = drvdata->pe_sel;
 694         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 695 }
 696
 697 static ssize_t pe_store(struct device *dev,
 698                         struct device_attribute *attr,
 699                         const char *buf, size_t size)
 700 {
 701         unsigned long val;
 702         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 703
 704         if (kstrtoul(buf, 16, &val))
 705                 return -EINVAL;
 706
 707         spin_lock(&drvdata->spinlock);
 708         if (val > drvdata->nr_pe) {
 709                 spin_unlock(&drvdata->spinlock);
 710                 return -EINVAL;
 711         }
 712
 713         drvdata->pe_sel = val;
 714         spin_unlock(&drvdata->spinlock);
 715         return size;
 716 }
 717 static DEVICE_ATTR_RW(pe);
 718
 719 static ssize_t event_show(struct device *dev,
 720                           struct device_attribute *attr,
 721                           char *buf)
 722 {
 723         unsigned long val;
 724         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 725
 726         val = drvdata->eventctrl0;
 727         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 728 }
 729
 730 static ssize_t event_store(struct device *dev,
 731                            struct device_attribute *attr,
 732                            const char *buf, size_t size)
 733 {
 734         unsigned long val;
 735         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 736
 737         if (kstrtoul(buf, 16, &val))
 738                 return -EINVAL;
 739
 740         spin_lock(&drvdata->spinlock);
 741         switch (drvdata->nr_event) {
 742         case 0x0:
 743                 /* EVENT0, bits[7:0] */
 744                 drvdata->eventctrl0 = val & 0xFF;
 745                 break;
 746         case 0x1:
 747                  /* EVENT1, bits[15:8] */
 748                 drvdata->eventctrl0 = val & 0xFFFF;
 749                 break;
 750         case 0x2:
 751                 /* EVENT2, bits[23:16] */
 752                 drvdata->eventctrl0 = val & 0xFFFFFF;
 753                 break;
 754         case 0x3:
 755                 /* EVENT3, bits[31:24] */
 756                 drvdata->eventctrl0 = val;
 757                 break;
 758         default:
 759                 break;
 760         }
 761         spin_unlock(&drvdata->spinlock);
 762         return size;
 763 }
 764 static DEVICE_ATTR_RW(event);
 765
 766 static ssize_t event_instren_show(struct device *dev,
 767                                   struct device_attribute *attr,
 768                                   char *buf)
 769 {
 770         unsigned long val;
 771         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 772
 773         val = BMVAL(drvdata->eventctrl1, 0, 3);
 774         return scnprintf(buf, PAGE_SIZE, "%#lx\n", val);
 775 }
 776
 777 static ssize_t event_instren_store(struct device *dev,
 778                                    struct device_attribute *attr,
 779                                    const char *buf, size_t size)
 780 {
 781         unsigned long val;
 782         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 783
 784         if (kstrtoul(buf, 16, &val))
 785                 return -EINVAL;
 786
 787         spin_lock(&drvdata->spinlock);
 788         /* start by clearing all instruction event enable bits */
 789         drvdata->eventctrl1 &= ~(BIT(0) | BIT(1) | BIT(2) | BIT(3));
 790         switch (drvdata->nr_event) {
 791         case 0x0:
 792                 /* generate Event element for event 1 */
 793                 drvdata->eventctrl1 |= val & BIT(1);
 794                 break;
 795         case 0x1:
 796                 /* generate Event element for event 1 and 2 */
 797                 drvdata->eventctrl1 |= val & (BIT(0) | BIT(1));
 798                 break;
 799         case 0x2:
 800                 /* generate Event element for event 1, 2 and 3 */
 801                 drvdata->eventctrl1 |= val & (BIT(0) | BIT(1) | BIT(2));
 802                 break;
 803         case 0x3:
 804                 /* generate Event element for all 4 events */
 805                 drvdata->eventctrl1 |= val & 0xF;
 806                 break;
 807         default:
 808                 break;
 809         }
 810         spin_unlock(&drvdata->spinlock);
 811         return size;
 812 }
 813 static DEVICE_ATTR_RW(event_instren);
 814
 815 static ssize_t cpu_show(struct device *dev,
 816                         struct device_attribute *attr, char *buf)
 817 {
 818         int val;
 819         struct etmv4_drvdata *drvdata = dev_get_drvdata(dev->parent);
 820
 821         val = drvdata->cpu;
 822         return scnprintf(buf, PAGE_SIZE, "%d\n", val);
 823
 824 }
 825 static DEVICE_ATTR_RO(cpu);
 826
 827 static struct attribute *coresight_etmv4_attrs[] = {
 828         &dev_attr_nr_pe_cmp.attr,
 829         &dev_attr_nr_addr_cmp.attr,
 830         &dev_attr_nr_cntr.attr,
 831         &dev_attr_nr_ext_inp.attr,
 832         &dev_attr_numcidc.attr,
 833         &dev_attr_numvmidc.attr,
 834         &dev_attr_nrseqstate.attr,
 835         &dev_attr_nr_resource.attr,
 836         &dev_attr_nr_ss_cmp.attr,
 837         &dev_attr_reset.attr,
 838         &dev_attr_mode.attr,
 839         &dev_attr_pe.attr,
 840         &dev_attr_event.attr,
 841         &dev_attr_event_instren.attr,
 842         &dev_attr_cpu.attr,
 843         NULL,
 844 };
 845 ATTRIBUTE_GROUPS(coresight_etmv4);
 846
 847 static void etm4_init_arch_data(void *info)
 848 {
 849         u32 etmidr0;
 850         u32 etmidr1;
 851         u32 etmidr2;
 852         u32 etmidr3;
 853         u32 etmidr4;
 854         u32 etmidr5;
 855         struct etmv4_drvdata *drvdata = info;
 856
 857         CS_UNLOCK(drvdata->base);
 858
 859         /* find all capabilities of the tracing unit */
 860         etmidr0 = readl_relaxed(drvdata->base + TRCIDR0);
 861
 862         /* INSTP0, bits[2:1] P0 tracing support field */
 863         if (BMVAL(etmidr0, 1, 1) && BMVAL(etmidr0, 2, 2))
 864                 drvdata->instrp0 = true;
 865         else
 866                 drvdata->instrp0 = false;
 867
 868         /* TRCBB, bit[5] Branch broadcast tracing support bit */
 869         if (BMVAL(etmidr0, 5, 5))
 870                 drvdata->trcbb = true;
 871         else
 872                 drvdata->trcbb = false;
 873
 874         /* TRCCOND, bit[6] Conditional instruction tracing support bit */
 875         if (BMVAL(etmidr0, 6, 6))
 876                 drvdata->trccond = true;
 877         else
 878                 drvdata->trccond = false;
 879
 880         /* TRCCCI, bit[7] Cycle counting instruction bit */
 881         if (BMVAL(etmidr0, 7, 7))
 882                 drvdata->trccci = true;
 883         else
 884                 drvdata->trccci = false;
 885
 886         /* RETSTACK, bit[9] Return stack bit */
 887         if (BMVAL(etmidr0, 9, 9))
 888                 drvdata->retstack = true;
 889         else
 890                 drvdata->retstack = false;
 891
 892         /* NUMEVENT, bits[11:10] Number of events field */
 893         drvdata->nr_event = BMVAL(etmidr0, 10, 11);
 894         /* QSUPP, bits[16:15] Q element support field */
 895         drvdata->q_support = BMVAL(etmidr0, 15, 16);
 896         /* TSSIZE, bits[28:24] Global timestamp size field */
 897         drvdata->ts_size = BMVAL(etmidr0, 24, 28);
 898
 899         /* base architecture of trace unit */
 900         etmidr1 = readl_relaxed(drvdata->base + TRCIDR1);
 901         /*
 902          * TRCARCHMIN, bits[7:4] architecture the minor version number
 903          * TRCARCHMAJ, bits[11:8] architecture major versin number
 904          */
 905         drvdata->arch = BMVAL(etmidr1, 4, 11);
 906
 907         /* maximum size of resources */
 908         etmidr2 = readl_relaxed(drvdata->base + TRCIDR2);
 909         /* CIDSIZE, bits[9:5] Indicates the Context ID size */
 910         drvdata->ctxid_size = BMVAL(etmidr2, 5, 9);
 911         /* VMIDSIZE, bits[14:10] Indicates the VMID size */
 912         drvdata->vmid_size = BMVAL(etmidr2, 10, 14);
 913         /* CCSIZE, bits[28:25] size of the cycle counter in bits minus 12 */
 914         drvdata->ccsize = BMVAL(etmidr2, 25, 28);
 915
 916         etmidr3 = readl_relaxed(drvdata->base + TRCIDR3);
 917         /* CCITMIN, bits[11:0] minimum threshold value that can be programmed */
 918         drvdata->ccitmin = BMVAL(etmidr3, 0, 11);
 919         /* EXLEVEL_S, bits[19:16] Secure state instruction tracing */
 920         drvdata->s_ex_level = BMVAL(etmidr3, 16, 19);
 921         /* EXLEVEL_NS, bits[23:20] Non-secure state instruction tracing */
 922         drvdata->ns_ex_level = BMVAL(etmidr3, 20, 23);
 923
 924         /*
 925          * TRCERR, bit[24] whether a trace unit can trace a
 926          * system error exception.
 927          */
 928         if (BMVAL(etmidr3, 24, 24))
 929                 drvdata->trc_error = true;
 930         else
 931                 drvdata->trc_error = false;
 932
 933         /* SYNCPR, bit[25] implementation has a fixed synchronization period? */
 934         if (BMVAL(etmidr3, 25, 25))
 935                 drvdata->syncpr = true;
 936         else
 937                 drvdata->syncpr = false;
 938
 939         /* STALLCTL, bit[26] is stall control implemented? */
 940         if (BMVAL(etmidr3, 26, 26))
 941                 drvdata->stallctl = true;
 942         else
 943                 drvdata->stallctl = false;
 944
 945         /* SYSSTALL, bit[27] implementation can support stall control? */
 946         if (BMVAL(etmidr3, 27, 27))
 947                 drvdata->sysstall = true;
 948         else
 949                 drvdata->sysstall = false;
 950
 951         /* NUMPROC, bits[30:28] the number of PEs available for tracing */
 952         drvdata->nr_pe = BMVAL(etmidr3, 28, 30);
 953
 954         /* NOOVERFLOW, bit[31] is trace overflow prevention supported */
 955         if (BMVAL(etmidr3, 31, 31))
 956                 drvdata->nooverflow = true;
 957         else
 958                 drvdata->nooverflow = false;
 959
 960         /* number of resources trace unit supports */
 961         etmidr4 = readl_relaxed(drvdata->base + TRCIDR4);
 962         /* NUMACPAIRS, bits[0:3] number of addr comparator pairs for tracing */
 963         drvdata->nr_addr_cmp = BMVAL(etmidr4, 0, 3);
 964         /* NUMPC, bits[15:12] number of PE comparator inputs for tracing */
 965         drvdata->nr_pe_cmp = BMVAL(etmidr4, 12, 15);
 966         /* NUMRSPAIR, bits[19:16] the number of resource pairs for tracing */
 967         drvdata->nr_resource = BMVAL(etmidr4, 16, 19);
 968         /*
 969          * NUMSSCC, bits[23:20] the number of single-shot
 970          * comparator control for tracing
 971          */
 972         drvdata->nr_ss_cmp = BMVAL(etmidr4, 20, 23);
 973         /* NUMCIDC, bits[27:24] number of Context ID comparators for tracing */
 974         drvdata->numcidc = BMVAL(etmidr4, 24, 27);
 975         /* NUMVMIDC, bits[31:28] number of VMID comparators for tracing */
 976         drvdata->numvmidc = BMVAL(etmidr4, 28, 31);
 977
 978         etmidr5 = readl_relaxed(drvdata->base + TRCIDR5);
 979         /* NUMEXTIN, bits[8:0] number of external inputs implemented */
 980         drvdata->nr_ext_inp = BMVAL(etmidr5, 0, 8);
 981         /* TRACEIDSIZE, bits[21:16] indicates the trace ID width */
 982         drvdata->trcid_size = BMVAL(etmidr5, 16, 21);
 983         /* ATBTRIG, bit[22] implementation can support ATB triggers? */
 984         if (BMVAL(etmidr5, 22, 22))
 985                 drvdata->atbtrig = true;
 986         else
 987                 drvdata->atbtrig = false;
 988         /*
 989          * LPOVERRIDE, bit[23] implementation supports
 990          * low-power state override
 991          */
 992         if (BMVAL(etmidr5, 23, 23))
 993                 drvdata->lpoverride = true;
 994         else
 995                 drvdata->lpoverride = false;
 996         /* NUMSEQSTATE, bits[27:25] number of sequencer states implemented */
 997         drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
 998         /* NUMCNTR, bits[30:28] number of counters available for tracing */
 999         drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
1000         CS_LOCK(drvdata->base);
1001 }
1002
1003 static void etm4_init_default_data(struct etmv4_drvdata *drvdata)
1004 {
1005         int i;
1006
1007         drvdata->pe_sel = 0x0;
1008         drvdata->cfg = (ETMv4_MODE_CTXID | ETM_MODE_VMID |
1009                         ETMv4_MODE_TIMESTAMP | ETM_MODE_RETURNSTACK);
1010
1011         /* disable all events tracing */
1012         drvdata->eventctrl0 = 0x0;
1013         drvdata->eventctrl1 = 0x0;
1014
1015         /* disable stalling */
1016         drvdata->stall_ctrl = 0x0;
1017
1018         /* disable timestamp event */
1019         drvdata->ts_ctrl = 0x0;
1020
1021         /* enable trace synchronization every 4096 bytes for trace */
1022         if (drvdata->syncpr == false)
1023                 drvdata->syncfreq = 0xC;
1024
1025         /*
1026          *  enable viewInst to trace everything with start-stop logic in
1027          *  started state
1028          */
1029         drvdata->vinst_ctrl |= BIT(0);
1030         /* set initial state of start-stop logic */
1031         if (drvdata->nr_addr_cmp)
1032                 drvdata->vinst_ctrl |= BIT(9);
1033
1034         /* no address range filtering for ViewInst */
1035         drvdata->viiectlr = 0x0;
1036         /* no start-stop filtering for ViewInst */
1037         drvdata->vissctlr = 0x0;
1038
1039         /* disable seq events */
1040         for (i = 0; i < drvdata->nrseqstate-1; i++)
1041                 drvdata->seq_ctrl[i] = 0x0;
1042         drvdata->seq_rst = 0x0;
1043         drvdata->seq_state = 0x0;
1044
1045         /* disable external input events */
1046         drvdata->ext_inp = 0x0;
1047
1048         for (i = 0; i < drvdata->nr_cntr; i++) {
1049                 drvdata->cntrldvr[i] = 0x0;
1050                 drvdata->cntr_ctrl[i] = 0x0;
1051                 drvdata->cntr_val[i] = 0x0;
1052         }
1053
1054         for (i = 2; i < drvdata->nr_resource * 2; i++)
1055                 drvdata->res_ctrl[i] = 0x0;
1056
1057         for (i = 0; i < drvdata->nr_ss_cmp; i++) {
1058                 drvdata->ss_ctrl[i] = 0x0;
1059                 drvdata->ss_pe_cmp[i] = 0x0;
1060         }
1061
1062         if (drvdata->nr_addr_cmp >= 1) {
1063                 drvdata->addr_val[0] = (unsigned long)_stext;
1064                 drvdata->addr_val[1] = (unsigned long)_etext;
1065                 drvdata->addr_type[0] = ETM_ADDR_TYPE_RANGE;
1066                 drvdata->addr_type[1] = ETM_ADDR_TYPE_RANGE;
1067         }
1068
1069         for (i = 0; i < drvdata->numcidc; i++)
1070                 drvdata->ctxid_val[i] = 0x0;
1071         drvdata->ctxid_mask0 = 0x0;
1072         drvdata->ctxid_mask1 = 0x0;
1073
1074         for (i = 0; i < drvdata->numvmidc; i++)
1075                 drvdata->vmid_val[i] = 0x0;
1076         drvdata->vmid_mask0 = 0x0;
1077         drvdata->vmid_mask1 = 0x0;
1078
1079         /*
1080          * A trace ID value of 0 is invalid, so let's start at some
1081          * random value that fits in 7 bits.  ETMv3.x has 0x10 so let's
1082          * start at 0x20.
1083          */
1084         drvdata->trcid = 0x20 + drvdata->cpu;
1085 }
1086
1087 static int etm4_cpu_callback(struct notifier_block *nfb, unsigned long action,
1088                             void *hcpu)
1089 {
1090         unsigned int cpu = (unsigned long)hcpu;
1091
1092         if (!etmdrvdata[cpu])
1093                 goto out;
1094
1095         switch (action & (~CPU_TASKS_FROZEN)) {
1096         case CPU_STARTING:
1097                 spin_lock(&etmdrvdata[cpu]->spinlock);
1098                 if (!etmdrvdata[cpu]->os_unlock) {
1099                         etm4_os_unlock(etmdrvdata[cpu]);
1100                         etmdrvdata[cpu]->os_unlock = true;
1101                 }
1102
1103                 if (etmdrvdata[cpu]->enable)
1104                         etm4_enable_hw(etmdrvdata[cpu]);
1105                 spin_unlock(&etmdrvdata[cpu]->spinlock);
1106                 break;
1107
1108         case CPU_ONLINE:
1109                 if (etmdrvdata[cpu]->boot_enable &&
1110                         !etmdrvdata[cpu]->sticky_enable)
1111                         coresight_enable(etmdrvdata[cpu]->csdev);
1112                 break;
1113
1114         case CPU_DYING:
1115                 spin_lock(&etmdrvdata[cpu]->spinlock);
1116                 if (etmdrvdata[cpu]->enable)
1117                         etm4_disable_hw(etmdrvdata[cpu]);
1118                 spin_unlock(&etmdrvdata[cpu]->spinlock);
1119                 break;
1120         }
1121 out:
1122         return NOTIFY_OK;
1123 }
1124
1125 static struct notifier_block etm4_cpu_notifier = {
1126         .notifier_call = etm4_cpu_callback,
1127 };
1128
1129 static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
1130 {
1131         int ret;
1132         void __iomem *base;
1133         struct device *dev = &adev->dev;
1134         struct coresight_platform_data *pdata = NULL;
1135         struct etmv4_drvdata *drvdata;
1136         struct resource *res = &adev->res;
1137         struct coresight_desc *desc;
1138         struct device_node *np = adev->dev.of_node;
1139
1140         desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
1141         if (!desc)
1142                 return -ENOMEM;
1143
1144         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
1145         if (!drvdata)
1146                 return -ENOMEM;
1147
1148         if (np) {
1149                 pdata = of_get_coresight_platform_data(dev, np);
1150                 if (IS_ERR(pdata))
1151                         return PTR_ERR(pdata);
1152                 adev->dev.platform_data = pdata;
1153         }
1154
1155         drvdata->dev = &adev->dev;
1156         dev_set_drvdata(dev, drvdata);
1157
1158         /* Validity for the resource is already checked by the AMBA core */
1159         base = devm_ioremap_resource(dev, res);
1160         if (IS_ERR(base))
1161                 return PTR_ERR(base);
1162
1163         drvdata->base = base;
1164
1165         spin_lock_init(&drvdata->spinlock);
1166
1167         drvdata->cpu = pdata ? pdata->cpu : 0;
1168
1169         get_online_cpus();
1170         etmdrvdata[drvdata->cpu] = drvdata;
1171
1172         if (!smp_call_function_single(drvdata->cpu, etm4_os_unlock, drvdata, 1))
1173                 drvdata->os_unlock = true;
1174
1175         if (smp_call_function_single(drvdata->cpu,
1176                                 etm4_init_arch_data,  drvdata, 1))
1177                 dev_err(dev, "ETM arch init failed\n");
1178
1179         if (!etm4_count++)
1180                 register_hotcpu_notifier(&etm4_cpu_notifier);
1181
1182         put_online_cpus();
1183
1184         if (etm4_arch_supported(drvdata->arch) == false) {
1185                 ret = -EINVAL;
1186                 goto err_arch_supported;
1187         }
1188         etm4_init_default_data(drvdata);
1189
1190         pm_runtime_put(&adev->dev);
1191
1192         desc->type = CORESIGHT_DEV_TYPE_SOURCE;
1193         desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
1194         desc->ops = &etm4_cs_ops;
1195         desc->pdata = pdata;
1196         desc->dev = dev;
1197         desc->groups = coresight_etmv4_groups;
1198         drvdata->csdev = coresight_register(desc);
1199         if (IS_ERR(drvdata->csdev)) {
1200                 ret = PTR_ERR(drvdata->csdev);
1201                 goto err_coresight_register;
1202         }
1203
1204         dev_info(dev, "%s initialized\n", (char *)id->data);
1205
1206         if (boot_enable) {
1207                 coresight_enable(drvdata->csdev);
1208                 drvdata->boot_enable = true;
1209         }
1210
1211         return 0;
1212
1213 err_arch_supported:
1214         pm_runtime_put(&adev->dev);
1215 err_coresight_register:
1216         if (--etm4_count == 0)
1217                 unregister_hotcpu_notifier(&etm4_cpu_notifier);
1218         return ret;
1219 }
1220
1221 static int etm4_remove(struct amba_device *adev)
1222 {
1223         struct etmv4_drvdata *drvdata = amba_get_drvdata(adev);
1224
1225         coresight_unregister(drvdata->csdev);
1226         if (--etm4_count == 0)
1227                 unregister_hotcpu_notifier(&etm4_cpu_notifier);
1228
1229         return 0;
1230 }
1231
1232 static struct amba_id etm4_ids[] = {
1233         {       /* ETM 4.0 - Qualcomm */
1234                 .id     = 0x0003b95d,
1235                 .mask   = 0x0003ffff,
1236                 .data   = "ETM 4.0",
1237         },
1238         {       /* ETM 4.0 - Juno board */
1239                 .id     = 0x000bb95e,
1240                 .mask   = 0x000fffff,
1241                 .data   = "ETM 4.0",
1242         },
1243         { 0, 0},
1244 };
1245
1246 static struct amba_driver etm4x_driver = {
1247         .drv = {
1248                 .name   = "coresight-etm4x",
1249         },
1250         .probe          = etm4_probe,
1251         .remove         = etm4_remove,
1252         .id_table       = etm4_ids,
1253 };
1254
1255 module_amba_driver(etm4x_driver);