drivers/hwtracing/coresight/coresight-tmc.c

   1 /* Copyright (c) 2012, The Linux Foundation. All rights reserved.
   2  *
   3  * Description: CoreSight Trace Memory Controller driver
   4  *
   5  * This program is free software; you can redistribute it and/or modify
   6  * it under the terms of the GNU General Public License version 2 and
   7  * only version 2 as published by the Free Software Foundation.
   8  *
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  */
  14
  15 #include <linux/kernel.h>
  16 #include <linux/init.h>
  17 #include <linux/types.h>
  18 #include <linux/device.h>
  19 #include <linux/io.h>
  20 #include <linux/err.h>
  21 #include <linux/fs.h>
  22 #include <linux/miscdevice.h>
  23 #include <linux/uaccess.h>
  24 #include <linux/slab.h>
  25 #include <linux/dma-mapping.h>
  26 #include <linux/spinlock.h>
  27 #include <linux/pm_runtime.h>
  28 #include <linux/of.h>
  29 #include <linux/coresight.h>
  30 #include <linux/amba/bus.h>
  31
  32 #include "coresight-priv.h"
  33
  34 #define TMC_RSZ                 0x004
  35 #define TMC_STS                 0x00c
  36 #define TMC_RRD                 0x010
  37 #define TMC_RRP                 0x014
  38 #define TMC_RWP                 0x018
  39 #define TMC_TRG                 0x01c
  40 #define TMC_CTL                 0x020
  41 #define TMC_RWD                 0x024
  42 #define TMC_MODE                0x028
  43 #define TMC_LBUFLEVEL           0x02c
  44 #define TMC_CBUFLEVEL           0x030
  45 #define TMC_BUFWM               0x034
  46 #define TMC_RRPHI               0x038
  47 #define TMC_RWPHI               0x03c
  48 #define TMC_AXICTL              0x110
  49 #define TMC_DBALO               0x118
  50 #define TMC_DBAHI               0x11c
  51 #define TMC_FFSR                0x300
  52 #define TMC_FFCR                0x304
  53 #define TMC_PSCR                0x308
  54 #define TMC_ITMISCOP0           0xee0
  55 #define TMC_ITTRFLIN            0xee8
  56 #define TMC_ITATBDATA0          0xeec
  57 #define TMC_ITATBCTR2           0xef0
  58 #define TMC_ITATBCTR1           0xef4
  59 #define TMC_ITATBCTR0           0xef8
  60
  61 /* register description */
  62 /* TMC_CTL - 0x020 */
  63 #define TMC_CTL_CAPT_EN         BIT(0)
  64 /* TMC_STS - 0x00C */
  65 #define TMC_STS_TRIGGERED       BIT(1)
  66 /* TMC_AXICTL - 0x110 */
  67 #define TMC_AXICTL_PROT_CTL_B0  BIT(0)
  68 #define TMC_AXICTL_PROT_CTL_B1  BIT(1)
  69 #define TMC_AXICTL_SCT_GAT_MODE BIT(7)
  70 #define TMC_AXICTL_WR_BURST_LEN 0xF00
  71 /* TMC_FFCR - 0x304 */
  72 #define TMC_FFCR_EN_FMT         BIT(0)
  73 #define TMC_FFCR_EN_TI          BIT(1)
  74 #define TMC_FFCR_FON_FLIN       BIT(4)
  75 #define TMC_FFCR_FON_TRIG_EVT   BIT(5)
  76 #define TMC_FFCR_FLUSHMAN       BIT(6)
  77 #define TMC_FFCR_TRIGON_TRIGIN  BIT(8)
  78 #define TMC_FFCR_STOP_ON_FLUSH  BIT(12)
  79
  80 #define TMC_STS_TMCREADY_BIT    2
  81 #define TMC_FFCR_FLUSHMAN_BIT   6
  82
  83 enum tmc_config_type {
  84         TMC_CONFIG_TYPE_ETB,
  85         TMC_CONFIG_TYPE_ETR,
  86         TMC_CONFIG_TYPE_ETF,
  87 };
  88
  89 enum tmc_mode {
  90         TMC_MODE_CIRCULAR_BUFFER,
  91         TMC_MODE_SOFTWARE_FIFO,
  92         TMC_MODE_HARDWARE_FIFO,
  93 };
  94
  95 enum tmc_mem_intf_width {
  96         TMC_MEM_INTF_WIDTH_32BITS       = 0x2,
  97         TMC_MEM_INTF_WIDTH_64BITS       = 0x3,
  98         TMC_MEM_INTF_WIDTH_128BITS      = 0x4,
  99         TMC_MEM_INTF_WIDTH_256BITS      = 0x5,
 100 };
 101
 102 /**
 103  * struct tmc_drvdata - specifics associated to an TMC component
 104  * @base:       memory mapped base address for this component.
 105  * @dev:        the device entity associated to this component.
 106  * @csdev:      component vitals needed by the framework.
 107  * @miscdev:    specifics to handle "/dev/xyz.tmc" entry.
 108  * @spinlock:   only one at a time pls.
 109  * @read_count: manages preparation of buffer for reading.
 110  * @buf:        area of memory where trace data get sent.
 111  * @paddr:      DMA start location in RAM.
 112  * @vaddr:      virtual representation of @paddr.
 113  * @size:       @buf size.
 114  * @enable:     this TMC is being used.
 115  * @config_type: TMC variant, must be of type @tmc_config_type.
 116  * @trigger_cntr: amount of words to store after a trigger.
 117  */
 118 struct tmc_drvdata {
 119         void __iomem            *base;
 120         struct device           *dev;
 121         struct coresight_device *csdev;
 122         struct miscdevice       miscdev;
 123         spinlock_t              spinlock;
 124         int                     read_count;
 125         bool                    reading;
 126         char                    *buf;
 127         dma_addr_t              paddr;
 128         void                    *vaddr;
 129         u32                     size;
 130         bool                    enable;
 131         enum tmc_config_type    config_type;
 132         u32                     trigger_cntr;
 133 };
 134
 135 static void tmc_wait_for_tmcready(struct tmc_drvdata *drvdata)
 136 {
 137         /* Ensure formatter, unformatter and hardware fifo are empty */
 138         if (coresight_timeout(drvdata->base,
 139                               TMC_STS, TMC_STS_TMCREADY_BIT, 1)) {
 140                 dev_err(drvdata->dev,
 141                         "timeout observed when probing at offset %#x\n",
 142                         TMC_STS);
 143         }
 144 }
 145
 146 static void tmc_flush_and_stop(struct tmc_drvdata *drvdata)
 147 {
 148         u32 ffcr;
 149
 150         ffcr = readl_relaxed(drvdata->base + TMC_FFCR);
 151         ffcr |= TMC_FFCR_STOP_ON_FLUSH;
 152         writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
 153         ffcr |= TMC_FFCR_FLUSHMAN;
 154         writel_relaxed(ffcr, drvdata->base + TMC_FFCR);
 155         /* Ensure flush completes */
 156         if (coresight_timeout(drvdata->base,
 157                               TMC_FFCR, TMC_FFCR_FLUSHMAN_BIT, 0)) {
 158                 dev_err(drvdata->dev,
 159                         "timeout observed when probing at offset %#x\n",
 160                         TMC_FFCR);
 161         }
 162
 163         tmc_wait_for_tmcready(drvdata);
 164 }
 165
 166 static void tmc_enable_hw(struct tmc_drvdata *drvdata)
 167 {
 168         writel_relaxed(TMC_CTL_CAPT_EN, drvdata->base + TMC_CTL);
 169 }
 170
 171 static void tmc_disable_hw(struct tmc_drvdata *drvdata)
 172 {
 173         writel_relaxed(0x0, drvdata->base + TMC_CTL);
 174 }
 175
 176 static void tmc_etb_enable_hw(struct tmc_drvdata *drvdata)
 177 {
 178         /* Zero out the memory to help with debug */
 179         memset(drvdata->buf, 0, drvdata->size);
 180
 181         CS_UNLOCK(drvdata->base);
 182
 183         /* Wait for TMCSReady bit to be set */
 184         tmc_wait_for_tmcready(drvdata);
 185
 186         writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
 187         writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
 188                        TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
 189                        TMC_FFCR_TRIGON_TRIGIN,
 190                        drvdata->base + TMC_FFCR);
 191
 192         writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
 193         tmc_enable_hw(drvdata);
 194
 195         CS_LOCK(drvdata->base);
 196 }
 197
 198 static void tmc_etr_enable_hw(struct tmc_drvdata *drvdata)
 199 {
 200         u32 axictl;
 201
 202         /* Zero out the memory to help with debug */
 203         memset(drvdata->vaddr, 0, drvdata->size);
 204
 205         CS_UNLOCK(drvdata->base);
 206
 207         /* Wait for TMCSReady bit to be set */
 208         tmc_wait_for_tmcready(drvdata);
 209
 210         writel_relaxed(drvdata->size / 4, drvdata->base + TMC_RSZ);
 211         writel_relaxed(TMC_MODE_CIRCULAR_BUFFER, drvdata->base + TMC_MODE);
 212
 213         axictl = readl_relaxed(drvdata->base + TMC_AXICTL);
 214         axictl |= TMC_AXICTL_WR_BURST_LEN;
 215         writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
 216         axictl &= ~TMC_AXICTL_SCT_GAT_MODE;
 217         writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
 218         axictl = (axictl &
 219                   ~(TMC_AXICTL_PROT_CTL_B0 | TMC_AXICTL_PROT_CTL_B1)) |
 220                   TMC_AXICTL_PROT_CTL_B1;
 221         writel_relaxed(axictl, drvdata->base + TMC_AXICTL);
 222
 223         writel_relaxed(drvdata->paddr, drvdata->base + TMC_DBALO);
 224         writel_relaxed(0x0, drvdata->base + TMC_DBAHI);
 225         writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI |
 226                        TMC_FFCR_FON_FLIN | TMC_FFCR_FON_TRIG_EVT |
 227                        TMC_FFCR_TRIGON_TRIGIN,
 228                        drvdata->base + TMC_FFCR);
 229         writel_relaxed(drvdata->trigger_cntr, drvdata->base + TMC_TRG);
 230         tmc_enable_hw(drvdata);
 231
 232         CS_LOCK(drvdata->base);
 233 }
 234
 235 static void tmc_etf_enable_hw(struct tmc_drvdata *drvdata)
 236 {
 237         CS_UNLOCK(drvdata->base);
 238
 239         /* Wait for TMCSReady bit to be set */
 240         tmc_wait_for_tmcready(drvdata);
 241
 242         writel_relaxed(TMC_MODE_HARDWARE_FIFO, drvdata->base + TMC_MODE);
 243         writel_relaxed(TMC_FFCR_EN_FMT | TMC_FFCR_EN_TI,
 244                        drvdata->base + TMC_FFCR);
 245         writel_relaxed(0x0, drvdata->base + TMC_BUFWM);
 246         tmc_enable_hw(drvdata);
 247
 248         CS_LOCK(drvdata->base);
 249 }
 250
 251 static int tmc_enable(struct tmc_drvdata *drvdata, enum tmc_mode mode)
 252 {
 253         unsigned long flags;
 254
 255         spin_lock_irqsave(&drvdata->spinlock, flags);
 256         if (drvdata->reading) {
 257                 spin_unlock_irqrestore(&drvdata->spinlock, flags);
 258                 return -EBUSY;
 259         }
 260
 261         if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
 262                 tmc_etb_enable_hw(drvdata);
 263         } else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
 264                 tmc_etr_enable_hw(drvdata);
 265         } else {
 266                 if (mode == TMC_MODE_CIRCULAR_BUFFER)
 267                         tmc_etb_enable_hw(drvdata);
 268                 else
 269                         tmc_etf_enable_hw(drvdata);
 270         }
 271         drvdata->enable = true;
 272         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 273
 274         dev_info(drvdata->dev, "TMC enabled\n");
 275         return 0;
 276 }
 277
 278 static int tmc_enable_sink(struct coresight_device *csdev, u32 mode)
 279 {
 280         struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 281
 282         return tmc_enable(drvdata, TMC_MODE_CIRCULAR_BUFFER);
 283 }
 284
 285 static int tmc_enable_link(struct coresight_device *csdev, int inport,
 286                            int outport)
 287 {
 288         struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 289
 290         return tmc_enable(drvdata, TMC_MODE_HARDWARE_FIFO);
 291 }
 292
 293 static void tmc_etb_dump_hw(struct tmc_drvdata *drvdata)
 294 {
 295         enum tmc_mem_intf_width memwidth;
 296         u8 memwords;
 297         char *bufp;
 298         u32 read_data;
 299         int i;
 300
 301         memwidth = BMVAL(readl_relaxed(drvdata->base + CORESIGHT_DEVID), 8, 10);
 302         if (memwidth == TMC_MEM_INTF_WIDTH_32BITS)
 303                 memwords = 1;
 304         else if (memwidth == TMC_MEM_INTF_WIDTH_64BITS)
 305                 memwords = 2;
 306         else if (memwidth == TMC_MEM_INTF_WIDTH_128BITS)
 307                 memwords = 4;
 308         else
 309                 memwords = 8;
 310
 311         bufp = drvdata->buf;
 312         while (1) {
 313                 for (i = 0; i < memwords; i++) {
 314                         read_data = readl_relaxed(drvdata->base + TMC_RRD);
 315                         if (read_data == 0xFFFFFFFF)
 316                                 return;
 317                         memcpy(bufp, &read_data, 4);
 318                         bufp += 4;
 319                 }
 320         }
 321 }
 322
 323 static void tmc_etb_disable_hw(struct tmc_drvdata *drvdata)
 324 {
 325         CS_UNLOCK(drvdata->base);
 326
 327         tmc_flush_and_stop(drvdata);
 328         tmc_etb_dump_hw(drvdata);
 329         tmc_disable_hw(drvdata);
 330
 331         CS_LOCK(drvdata->base);
 332 }
 333
 334 static void tmc_etr_dump_hw(struct tmc_drvdata *drvdata)
 335 {
 336         u32 rwp, val;
 337
 338         rwp = readl_relaxed(drvdata->base + TMC_RWP);
 339         val = readl_relaxed(drvdata->base + TMC_STS);
 340
 341         /* How much memory do we still have */
 342         if (val & BIT(0))
 343                 drvdata->buf = drvdata->vaddr + rwp - drvdata->paddr;
 344         else
 345                 drvdata->buf = drvdata->vaddr;
 346 }
 347
 348 static void tmc_etr_disable_hw(struct tmc_drvdata *drvdata)
 349 {
 350         CS_UNLOCK(drvdata->base);
 351
 352         tmc_flush_and_stop(drvdata);
 353         tmc_etr_dump_hw(drvdata);
 354         tmc_disable_hw(drvdata);
 355
 356         CS_LOCK(drvdata->base);
 357 }
 358
 359 static void tmc_etf_disable_hw(struct tmc_drvdata *drvdata)
 360 {
 361         CS_UNLOCK(drvdata->base);
 362
 363         tmc_flush_and_stop(drvdata);
 364         tmc_disable_hw(drvdata);
 365
 366         CS_LOCK(drvdata->base);
 367 }
 368
 369 static void tmc_disable(struct tmc_drvdata *drvdata, enum tmc_mode mode)
 370 {
 371         unsigned long flags;
 372
 373         spin_lock_irqsave(&drvdata->spinlock, flags);
 374         if (drvdata->reading)
 375                 goto out;
 376
 377         if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
 378                 tmc_etb_disable_hw(drvdata);
 379         } else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
 380                 tmc_etr_disable_hw(drvdata);
 381         } else {
 382                 if (mode == TMC_MODE_CIRCULAR_BUFFER)
 383                         tmc_etb_disable_hw(drvdata);
 384                 else
 385                         tmc_etf_disable_hw(drvdata);
 386         }
 387 out:
 388         drvdata->enable = false;
 389         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 390
 391         dev_info(drvdata->dev, "TMC disabled\n");
 392 }
 393
 394 static void tmc_disable_sink(struct coresight_device *csdev)
 395 {
 396         struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 397
 398         tmc_disable(drvdata, TMC_MODE_CIRCULAR_BUFFER);
 399 }
 400
 401 static void tmc_disable_link(struct coresight_device *csdev, int inport,
 402                              int outport)
 403 {
 404         struct tmc_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
 405
 406         tmc_disable(drvdata, TMC_MODE_HARDWARE_FIFO);
 407 }
 408
 409 static const struct coresight_ops_sink tmc_sink_ops = {
 410         .enable         = tmc_enable_sink,
 411         .disable        = tmc_disable_sink,
 412 };
 413
 414 static const struct coresight_ops_link tmc_link_ops = {
 415         .enable         = tmc_enable_link,
 416         .disable        = tmc_disable_link,
 417 };
 418
 419 static const struct coresight_ops tmc_etb_cs_ops = {
 420         .sink_ops       = &tmc_sink_ops,
 421 };
 422
 423 static const struct coresight_ops tmc_etr_cs_ops = {
 424         .sink_ops       = &tmc_sink_ops,
 425 };
 426
 427 static const struct coresight_ops tmc_etf_cs_ops = {
 428         .sink_ops       = &tmc_sink_ops,
 429         .link_ops       = &tmc_link_ops,
 430 };
 431
 432 static int tmc_read_prepare(struct tmc_drvdata *drvdata)
 433 {
 434         int ret = 0;
 435         unsigned long flags;
 436         enum tmc_mode mode;
 437
 438         spin_lock_irqsave(&drvdata->spinlock, flags);
 439         if (!drvdata->enable)
 440                 goto out;
 441
 442         switch (drvdata->config_type) {
 443         case TMC_CONFIG_TYPE_ETB:
 444                 tmc_etb_disable_hw(drvdata);
 445                 break;
 446         case TMC_CONFIG_TYPE_ETF:
 447                 /* There is no point in reading a TMC in HW FIFO mode */
 448                 mode = readl_relaxed(drvdata->base + TMC_MODE);
 449                 if (mode != TMC_MODE_CIRCULAR_BUFFER) {
 450                         ret = -EINVAL;
 451                         goto err;
 452                 }
 453
 454                 tmc_etb_disable_hw(drvdata);
 455                 break;
 456         case TMC_CONFIG_TYPE_ETR:
 457                 tmc_etr_disable_hw(drvdata);
 458                 break;
 459         default:
 460                 ret = -EINVAL;
 461                 goto err;
 462         }
 463
 464 out:
 465         drvdata->reading = true;
 466         dev_info(drvdata->dev, "TMC read start\n");
 467 err:
 468         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 469         return ret;
 470 }
 471
 472 static void tmc_read_unprepare(struct tmc_drvdata *drvdata)
 473 {
 474         unsigned long flags;
 475         enum tmc_mode mode;
 476
 477         spin_lock_irqsave(&drvdata->spinlock, flags);
 478         if (!drvdata->enable)
 479                 goto out;
 480
 481         switch (drvdata->config_type) {
 482         case TMC_CONFIG_TYPE_ETB:
 483                 tmc_etb_enable_hw(drvdata);
 484                 break;
 485         case TMC_CONFIG_TYPE_ETF:
 486                 /* Make sure we don't re-enable a TMC in HW FIFO mode */
 487                 mode = readl_relaxed(drvdata->base + TMC_MODE);
 488                 if (mode != TMC_MODE_CIRCULAR_BUFFER)
 489                         goto err;
 490
 491                 tmc_etb_enable_hw(drvdata);
 492                 break;
 493         case TMC_CONFIG_TYPE_ETR:
 494                 tmc_etr_disable_hw(drvdata);
 495                 break;
 496         default:
 497                 goto err;
 498         }
 499
 500 out:
 501         drvdata->reading = false;
 502         dev_info(drvdata->dev, "TMC read end\n");
 503 err:
 504         spin_unlock_irqrestore(&drvdata->spinlock, flags);
 505 }
 506
 507 static int tmc_open(struct inode *inode, struct file *file)
 508 {
 509         struct tmc_drvdata *drvdata = container_of(file->private_data,
 510                                                    struct tmc_drvdata, miscdev);
 511         int ret = 0;
 512
 513         if (drvdata->read_count++)
 514                 goto out;
 515
 516         ret = tmc_read_prepare(drvdata);
 517         if (ret)
 518                 return ret;
 519 out:
 520         nonseekable_open(inode, file);
 521
 522         dev_dbg(drvdata->dev, "%s: successfully opened\n", __func__);
 523         return 0;
 524 }
 525
 526 static ssize_t tmc_read(struct file *file, char __user *data, size_t len,
 527                         loff_t *ppos)
 528 {
 529         struct tmc_drvdata *drvdata = container_of(file->private_data,
 530                                                    struct tmc_drvdata, miscdev);
 531         char *bufp = drvdata->buf + *ppos;
 532
 533         if (*ppos + len > drvdata->size)
 534                 len = drvdata->size - *ppos;
 535
 536         if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
 537                 if (bufp == (char *)(drvdata->vaddr + drvdata->size))
 538                         bufp = drvdata->vaddr;
 539                 else if (bufp > (char *)(drvdata->vaddr + drvdata->size))
 540                         bufp -= drvdata->size;
 541                 if ((bufp + len) > (char *)(drvdata->vaddr + drvdata->size))
 542                         len = (char *)(drvdata->vaddr + drvdata->size) - bufp;
 543         }
 544
 545         if (copy_to_user(data, bufp, len)) {
 546                 dev_dbg(drvdata->dev, "%s: copy_to_user failed\n", __func__);
 547                 return -EFAULT;
 548         }
 549
 550         *ppos += len;
 551
 552         dev_dbg(drvdata->dev, "%s: %zu bytes copied, %d bytes left\n",
 553                 __func__, len, (int)(drvdata->size - *ppos));
 554         return len;
 555 }
 556
 557 static int tmc_release(struct inode *inode, struct file *file)
 558 {
 559         struct tmc_drvdata *drvdata = container_of(file->private_data,
 560                                                    struct tmc_drvdata, miscdev);
 561
 562         if (--drvdata->read_count) {
 563                 if (drvdata->read_count < 0) {
 564                         dev_err(drvdata->dev, "mismatched close\n");
 565                         drvdata->read_count = 0;
 566                 }
 567                 goto out;
 568         }
 569
 570         tmc_read_unprepare(drvdata);
 571 out:
 572         dev_dbg(drvdata->dev, "%s: released\n", __func__);
 573         return 0;
 574 }
 575
 576 static const struct file_operations tmc_fops = {
 577         .owner          = THIS_MODULE,
 578         .open           = tmc_open,
 579         .read           = tmc_read,
 580         .release        = tmc_release,
 581         .llseek         = no_llseek,
 582 };
 583
 584 #define coresight_tmc_simple_func(name, offset)                 \
 585         coresight_simple_func(struct tmc_drvdata, name, offset)
 586
 587 coresight_tmc_simple_func(rsz, TMC_RSZ);
 588 coresight_tmc_simple_func(sts, TMC_STS);
 589 coresight_tmc_simple_func(rrp, TMC_RRP);
 590 coresight_tmc_simple_func(rwp, TMC_RWP);
 591 coresight_tmc_simple_func(trg, TMC_TRG);
 592 coresight_tmc_simple_func(ctl, TMC_CTL);
 593 coresight_tmc_simple_func(ffsr, TMC_FFSR);
 594 coresight_tmc_simple_func(ffcr, TMC_FFCR);
 595 coresight_tmc_simple_func(mode, TMC_MODE);
 596 coresight_tmc_simple_func(pscr, TMC_PSCR);
 597 coresight_tmc_simple_func(devid, CORESIGHT_DEVID);
 598
 599 static struct attribute *coresight_tmc_mgmt_attrs[] = {
 600         &dev_attr_rsz.attr,
 601         &dev_attr_sts.attr,
 602         &dev_attr_rrp.attr,
 603         &dev_attr_rwp.attr,
 604         &dev_attr_trg.attr,
 605         &dev_attr_ctl.attr,
 606         &dev_attr_ffsr.attr,
 607         &dev_attr_ffcr.attr,
 608         &dev_attr_mode.attr,
 609         &dev_attr_pscr.attr,
 610         &dev_attr_devid.attr,
 611         NULL,
 612 };
 613
 614 ssize_t trigger_cntr_show(struct device *dev,
 615                           struct device_attribute *attr, char *buf)
 616 {
 617         struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
 618         unsigned long val = drvdata->trigger_cntr;
 619
 620         return sprintf(buf, "%#lx\n", val);
 621 }
 622
 623 static ssize_t trigger_cntr_store(struct device *dev,
 624                              struct device_attribute *attr,
 625                              const char *buf, size_t size)
 626 {
 627         int ret;
 628         unsigned long val;
 629         struct tmc_drvdata *drvdata = dev_get_drvdata(dev->parent);
 630
 631         ret = kstrtoul(buf, 16, &val);
 632         if (ret)
 633                 return ret;
 634
 635         drvdata->trigger_cntr = val;
 636         return size;
 637 }
 638 static DEVICE_ATTR_RW(trigger_cntr);
 639
 640 static struct attribute *coresight_tmc_attrs[] = {
 641         &dev_attr_trigger_cntr.attr,
 642         NULL,
 643 };
 644
 645 static const struct attribute_group coresight_tmc_group = {
 646         .attrs = coresight_tmc_attrs,
 647 };
 648
 649 static const struct attribute_group coresight_tmc_mgmt_group = {
 650         .attrs = coresight_tmc_mgmt_attrs,
 651         .name = "mgmt",
 652 };
 653
 654 const struct attribute_group *coresight_tmc_groups[] = {
 655         &coresight_tmc_group,
 656         &coresight_tmc_mgmt_group,
 657         NULL,
 658 };
 659
 660 static int tmc_probe(struct amba_device *adev, const struct amba_id *id)
 661 {
 662         int ret = 0;
 663         u32 devid;
 664         void __iomem *base;
 665         struct device *dev = &adev->dev;
 666         struct coresight_platform_data *pdata = NULL;
 667         struct tmc_drvdata *drvdata;
 668         struct resource *res = &adev->res;
 669         struct coresight_desc *desc;
 670         struct device_node *np = adev->dev.of_node;
 671
 672         if (np) {
 673                 pdata = of_get_coresight_platform_data(dev, np);
 674                 if (IS_ERR(pdata))
 675                         return PTR_ERR(pdata);
 676                 adev->dev.platform_data = pdata;
 677         }
 678
 679         drvdata = devm_kzalloc(dev, sizeof(*drvdata), GFP_KERNEL);
 680         if (!drvdata)
 681                 return -ENOMEM;
 682
 683         drvdata->dev = &adev->dev;
 684         dev_set_drvdata(dev, drvdata);
 685
 686         /* Validity for the resource is already checked by the AMBA core */
 687         base = devm_ioremap_resource(dev, res);
 688         if (IS_ERR(base))
 689                 return PTR_ERR(base);
 690
 691         drvdata->base = base;
 692
 693         spin_lock_init(&drvdata->spinlock);
 694
 695         devid = readl_relaxed(drvdata->base + CORESIGHT_DEVID);
 696         drvdata->config_type = BMVAL(devid, 6, 7);
 697
 698         if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
 699                 if (np)
 700                         ret = of_property_read_u32(np,
 701                                                    "arm,buffer-size",
 702                                                    &drvdata->size);
 703                 if (ret)
 704                         drvdata->size = SZ_1M;
 705         } else {
 706                 drvdata->size = readl_relaxed(drvdata->base + TMC_RSZ) * 4;
 707         }
 708
 709         pm_runtime_put(&adev->dev);
 710
 711         if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
 712                 drvdata->vaddr = dma_alloc_coherent(dev, drvdata->size,
 713                                                 &drvdata->paddr, GFP_KERNEL);
 714                 if (!drvdata->vaddr)
 715                         return -ENOMEM;
 716
 717                 memset(drvdata->vaddr, 0, drvdata->size);
 718                 drvdata->buf = drvdata->vaddr;
 719         } else {
 720                 drvdata->buf = devm_kzalloc(dev, drvdata->size, GFP_KERNEL);
 721                 if (!drvdata->buf)
 722                         return -ENOMEM;
 723         }
 724
 725         desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL);
 726         if (!desc) {
 727                 ret = -ENOMEM;
 728                 goto err_devm_kzalloc;
 729         }
 730
 731         desc->pdata = pdata;
 732         desc->dev = dev;
 733         desc->subtype.sink_subtype = CORESIGHT_DEV_SUBTYPE_SINK_BUFFER;
 734         desc->groups = coresight_tmc_groups;
 735
 736         if (drvdata->config_type == TMC_CONFIG_TYPE_ETB) {
 737                 desc->type = CORESIGHT_DEV_TYPE_SINK;
 738                 desc->ops = &tmc_etb_cs_ops;
 739         } else if (drvdata->config_type == TMC_CONFIG_TYPE_ETR) {
 740                 desc->type = CORESIGHT_DEV_TYPE_SINK;
 741                 desc->ops = &tmc_etr_cs_ops;
 742         } else {
 743                 desc->type = CORESIGHT_DEV_TYPE_LINKSINK;
 744                 desc->subtype.link_subtype = CORESIGHT_DEV_SUBTYPE_LINK_FIFO;
 745                 desc->ops = &tmc_etf_cs_ops;
 746         }
 747
 748         drvdata->csdev = coresight_register(desc);
 749         if (IS_ERR(drvdata->csdev)) {
 750                 ret = PTR_ERR(drvdata->csdev);
 751                 goto err_devm_kzalloc;
 752         }
 753
 754         drvdata->miscdev.name = pdata->name;
 755         drvdata->miscdev.minor = MISC_DYNAMIC_MINOR;
 756         drvdata->miscdev.fops = &tmc_fops;
 757         ret = misc_register(&drvdata->miscdev);
 758         if (ret)
 759                 goto err_misc_register;
 760
 761         return 0;
 762
 763 err_misc_register:
 764         coresight_unregister(drvdata->csdev);
 765 err_devm_kzalloc:
 766         if (drvdata->config_type == TMC_CONFIG_TYPE_ETR)
 767                 dma_free_coherent(dev, drvdata->size,
 768                                 drvdata->vaddr, drvdata->paddr);
 769         return ret;
 770 }
 771
 772 static struct amba_id tmc_ids[] = {
 773         {
 774                 .id     = 0x0003b961,
 775                 .mask   = 0x0003ffff,
 776         },
 777         { 0, 0},
 778 };
 779
 780 static struct amba_driver tmc_driver = {
 781         .drv = {
 782                 .name   = "coresight-tmc",
 783                 .owner  = THIS_MODULE,
 784                 .suppress_bind_attrs = true,
 785         },
 786         .probe          = tmc_probe,
 787         .id_table       = tmc_ids,
 788 };
 789 builtin_amba_driver(tmc_driver);