2 * i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
4 * Copyright (C) 2011 Weinmann Medical GmbH
5 * Author: Nikolaus Voss <n.voss@weinmann.de>
7 * Evolved from original work by:
8 * Copyright (C) 2004 Rick Bronson
9 * Converted to 2.6 by Andrew Victor <andrew@sanpeople.com>
11 * Borrowed heavily from original work by:
12 * Copyright (C) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
20 #include <linux/clk.h>
21 #include <linux/completion.h>
22 #include <linux/dma-mapping.h>
23 #include <linux/dmaengine.h>
24 #include <linux/err.h>
25 #include <linux/i2c.h>
26 #include <linux/interrupt.h>
28 #include <linux/module.h>
30 #include <linux/of_device.h>
31 #include <linux/platform_device.h>
32 #include <linux/slab.h>
33 #include <linux/platform_data/dma-atmel.h>
34 #include <linux/pm_runtime.h>
35 #include <linux/pinctrl/consumer.h>
37 #define DEFAULT_TWI_CLK_HZ 100000 /* max 400 Kbits/s */
38 #define AT91_I2C_TIMEOUT msecs_to_jiffies(100) /* transfer timeout */
39 #define AT91_I2C_DMA_THRESHOLD 8 /* enable DMA if transfer size is bigger than this threshold */
40 #define AUTOSUSPEND_TIMEOUT 2000
42 /* AT91 TWI register definitions */
43 #define AT91_TWI_CR 0x0000 /* Control Register */
44 #define AT91_TWI_START BIT(0) /* Send a Start Condition */
45 #define AT91_TWI_STOP BIT(1) /* Send a Stop Condition */
46 #define AT91_TWI_MSEN BIT(2) /* Master Transfer Enable */
47 #define AT91_TWI_MSDIS BIT(3) /* Master Transfer Disable */
48 #define AT91_TWI_SVEN BIT(4) /* Slave Transfer Enable */
49 #define AT91_TWI_SVDIS BIT(5) /* Slave Transfer Disable */
50 #define AT91_TWI_QUICK BIT(6) /* SMBus quick command */
51 #define AT91_TWI_SWRST BIT(7) /* Software Reset */
52 #define AT91_TWI_ACMEN BIT(16) /* Alternative Command Mode Enable */
53 #define AT91_TWI_ACMDIS BIT(17) /* Alternative Command Mode Disable */
54 #define AT91_TWI_THRCLR BIT(24) /* Transmit Holding Register Clear */
55 #define AT91_TWI_RHRCLR BIT(25) /* Receive Holding Register Clear */
56 #define AT91_TWI_LOCKCLR BIT(26) /* Lock Clear */
57 #define AT91_TWI_FIFOEN BIT(28) /* FIFO Enable */
58 #define AT91_TWI_FIFODIS BIT(29) /* FIFO Disable */
60 #define AT91_TWI_MMR 0x0004 /* Master Mode Register */
61 #define AT91_TWI_IADRSZ_1 0x0100 /* Internal Device Address Size */
62 #define AT91_TWI_MREAD BIT(12) /* Master Read Direction */
64 #define AT91_TWI_IADR 0x000c /* Internal Address Register */
66 #define AT91_TWI_CWGR 0x0010 /* Clock Waveform Generator Reg */
68 #define AT91_TWI_SR 0x0020 /* Status Register */
69 #define AT91_TWI_TXCOMP BIT(0) /* Transmission Complete */
70 #define AT91_TWI_RXRDY BIT(1) /* Receive Holding Register Ready */
71 #define AT91_TWI_TXRDY BIT(2) /* Transmit Holding Register Ready */
72 #define AT91_TWI_OVRE BIT(6) /* Overrun Error */
73 #define AT91_TWI_UNRE BIT(7) /* Underrun Error */
74 #define AT91_TWI_NACK BIT(8) /* Not Acknowledged */
75 #define AT91_TWI_LOCK BIT(23) /* TWI Lock due to Frame Errors */
77 #define AT91_TWI_INT_MASK \
78 (AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY | AT91_TWI_NACK)
80 #define AT91_TWI_IER 0x0024 /* Interrupt Enable Register */
81 #define AT91_TWI_IDR 0x0028 /* Interrupt Disable Register */
82 #define AT91_TWI_IMR 0x002c /* Interrupt Mask Register */
83 #define AT91_TWI_RHR 0x0030 /* Receive Holding Register */
84 #define AT91_TWI_THR 0x0034 /* Transmit Holding Register */
86 #define AT91_TWI_ACR 0x0040 /* Alternative Command Register */
87 #define AT91_TWI_ACR_DATAL(len) ((len) & 0xff)
88 #define AT91_TWI_ACR_DIR BIT(8)
90 #define AT91_TWI_FMR 0x0050 /* FIFO Mode Register */
91 #define AT91_TWI_FMR_TXRDYM(mode) (((mode) & 0x3) << 0)
92 #define AT91_TWI_FMR_TXRDYM_MASK (0x3 << 0)
93 #define AT91_TWI_FMR_RXRDYM(mode) (((mode) & 0x3) << 4)
94 #define AT91_TWI_FMR_RXRDYM_MASK (0x3 << 4)
95 #define AT91_TWI_ONE_DATA 0x0
96 #define AT91_TWI_TWO_DATA 0x1
97 #define AT91_TWI_FOUR_DATA 0x2
99 #define AT91_TWI_FLR 0x0054 /* FIFO Level Register */
101 #define AT91_TWI_FSR 0x0060 /* FIFO Status Register */
102 #define AT91_TWI_FIER 0x0064 /* FIFO Interrupt Enable Register */
103 #define AT91_TWI_FIDR 0x0068 /* FIFO Interrupt Disable Register */
104 #define AT91_TWI_FIMR 0x006c /* FIFO Interrupt Mask Register */
106 #define AT91_TWI_VER 0x00fc /* Version Register */
108 struct at91_twi_pdata {
109 unsigned clk_max_div;
113 struct at_dma_slave dma_slave;
116 struct at91_twi_dma {
117 struct dma_chan *chan_rx;
118 struct dma_chan *chan_tx;
119 struct scatterlist sg[2];
120 struct dma_async_tx_descriptor *data_desc;
121 enum dma_data_direction direction;
123 bool xfer_in_progress;
126 struct at91_twi_dev {
129 struct completion cmd_complete;
136 unsigned transfer_status;
137 struct i2c_adapter adapter;
138 unsigned twi_cwgr_reg;
139 struct at91_twi_pdata *pdata;
143 struct at91_twi_dma dma;
146 static unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg)
148 return readl_relaxed(dev->base + reg);
151 static void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val)
153 writel_relaxed(val, dev->base + reg);
156 static void at91_disable_twi_interrupts(struct at91_twi_dev *dev)
158 at91_twi_write(dev, AT91_TWI_IDR, AT91_TWI_INT_MASK);
161 static void at91_twi_irq_save(struct at91_twi_dev *dev)
163 dev->imr = at91_twi_read(dev, AT91_TWI_IMR) & AT91_TWI_INT_MASK;
164 at91_disable_twi_interrupts(dev);
167 static void at91_twi_irq_restore(struct at91_twi_dev *dev)
169 at91_twi_write(dev, AT91_TWI_IER, dev->imr);
172 static void at91_init_twi_bus(struct at91_twi_dev *dev)
174 at91_disable_twi_interrupts(dev);
175 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SWRST);
176 /* FIFO should be enabled immediately after the software reset */
178 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_FIFOEN);
179 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_MSEN);
180 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SVDIS);
181 at91_twi_write(dev, AT91_TWI_CWGR, dev->twi_cwgr_reg);
185 * Calculate symmetric clock as stated in datasheet:
186 * twi_clk = F_MAIN / (2 * (cdiv * (1 << ckdiv) + offset))
188 static void at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
190 int ckdiv, cdiv, div;
191 struct at91_twi_pdata *pdata = dev->pdata;
192 int offset = pdata->clk_offset;
193 int max_ckdiv = pdata->clk_max_div;
195 div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
196 2 * twi_clk) - offset);
197 ckdiv = fls(div >> 8);
200 if (ckdiv > max_ckdiv) {
201 dev_warn(dev->dev, "%d exceeds ckdiv max value which is %d.\n",
207 dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv;
208 dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv);
211 static void at91_twi_dma_cleanup(struct at91_twi_dev *dev)
213 struct at91_twi_dma *dma = &dev->dma;
215 at91_twi_irq_save(dev);
217 if (dma->xfer_in_progress) {
218 if (dma->direction == DMA_FROM_DEVICE)
219 dmaengine_terminate_all(dma->chan_rx);
221 dmaengine_terminate_all(dma->chan_tx);
222 dma->xfer_in_progress = false;
224 if (dma->buf_mapped) {
225 dma_unmap_single(dev->dev, sg_dma_address(&dma->sg[0]),
226 dev->buf_len, dma->direction);
227 dma->buf_mapped = false;
230 at91_twi_irq_restore(dev);
233 static void at91_twi_write_next_byte(struct at91_twi_dev *dev)
238 /* 8bit write works with and without FIFO */
239 writeb_relaxed(*dev->buf, dev->base + AT91_TWI_THR);
241 /* send stop when last byte has been written */
242 if (--dev->buf_len == 0)
243 if (!dev->pdata->has_alt_cmd)
244 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
246 dev_dbg(dev->dev, "wrote 0x%x, to go %d\n", *dev->buf, dev->buf_len);
251 static void at91_twi_write_data_dma_callback(void *data)
253 struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
255 dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg[0]),
256 dev->buf_len, DMA_TO_DEVICE);
259 * When this callback is called, THR/TX FIFO is likely not to be empty
260 * yet. So we have to wait for TXCOMP or NACK bits to be set into the
261 * Status Register to be sure that the STOP bit has been sent and the
262 * transfer is completed. The NACK interrupt has already been enabled,
263 * we just have to enable TXCOMP one.
265 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
266 if (!dev->pdata->has_alt_cmd)
267 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
270 static void at91_twi_write_data_dma(struct at91_twi_dev *dev)
273 struct dma_async_tx_descriptor *txdesc;
274 struct at91_twi_dma *dma = &dev->dma;
275 struct dma_chan *chan_tx = dma->chan_tx;
276 unsigned int sg_len = 1;
281 dma->direction = DMA_TO_DEVICE;
283 at91_twi_irq_save(dev);
284 dma_addr = dma_map_single(dev->dev, dev->buf, dev->buf_len,
286 if (dma_mapping_error(dev->dev, dma_addr)) {
287 dev_err(dev->dev, "dma map failed\n");
290 dma->buf_mapped = true;
291 at91_twi_irq_restore(dev);
293 if (dev->fifo_size) {
294 size_t part1_len, part2_len;
295 struct scatterlist *sg;
300 part1_len = dev->buf_len & ~0x3;
302 sg = &dma->sg[sg_len++];
303 sg_dma_len(sg) = part1_len;
304 sg_dma_address(sg) = dma_addr;
307 part2_len = dev->buf_len & 0x3;
309 sg = &dma->sg[sg_len++];
310 sg_dma_len(sg) = part2_len;
311 sg_dma_address(sg) = dma_addr + part1_len;
315 * DMA controller is triggered when at least 4 data can be
316 * written into the TX FIFO
318 fifo_mr = at91_twi_read(dev, AT91_TWI_FMR);
319 fifo_mr &= ~AT91_TWI_FMR_TXRDYM_MASK;
320 fifo_mr |= AT91_TWI_FMR_TXRDYM(AT91_TWI_FOUR_DATA);
321 at91_twi_write(dev, AT91_TWI_FMR, fifo_mr);
323 sg_dma_len(&dma->sg[0]) = dev->buf_len;
324 sg_dma_address(&dma->sg[0]) = dma_addr;
327 txdesc = dmaengine_prep_slave_sg(chan_tx, dma->sg, sg_len,
329 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
331 dev_err(dev->dev, "dma prep slave sg failed\n");
335 txdesc->callback = at91_twi_write_data_dma_callback;
336 txdesc->callback_param = dev;
338 dma->xfer_in_progress = true;
339 dmaengine_submit(txdesc);
340 dma_async_issue_pending(chan_tx);
345 at91_twi_dma_cleanup(dev);
348 static void at91_twi_read_next_byte(struct at91_twi_dev *dev)
353 /* 8bit read works with and without FIFO */
354 *dev->buf = readb_relaxed(dev->base + AT91_TWI_RHR);
357 /* return if aborting, we only needed to read RHR to clear RXRDY*/
358 if (dev->recv_len_abort)
361 /* handle I2C_SMBUS_BLOCK_DATA */
362 if (unlikely(dev->msg->flags & I2C_M_RECV_LEN)) {
363 /* ensure length byte is a valid value */
364 if (*dev->buf <= I2C_SMBUS_BLOCK_MAX && *dev->buf > 0) {
365 dev->msg->flags &= ~I2C_M_RECV_LEN;
366 dev->buf_len += *dev->buf;
367 dev->msg->len = dev->buf_len + 1;
368 dev_dbg(dev->dev, "received block length %d\n",
371 /* abort and send the stop by reading one more byte */
372 dev->recv_len_abort = true;
377 /* send stop if second but last byte has been read */
378 if (!dev->pdata->has_alt_cmd && dev->buf_len == 1)
379 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
381 dev_dbg(dev->dev, "read 0x%x, to go %d\n", *dev->buf, dev->buf_len);
386 static void at91_twi_read_data_dma_callback(void *data)
388 struct at91_twi_dev *dev = (struct at91_twi_dev *)data;
389 unsigned ier = AT91_TWI_TXCOMP;
391 dma_unmap_single(dev->dev, sg_dma_address(&dev->dma.sg[0]),
392 dev->buf_len, DMA_FROM_DEVICE);
394 if (!dev->pdata->has_alt_cmd) {
395 /* The last two bytes have to be read without using dma */
396 dev->buf += dev->buf_len - 2;
398 ier |= AT91_TWI_RXRDY;
400 at91_twi_write(dev, AT91_TWI_IER, ier);
403 static void at91_twi_read_data_dma(struct at91_twi_dev *dev)
406 struct dma_async_tx_descriptor *rxdesc;
407 struct at91_twi_dma *dma = &dev->dma;
408 struct dma_chan *chan_rx = dma->chan_rx;
411 buf_len = (dev->pdata->has_alt_cmd) ? dev->buf_len : dev->buf_len - 2;
412 dma->direction = DMA_FROM_DEVICE;
414 /* Keep in mind that we won't use dma to read the last two bytes */
415 at91_twi_irq_save(dev);
416 dma_addr = dma_map_single(dev->dev, dev->buf, buf_len, DMA_FROM_DEVICE);
417 if (dma_mapping_error(dev->dev, dma_addr)) {
418 dev_err(dev->dev, "dma map failed\n");
421 dma->buf_mapped = true;
422 at91_twi_irq_restore(dev);
424 if (dev->fifo_size && IS_ALIGNED(buf_len, 4)) {
428 * DMA controller is triggered when at least 4 data can be
429 * read from the RX FIFO
431 fifo_mr = at91_twi_read(dev, AT91_TWI_FMR);
432 fifo_mr &= ~AT91_TWI_FMR_RXRDYM_MASK;
433 fifo_mr |= AT91_TWI_FMR_RXRDYM(AT91_TWI_FOUR_DATA);
434 at91_twi_write(dev, AT91_TWI_FMR, fifo_mr);
437 sg_dma_len(&dma->sg[0]) = buf_len;
438 sg_dma_address(&dma->sg[0]) = dma_addr;
440 rxdesc = dmaengine_prep_slave_sg(chan_rx, dma->sg, 1, DMA_DEV_TO_MEM,
441 DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
443 dev_err(dev->dev, "dma prep slave sg failed\n");
447 rxdesc->callback = at91_twi_read_data_dma_callback;
448 rxdesc->callback_param = dev;
450 dma->xfer_in_progress = true;
451 dmaengine_submit(rxdesc);
452 dma_async_issue_pending(dma->chan_rx);
457 at91_twi_dma_cleanup(dev);
460 static irqreturn_t atmel_twi_interrupt(int irq, void *dev_id)
462 struct at91_twi_dev *dev = dev_id;
463 const unsigned status = at91_twi_read(dev, AT91_TWI_SR);
464 const unsigned irqstatus = status & at91_twi_read(dev, AT91_TWI_IMR);
468 else if (irqstatus & AT91_TWI_RXRDY)
469 at91_twi_read_next_byte(dev);
470 else if (irqstatus & AT91_TWI_TXRDY)
471 at91_twi_write_next_byte(dev);
473 /* catch error flags */
474 dev->transfer_status |= status;
476 if (irqstatus & (AT91_TWI_TXCOMP | AT91_TWI_NACK)) {
477 at91_disable_twi_interrupts(dev);
478 complete(&dev->cmd_complete);
484 static int at91_do_twi_transfer(struct at91_twi_dev *dev)
487 unsigned long time_left;
488 bool has_unre_flag = dev->pdata->has_unre_flag;
489 bool has_alt_cmd = dev->pdata->has_alt_cmd;
492 * WARNING: the TXCOMP bit in the Status Register is NOT a clear on
493 * read flag but shows the state of the transmission at the time the
494 * Status Register is read. According to the programmer datasheet,
495 * TXCOMP is set when both holding register and internal shifter are
496 * empty and STOP condition has been sent.
497 * Consequently, we should enable NACK interrupt rather than TXCOMP to
498 * detect transmission failure.
499 * Indeed let's take the case of an i2c write command using DMA.
500 * Whenever the slave doesn't acknowledge a byte, the LOCK, NACK and
501 * TXCOMP bits are set together into the Status Register.
502 * LOCK is a clear on write bit, which is set to prevent the DMA
503 * controller from sending new data on the i2c bus after a NACK
504 * condition has happened. Once locked, this i2c peripheral stops
505 * triggering the DMA controller for new data but it is more than
506 * likely that a new DMA transaction is already in progress, writing
507 * into the Transmit Holding Register. Since the peripheral is locked,
508 * these new data won't be sent to the i2c bus but they will remain
509 * into the Transmit Holding Register, so TXCOMP bit is cleared.
510 * Then when the interrupt handler is called, the Status Register is
511 * read: the TXCOMP bit is clear but NACK bit is still set. The driver
512 * manage the error properly, without waiting for timeout.
513 * This case can be reproduced easyly when writing into an at24 eeprom.
515 * Besides, the TXCOMP bit is already set before the i2c transaction
516 * has been started. For read transactions, this bit is cleared when
517 * writing the START bit into the Control Register. So the
518 * corresponding interrupt can safely be enabled just after.
519 * However for write transactions managed by the CPU, we first write
520 * into THR, so TXCOMP is cleared. Then we can safely enable TXCOMP
521 * interrupt. If TXCOMP interrupt were enabled before writing into THR,
522 * the interrupt handler would be called immediately and the i2c command
523 * would be reported as completed.
524 * Also when a write transaction is managed by the DMA controller,
525 * enabling the TXCOMP interrupt in this function may lead to a race
526 * condition since we don't know whether the TXCOMP interrupt is enabled
527 * before or after the DMA has started to write into THR. So the TXCOMP
528 * interrupt is enabled later by at91_twi_write_data_dma_callback().
529 * Immediately after in that DMA callback, if the alternative command
530 * mode is not used, we still need to send the STOP condition manually
531 * writing the corresponding bit into the Control Register.
534 dev_dbg(dev->dev, "transfer: %s %d bytes.\n",
535 (dev->msg->flags & I2C_M_RD) ? "read" : "write", dev->buf_len);
537 reinit_completion(&dev->cmd_complete);
538 dev->transfer_status = 0;
540 if (dev->fifo_size) {
541 unsigned fifo_mr = at91_twi_read(dev, AT91_TWI_FMR);
543 /* Reset FIFO mode register */
544 fifo_mr &= ~(AT91_TWI_FMR_TXRDYM_MASK |
545 AT91_TWI_FMR_RXRDYM_MASK);
546 fifo_mr |= AT91_TWI_FMR_TXRDYM(AT91_TWI_ONE_DATA);
547 fifo_mr |= AT91_TWI_FMR_RXRDYM(AT91_TWI_ONE_DATA);
548 at91_twi_write(dev, AT91_TWI_FMR, fifo_mr);
551 at91_twi_write(dev, AT91_TWI_CR,
552 AT91_TWI_THRCLR | AT91_TWI_RHRCLR);
556 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_QUICK);
557 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
558 } else if (dev->msg->flags & I2C_M_RD) {
559 unsigned start_flags = AT91_TWI_START;
561 if (at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_RXRDY) {
562 dev_err(dev->dev, "RXRDY still set!");
563 at91_twi_read(dev, AT91_TWI_RHR);
566 /* if only one byte is to be read, immediately stop transfer */
567 if (!has_alt_cmd && dev->buf_len <= 1 &&
568 !(dev->msg->flags & I2C_M_RECV_LEN))
569 start_flags |= AT91_TWI_STOP;
570 at91_twi_write(dev, AT91_TWI_CR, start_flags);
572 * When using dma without alternative command mode, the last
573 * byte has to be read manually in order to not send the stop
574 * command too late and then to receive extra data.
575 * In practice, there are some issues if you use the dma to
576 * read n-1 bytes because of latency.
577 * Reading n-2 bytes with dma and the two last ones manually
578 * seems to be the best solution.
580 if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) {
581 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_NACK);
582 at91_twi_read_data_dma(dev);
584 at91_twi_write(dev, AT91_TWI_IER,
590 if (dev->use_dma && (dev->buf_len > AT91_I2C_DMA_THRESHOLD)) {
591 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_NACK);
592 at91_twi_write_data_dma(dev);
594 at91_twi_write_next_byte(dev);
595 at91_twi_write(dev, AT91_TWI_IER,
602 time_left = wait_for_completion_timeout(&dev->cmd_complete,
603 dev->adapter.timeout);
604 if (time_left == 0) {
605 dev->transfer_status |= at91_twi_read(dev, AT91_TWI_SR);
606 dev_err(dev->dev, "controller timed out\n");
607 at91_init_twi_bus(dev);
611 if (dev->transfer_status & AT91_TWI_NACK) {
612 dev_dbg(dev->dev, "received nack\n");
616 if (dev->transfer_status & AT91_TWI_OVRE) {
617 dev_err(dev->dev, "overrun while reading\n");
621 if (has_unre_flag && dev->transfer_status & AT91_TWI_UNRE) {
622 dev_err(dev->dev, "underrun while writing\n");
626 if ((has_alt_cmd || dev->fifo_size) &&
627 (dev->transfer_status & AT91_TWI_LOCK)) {
628 dev_err(dev->dev, "tx locked\n");
632 if (dev->recv_len_abort) {
633 dev_err(dev->dev, "invalid smbus block length recvd\n");
638 dev_dbg(dev->dev, "transfer complete\n");
643 /* first stop DMA transfer if still in progress */
644 at91_twi_dma_cleanup(dev);
645 /* then flush THR/FIFO and unlock TX if locked */
646 if ((has_alt_cmd || dev->fifo_size) &&
647 (dev->transfer_status & AT91_TWI_LOCK)) {
648 dev_dbg(dev->dev, "unlock tx\n");
649 at91_twi_write(dev, AT91_TWI_CR,
650 AT91_TWI_THRCLR | AT91_TWI_LOCKCLR);
655 static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num)
657 struct at91_twi_dev *dev = i2c_get_adapdata(adap);
659 unsigned int_addr_flag = 0;
660 struct i2c_msg *m_start = msg;
661 bool is_read, use_alt_cmd = false;
663 dev_dbg(&adap->dev, "at91_xfer: processing %d messages:\n", num);
665 ret = pm_runtime_get_sync(dev->dev);
670 int internal_address = 0;
673 /* 1st msg is put into the internal address, start with 2nd */
675 for (i = 0; i < msg->len; ++i) {
676 const unsigned addr = msg->buf[msg->len - 1 - i];
678 internal_address |= addr << (8 * i);
679 int_addr_flag += AT91_TWI_IADRSZ_1;
681 at91_twi_write(dev, AT91_TWI_IADR, internal_address);
684 is_read = (m_start->flags & I2C_M_RD);
685 if (dev->pdata->has_alt_cmd) {
686 if (m_start->len > 0) {
687 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_ACMEN);
688 at91_twi_write(dev, AT91_TWI_ACR,
689 AT91_TWI_ACR_DATAL(m_start->len) |
690 ((is_read) ? AT91_TWI_ACR_DIR : 0));
693 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_ACMDIS);
697 at91_twi_write(dev, AT91_TWI_MMR,
698 (m_start->addr << 16) |
700 ((!use_alt_cmd && is_read) ? AT91_TWI_MREAD : 0));
702 dev->buf_len = m_start->len;
703 dev->buf = m_start->buf;
705 dev->recv_len_abort = false;
707 ret = at91_do_twi_transfer(dev);
709 ret = (ret < 0) ? ret : num;
711 pm_runtime_mark_last_busy(dev->dev);
712 pm_runtime_put_autosuspend(dev->dev);
718 * The hardware can handle at most two messages concatenated by a
719 * repeated start via it's internal address feature.
721 static struct i2c_adapter_quirks at91_twi_quirks = {
722 .flags = I2C_AQ_COMB | I2C_AQ_COMB_WRITE_FIRST | I2C_AQ_COMB_SAME_ADDR,
723 .max_comb_1st_msg_len = 3,
726 static u32 at91_twi_func(struct i2c_adapter *adapter)
728 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
729 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
732 static struct i2c_algorithm at91_twi_algorithm = {
733 .master_xfer = at91_twi_xfer,
734 .functionality = at91_twi_func,
737 static struct at91_twi_pdata at91rm9200_config = {
740 .has_unre_flag = true,
741 .has_alt_cmd = false,
744 static struct at91_twi_pdata at91sam9261_config = {
747 .has_unre_flag = false,
748 .has_alt_cmd = false,
751 static struct at91_twi_pdata at91sam9260_config = {
754 .has_unre_flag = false,
755 .has_alt_cmd = false,
758 static struct at91_twi_pdata at91sam9g20_config = {
761 .has_unre_flag = false,
762 .has_alt_cmd = false,
765 static struct at91_twi_pdata at91sam9g10_config = {
768 .has_unre_flag = false,
769 .has_alt_cmd = false,
772 static const struct platform_device_id at91_twi_devtypes[] = {
774 .name = "i2c-at91rm9200",
775 .driver_data = (unsigned long) &at91rm9200_config,
777 .name = "i2c-at91sam9261",
778 .driver_data = (unsigned long) &at91sam9261_config,
780 .name = "i2c-at91sam9260",
781 .driver_data = (unsigned long) &at91sam9260_config,
783 .name = "i2c-at91sam9g20",
784 .driver_data = (unsigned long) &at91sam9g20_config,
786 .name = "i2c-at91sam9g10",
787 .driver_data = (unsigned long) &at91sam9g10_config,
793 #if defined(CONFIG_OF)
794 static struct at91_twi_pdata at91sam9x5_config = {
797 .has_unre_flag = false,
798 .has_alt_cmd = false,
801 static struct at91_twi_pdata sama5d2_config = {
804 .has_unre_flag = true,
808 static const struct of_device_id atmel_twi_dt_ids[] = {
810 .compatible = "atmel,at91rm9200-i2c",
811 .data = &at91rm9200_config,
813 .compatible = "atmel,at91sam9260-i2c",
814 .data = &at91sam9260_config,
816 .compatible = "atmel,at91sam9261-i2c",
817 .data = &at91sam9261_config,
819 .compatible = "atmel,at91sam9g20-i2c",
820 .data = &at91sam9g20_config,
822 .compatible = "atmel,at91sam9g10-i2c",
823 .data = &at91sam9g10_config,
825 .compatible = "atmel,at91sam9x5-i2c",
826 .data = &at91sam9x5_config,
828 .compatible = "atmel,sama5d2-i2c",
829 .data = &sama5d2_config,
834 MODULE_DEVICE_TABLE(of, atmel_twi_dt_ids);
837 static int at91_twi_configure_dma(struct at91_twi_dev *dev, u32 phy_addr)
840 struct dma_slave_config slave_config;
841 struct at91_twi_dma *dma = &dev->dma;
842 enum dma_slave_buswidth addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE;
845 * The actual width of the access will be chosen in
846 * dmaengine_prep_slave_sg():
847 * for each buffer in the scatter-gather list, if its size is aligned
848 * to addr_width then addr_width accesses will be performed to transfer
849 * the buffer. On the other hand, if the buffer size is not aligned to
850 * addr_width then the buffer is transferred using single byte accesses.
851 * Please refer to the Atmel eXtended DMA controller driver.
852 * When FIFOs are used, the TXRDYM threshold can always be set to
853 * trigger the XDMAC when at least 4 data can be written into the TX
854 * FIFO, even if single byte accesses are performed.
855 * However the RXRDYM threshold must be set to fit the access width,
856 * deduced from buffer length, so the XDMAC is triggered properly to
857 * read data from the RX FIFO.
860 addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
862 memset(&slave_config, 0, sizeof(slave_config));
863 slave_config.src_addr = (dma_addr_t)phy_addr + AT91_TWI_RHR;
864 slave_config.src_addr_width = addr_width;
865 slave_config.src_maxburst = 1;
866 slave_config.dst_addr = (dma_addr_t)phy_addr + AT91_TWI_THR;
867 slave_config.dst_addr_width = addr_width;
868 slave_config.dst_maxburst = 1;
869 slave_config.device_fc = false;
871 dma->chan_tx = dma_request_slave_channel_reason(dev->dev, "tx");
872 if (IS_ERR(dma->chan_tx)) {
873 ret = PTR_ERR(dma->chan_tx);
878 dma->chan_rx = dma_request_slave_channel_reason(dev->dev, "rx");
879 if (IS_ERR(dma->chan_rx)) {
880 ret = PTR_ERR(dma->chan_rx);
885 slave_config.direction = DMA_MEM_TO_DEV;
886 if (dmaengine_slave_config(dma->chan_tx, &slave_config)) {
887 dev_err(dev->dev, "failed to configure tx channel\n");
892 slave_config.direction = DMA_DEV_TO_MEM;
893 if (dmaengine_slave_config(dma->chan_rx, &slave_config)) {
894 dev_err(dev->dev, "failed to configure rx channel\n");
899 sg_init_table(dma->sg, 2);
900 dma->buf_mapped = false;
901 dma->xfer_in_progress = false;
904 dev_info(dev->dev, "using %s (tx) and %s (rx) for DMA transfers\n",
905 dma_chan_name(dma->chan_tx), dma_chan_name(dma->chan_rx));
910 if (ret != -EPROBE_DEFER)
911 dev_info(dev->dev, "can't use DMA, error %d\n", ret);
913 dma_release_channel(dma->chan_rx);
915 dma_release_channel(dma->chan_tx);
919 static struct at91_twi_pdata *at91_twi_get_driver_data(
920 struct platform_device *pdev)
922 if (pdev->dev.of_node) {
923 const struct of_device_id *match;
924 match = of_match_node(atmel_twi_dt_ids, pdev->dev.of_node);
927 return (struct at91_twi_pdata *)match->data;
929 return (struct at91_twi_pdata *) platform_get_device_id(pdev)->driver_data;
932 static int at91_twi_probe(struct platform_device *pdev)
934 struct at91_twi_dev *dev;
935 struct resource *mem;
940 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
943 init_completion(&dev->cmd_complete);
944 dev->dev = &pdev->dev;
946 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
949 phy_addr = mem->start;
951 dev->pdata = at91_twi_get_driver_data(pdev);
955 dev->base = devm_ioremap_resource(&pdev->dev, mem);
956 if (IS_ERR(dev->base))
957 return PTR_ERR(dev->base);
959 dev->irq = platform_get_irq(pdev, 0);
963 rc = devm_request_irq(&pdev->dev, dev->irq, atmel_twi_interrupt, 0,
964 dev_name(dev->dev), dev);
966 dev_err(dev->dev, "Cannot get irq %d: %d\n", dev->irq, rc);
970 platform_set_drvdata(pdev, dev);
972 dev->clk = devm_clk_get(dev->dev, NULL);
973 if (IS_ERR(dev->clk)) {
974 dev_err(dev->dev, "no clock defined\n");
977 clk_prepare_enable(dev->clk);
979 if (dev->dev->of_node) {
980 rc = at91_twi_configure_dma(dev, phy_addr);
981 if (rc == -EPROBE_DEFER)
985 if (!of_property_read_u32(pdev->dev.of_node, "atmel,fifo-size",
987 dev_info(dev->dev, "Using FIFO (%u data)\n", dev->fifo_size);
990 rc = of_property_read_u32(dev->dev->of_node, "clock-frequency",
993 bus_clk_rate = DEFAULT_TWI_CLK_HZ;
995 at91_calc_twi_clock(dev, bus_clk_rate);
996 at91_init_twi_bus(dev);
998 snprintf(dev->adapter.name, sizeof(dev->adapter.name), "AT91");
999 i2c_set_adapdata(&dev->adapter, dev);
1000 dev->adapter.owner = THIS_MODULE;
1001 dev->adapter.class = I2C_CLASS_DEPRECATED;
1002 dev->adapter.algo = &at91_twi_algorithm;
1003 dev->adapter.quirks = &at91_twi_quirks;
1004 dev->adapter.dev.parent = dev->dev;
1005 dev->adapter.nr = pdev->id;
1006 dev->adapter.timeout = AT91_I2C_TIMEOUT;
1007 dev->adapter.dev.of_node = pdev->dev.of_node;
1009 pm_runtime_set_autosuspend_delay(dev->dev, AUTOSUSPEND_TIMEOUT);
1010 pm_runtime_use_autosuspend(dev->dev);
1011 pm_runtime_set_active(dev->dev);
1012 pm_runtime_enable(dev->dev);
1014 rc = i2c_add_numbered_adapter(&dev->adapter);
1016 dev_err(dev->dev, "Adapter %s registration failed\n",
1018 clk_disable_unprepare(dev->clk);
1020 pm_runtime_disable(dev->dev);
1021 pm_runtime_set_suspended(dev->dev);
1026 dev_info(dev->dev, "AT91 i2c bus driver (hw version: %#x).\n",
1027 at91_twi_read(dev, AT91_TWI_VER));
1031 static int at91_twi_remove(struct platform_device *pdev)
1033 struct at91_twi_dev *dev = platform_get_drvdata(pdev);
1035 i2c_del_adapter(&dev->adapter);
1036 clk_disable_unprepare(dev->clk);
1038 pm_runtime_disable(dev->dev);
1039 pm_runtime_set_suspended(dev->dev);
1046 static int at91_twi_runtime_suspend(struct device *dev)
1048 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
1050 clk_disable_unprepare(twi_dev->clk);
1052 pinctrl_pm_select_sleep_state(dev);
1057 static int at91_twi_runtime_resume(struct device *dev)
1059 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
1061 pinctrl_pm_select_default_state(dev);
1063 return clk_prepare_enable(twi_dev->clk);
1066 static int at91_twi_suspend_noirq(struct device *dev)
1068 if (!pm_runtime_status_suspended(dev))
1069 at91_twi_runtime_suspend(dev);
1074 static int at91_twi_resume_noirq(struct device *dev)
1078 if (!pm_runtime_status_suspended(dev)) {
1079 ret = at91_twi_runtime_resume(dev);
1084 pm_runtime_mark_last_busy(dev);
1085 pm_request_autosuspend(dev);
1090 static const struct dev_pm_ops at91_twi_pm = {
1091 .suspend_noirq = at91_twi_suspend_noirq,
1092 .resume_noirq = at91_twi_resume_noirq,
1093 .runtime_suspend = at91_twi_runtime_suspend,
1094 .runtime_resume = at91_twi_runtime_resume,
1097 #define at91_twi_pm_ops (&at91_twi_pm)
1099 #define at91_twi_pm_ops NULL
1102 static struct platform_driver at91_twi_driver = {
1103 .probe = at91_twi_probe,
1104 .remove = at91_twi_remove,
1105 .id_table = at91_twi_devtypes,
1108 .of_match_table = of_match_ptr(atmel_twi_dt_ids),
1109 .pm = at91_twi_pm_ops,
1113 static int __init at91_twi_init(void)
1115 return platform_driver_register(&at91_twi_driver);
1118 static void __exit at91_twi_exit(void)
1120 platform_driver_unregister(&at91_twi_driver);
1123 subsys_initcall(at91_twi_init);
1124 module_exit(at91_twi_exit);
1126 MODULE_AUTHOR("Nikolaus Voss <n.voss@weinmann.de>");
1127 MODULE_DESCRIPTION("I2C (TWI) driver for Atmel AT91");
1128 MODULE_LICENSE("GPL");
1129 MODULE_ALIAS("platform:at91_i2c");