2 * i2c Support for Atmel's AT91 Two-Wire Interface (TWI)
4 * Copyright (C) 2011 Weinmann Medical GmbH
5 * Author: Nikolaus Voss <n.voss@weinmann.de>
7 * Evolved from original work by:
8 * Copyright (C) 2004 Rick Bronson
9 * Converted to 2.6 by Andrew Victor <andrew@sanpeople.com>
11 * Borrowed heavily from original work by:
12 * Copyright (C) 2000 Philip Edelbrock <phil@stimpy.netroedge.com>
14 * This program is free software; you can redistribute it and/or modify
15 * it under the terms of the GNU General Public License as published by
16 * the Free Software Foundation; either version 2 of the License, or
17 * (at your option) any later version.
20 #include <linux/clk.h>
21 #include <linux/completion.h>
22 #include <linux/err.h>
23 #include <linux/i2c.h>
24 #include <linux/interrupt.h>
26 #include <linux/module.h>
28 #include <linux/of_device.h>
29 #include <linux/of_i2c.h>
30 #include <linux/platform_device.h>
31 #include <linux/slab.h>
33 #define TWI_CLK_HZ 100000 /* max 400 Kbits/s */
34 #define AT91_I2C_TIMEOUT msecs_to_jiffies(100) /* transfer timeout */
36 /* AT91 TWI register definitions */
37 #define AT91_TWI_CR 0x0000 /* Control Register */
38 #define AT91_TWI_START 0x0001 /* Send a Start Condition */
39 #define AT91_TWI_STOP 0x0002 /* Send a Stop Condition */
40 #define AT91_TWI_MSEN 0x0004 /* Master Transfer Enable */
41 #define AT91_TWI_SVDIS 0x0020 /* Slave Transfer Disable */
42 #define AT91_TWI_QUICK 0x0040 /* SMBus quick command */
43 #define AT91_TWI_SWRST 0x0080 /* Software Reset */
45 #define AT91_TWI_MMR 0x0004 /* Master Mode Register */
46 #define AT91_TWI_IADRSZ_1 0x0100 /* Internal Device Address Size */
47 #define AT91_TWI_MREAD 0x1000 /* Master Read Direction */
49 #define AT91_TWI_IADR 0x000c /* Internal Address Register */
51 #define AT91_TWI_CWGR 0x0010 /* Clock Waveform Generator Reg */
53 #define AT91_TWI_SR 0x0020 /* Status Register */
54 #define AT91_TWI_TXCOMP 0x0001 /* Transmission Complete */
55 #define AT91_TWI_RXRDY 0x0002 /* Receive Holding Register Ready */
56 #define AT91_TWI_TXRDY 0x0004 /* Transmit Holding Register Ready */
58 #define AT91_TWI_OVRE 0x0040 /* Overrun Error */
59 #define AT91_TWI_UNRE 0x0080 /* Underrun Error */
60 #define AT91_TWI_NACK 0x0100 /* Not Acknowledged */
62 #define AT91_TWI_IER 0x0024 /* Interrupt Enable Register */
63 #define AT91_TWI_IDR 0x0028 /* Interrupt Disable Register */
64 #define AT91_TWI_IMR 0x002c /* Interrupt Mask Register */
65 #define AT91_TWI_RHR 0x0030 /* Receive Holding Register */
66 #define AT91_TWI_THR 0x0034 /* Transmit Holding Register */
68 struct at91_twi_pdata {
77 struct completion cmd_complete;
83 unsigned transfer_status;
84 struct i2c_adapter adapter;
85 unsigned twi_cwgr_reg;
86 struct at91_twi_pdata *pdata;
89 static unsigned at91_twi_read(struct at91_twi_dev *dev, unsigned reg)
91 return readl_relaxed(dev->base + reg);
94 static void at91_twi_write(struct at91_twi_dev *dev, unsigned reg, unsigned val)
96 writel_relaxed(val, dev->base + reg);
99 static void at91_disable_twi_interrupts(struct at91_twi_dev *dev)
101 at91_twi_write(dev, AT91_TWI_IDR,
102 AT91_TWI_TXCOMP | AT91_TWI_RXRDY | AT91_TWI_TXRDY);
105 static void at91_init_twi_bus(struct at91_twi_dev *dev)
107 at91_disable_twi_interrupts(dev);
108 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SWRST);
109 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_MSEN);
110 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_SVDIS);
111 at91_twi_write(dev, AT91_TWI_CWGR, dev->twi_cwgr_reg);
115 * Calculate symmetric clock as stated in datasheet:
116 * twi_clk = F_MAIN / (2 * (cdiv * (1 << ckdiv) + offset))
118 static void __devinit at91_calc_twi_clock(struct at91_twi_dev *dev, int twi_clk)
120 int ckdiv, cdiv, div;
121 struct at91_twi_pdata *pdata = dev->pdata;
122 int offset = pdata->clk_offset;
123 int max_ckdiv = pdata->clk_max_div;
125 div = max(0, (int)DIV_ROUND_UP(clk_get_rate(dev->clk),
126 2 * twi_clk) - offset);
127 ckdiv = fls(div >> 8);
130 if (ckdiv > max_ckdiv) {
131 dev_warn(dev->dev, "%d exceeds ckdiv max value which is %d.\n",
137 dev->twi_cwgr_reg = (ckdiv << 16) | (cdiv << 8) | cdiv;
138 dev_dbg(dev->dev, "cdiv %d ckdiv %d\n", cdiv, ckdiv);
141 static void at91_twi_write_next_byte(struct at91_twi_dev *dev)
143 if (dev->buf_len <= 0)
146 at91_twi_write(dev, AT91_TWI_THR, *dev->buf);
148 /* send stop when last byte has been written */
149 if (--dev->buf_len == 0)
150 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
152 dev_dbg(dev->dev, "wrote 0x%x, to go %d\n", *dev->buf, dev->buf_len);
157 static void at91_twi_read_next_byte(struct at91_twi_dev *dev)
159 if (dev->buf_len <= 0)
162 *dev->buf = at91_twi_read(dev, AT91_TWI_RHR) & 0xff;
165 /* handle I2C_SMBUS_BLOCK_DATA */
166 if (unlikely(dev->msg->flags & I2C_M_RECV_LEN)) {
167 dev->msg->flags &= ~I2C_M_RECV_LEN;
168 dev->buf_len += *dev->buf;
169 dev->msg->len = dev->buf_len + 1;
170 dev_dbg(dev->dev, "received block length %d\n", dev->buf_len);
173 /* send stop if second but last byte has been read */
174 if (dev->buf_len == 1)
175 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_STOP);
177 dev_dbg(dev->dev, "read 0x%x, to go %d\n", *dev->buf, dev->buf_len);
182 static irqreturn_t atmel_twi_interrupt(int irq, void *dev_id)
184 struct at91_twi_dev *dev = dev_id;
185 const unsigned status = at91_twi_read(dev, AT91_TWI_SR);
186 const unsigned irqstatus = status & at91_twi_read(dev, AT91_TWI_IMR);
190 else if (irqstatus & AT91_TWI_RXRDY)
191 at91_twi_read_next_byte(dev);
192 else if (irqstatus & AT91_TWI_TXRDY)
193 at91_twi_write_next_byte(dev);
195 /* catch error flags */
196 dev->transfer_status |= status;
198 if (irqstatus & AT91_TWI_TXCOMP) {
199 at91_disable_twi_interrupts(dev);
200 complete(&dev->cmd_complete);
206 static int at91_do_twi_transfer(struct at91_twi_dev *dev)
209 bool has_unre_flag = dev->pdata->has_unre_flag;
211 dev_dbg(dev->dev, "transfer: %s %d bytes.\n",
212 (dev->msg->flags & I2C_M_RD) ? "read" : "write", dev->buf_len);
214 INIT_COMPLETION(dev->cmd_complete);
215 dev->transfer_status = 0;
218 at91_twi_write(dev, AT91_TWI_CR, AT91_TWI_QUICK);
219 at91_twi_write(dev, AT91_TWI_IER, AT91_TWI_TXCOMP);
220 } else if (dev->msg->flags & I2C_M_RD) {
221 unsigned start_flags = AT91_TWI_START;
223 if (at91_twi_read(dev, AT91_TWI_SR) & AT91_TWI_RXRDY) {
224 dev_err(dev->dev, "RXRDY still set!");
225 at91_twi_read(dev, AT91_TWI_RHR);
228 /* if only one byte is to be read, immediately stop transfer */
229 if (dev->buf_len <= 1 && !(dev->msg->flags & I2C_M_RECV_LEN))
230 start_flags |= AT91_TWI_STOP;
231 at91_twi_write(dev, AT91_TWI_CR, start_flags);
232 at91_twi_write(dev, AT91_TWI_IER,
233 AT91_TWI_TXCOMP | AT91_TWI_RXRDY);
235 at91_twi_write_next_byte(dev);
236 at91_twi_write(dev, AT91_TWI_IER,
237 AT91_TWI_TXCOMP | AT91_TWI_TXRDY);
240 ret = wait_for_completion_interruptible_timeout(&dev->cmd_complete,
241 dev->adapter.timeout);
243 dev_err(dev->dev, "controller timed out\n");
244 at91_init_twi_bus(dev);
247 if (dev->transfer_status & AT91_TWI_NACK) {
248 dev_dbg(dev->dev, "received nack\n");
251 if (dev->transfer_status & AT91_TWI_OVRE) {
252 dev_err(dev->dev, "overrun while reading\n");
255 if (has_unre_flag && dev->transfer_status & AT91_TWI_UNRE) {
256 dev_err(dev->dev, "underrun while writing\n");
259 dev_dbg(dev->dev, "transfer complete\n");
264 static int at91_twi_xfer(struct i2c_adapter *adap, struct i2c_msg *msg, int num)
266 struct at91_twi_dev *dev = i2c_get_adapdata(adap);
268 unsigned int_addr_flag = 0;
269 struct i2c_msg *m_start = msg;
271 dev_dbg(&adap->dev, "at91_xfer: processing %d messages:\n", num);
274 * The hardware can handle at most two messages concatenated by a
275 * repeated start via it's internal address feature.
279 "cannot handle more than two concatenated messages.\n");
281 } else if (num == 2) {
282 int internal_address = 0;
285 if (msg->flags & I2C_M_RD) {
286 dev_err(dev->dev, "first transfer must be write.\n");
290 dev_err(dev->dev, "first message size must be <= 3.\n");
294 /* 1st msg is put into the internal address, start with 2nd */
296 for (i = 0; i < msg->len; ++i) {
297 const unsigned addr = msg->buf[msg->len - 1 - i];
299 internal_address |= addr << (8 * i);
300 int_addr_flag += AT91_TWI_IADRSZ_1;
302 at91_twi_write(dev, AT91_TWI_IADR, internal_address);
305 at91_twi_write(dev, AT91_TWI_MMR, (m_start->addr << 16) | int_addr_flag
306 | ((m_start->flags & I2C_M_RD) ? AT91_TWI_MREAD : 0));
308 dev->buf_len = m_start->len;
309 dev->buf = m_start->buf;
312 ret = at91_do_twi_transfer(dev);
314 return (ret < 0) ? ret : num;
317 static u32 at91_twi_func(struct i2c_adapter *adapter)
319 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL
320 | I2C_FUNC_SMBUS_READ_BLOCK_DATA;
323 static struct i2c_algorithm at91_twi_algorithm = {
324 .master_xfer = at91_twi_xfer,
325 .functionality = at91_twi_func,
328 static struct at91_twi_pdata at91rm9200_config = {
331 .has_unre_flag = true,
334 static struct at91_twi_pdata at91sam9261_config = {
337 .has_unre_flag = false,
340 static struct at91_twi_pdata at91sam9260_config = {
343 .has_unre_flag = false,
346 static struct at91_twi_pdata at91sam9g20_config = {
349 .has_unre_flag = false,
352 static struct at91_twi_pdata at91sam9g10_config = {
355 .has_unre_flag = false,
358 static struct at91_twi_pdata at91sam9x5_config = {
361 .has_unre_flag = false,
364 static const struct platform_device_id at91_twi_devtypes[] = {
366 .name = "i2c-at91rm9200",
367 .driver_data = (unsigned long) &at91rm9200_config,
369 .name = "i2c-at91sam9261",
370 .driver_data = (unsigned long) &at91sam9261_config,
372 .name = "i2c-at91sam9260",
373 .driver_data = (unsigned long) &at91sam9260_config,
375 .name = "i2c-at91sam9g20",
376 .driver_data = (unsigned long) &at91sam9g20_config,
378 .name = "i2c-at91sam9g10",
379 .driver_data = (unsigned long) &at91sam9g10_config,
385 #if defined(CONFIG_OF)
386 static const struct of_device_id atmel_twi_dt_ids[] = {
388 .compatible = "atmel,at91sam9260-i2c",
389 .data = &at91sam9260_config,
391 .compatible = "atmel,at91sam9g20-i2c",
392 .data = &at91sam9g20_config,
394 .compatible = "atmel,at91sam9g10-i2c",
395 .data = &at91sam9g10_config,
397 .compatible = "atmel,at91sam9x5-i2c",
398 .data = &at91sam9x5_config,
403 MODULE_DEVICE_TABLE(of, atmel_twi_dt_ids);
405 #define atmel_twi_dt_ids NULL
408 static struct at91_twi_pdata * __devinit at91_twi_get_driver_data(
409 struct platform_device *pdev)
411 if (pdev->dev.of_node) {
412 const struct of_device_id *match;
413 match = of_match_node(atmel_twi_dt_ids, pdev->dev.of_node);
418 return (struct at91_twi_pdata *) platform_get_device_id(pdev)->driver_data;
421 static int __devinit at91_twi_probe(struct platform_device *pdev)
423 struct at91_twi_dev *dev;
424 struct resource *mem;
427 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
430 init_completion(&dev->cmd_complete);
431 dev->dev = &pdev->dev;
433 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
437 dev->pdata = at91_twi_get_driver_data(pdev);
441 dev->base = devm_request_and_ioremap(&pdev->dev, mem);
445 dev->irq = platform_get_irq(pdev, 0);
449 rc = devm_request_irq(&pdev->dev, dev->irq, atmel_twi_interrupt, 0,
450 dev_name(dev->dev), dev);
452 dev_err(dev->dev, "Cannot get irq %d: %d\n", dev->irq, rc);
456 platform_set_drvdata(pdev, dev);
458 dev->clk = devm_clk_get(dev->dev, NULL);
459 if (IS_ERR(dev->clk)) {
460 dev_err(dev->dev, "no clock defined\n");
463 clk_prepare_enable(dev->clk);
465 at91_calc_twi_clock(dev, TWI_CLK_HZ);
466 at91_init_twi_bus(dev);
468 snprintf(dev->adapter.name, sizeof(dev->adapter.name), "AT91");
469 i2c_set_adapdata(&dev->adapter, dev);
470 dev->adapter.owner = THIS_MODULE;
471 dev->adapter.class = I2C_CLASS_HWMON;
472 dev->adapter.algo = &at91_twi_algorithm;
473 dev->adapter.dev.parent = dev->dev;
474 dev->adapter.nr = pdev->id;
475 dev->adapter.timeout = AT91_I2C_TIMEOUT;
476 dev->adapter.dev.of_node = pdev->dev.of_node;
478 rc = i2c_add_numbered_adapter(&dev->adapter);
480 dev_err(dev->dev, "Adapter %s registration failed\n",
482 clk_disable_unprepare(dev->clk);
486 of_i2c_register_devices(&dev->adapter);
488 dev_info(dev->dev, "AT91 i2c bus driver.\n");
492 static int __devexit at91_twi_remove(struct platform_device *pdev)
494 struct at91_twi_dev *dev = platform_get_drvdata(pdev);
497 rc = i2c_del_adapter(&dev->adapter);
498 clk_disable_unprepare(dev->clk);
505 static int at91_twi_runtime_suspend(struct device *dev)
507 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
509 clk_disable(twi_dev->clk);
514 static int at91_twi_runtime_resume(struct device *dev)
516 struct at91_twi_dev *twi_dev = dev_get_drvdata(dev);
518 return clk_enable(twi_dev->clk);
521 static const struct dev_pm_ops at91_twi_pm = {
522 .runtime_suspend = at91_twi_runtime_suspend,
523 .runtime_resume = at91_twi_runtime_resume,
526 #define at91_twi_pm_ops (&at91_twi_pm)
528 #define at91_twi_pm_ops NULL
531 static struct platform_driver at91_twi_driver = {
532 .probe = at91_twi_probe,
533 .remove = __devexit_p(at91_twi_remove),
534 .id_table = at91_twi_devtypes,
537 .owner = THIS_MODULE,
538 .of_match_table = atmel_twi_dt_ids,
539 .pm = at91_twi_pm_ops,
543 static int __init at91_twi_init(void)
545 return platform_driver_register(&at91_twi_driver);
548 static void __exit at91_twi_exit(void)
550 platform_driver_unregister(&at91_twi_driver);
553 subsys_initcall(at91_twi_init);
554 module_exit(at91_twi_exit);
556 MODULE_AUTHOR("Nikolaus Voss <n.voss@weinmann.de>");
557 MODULE_DESCRIPTION("I2C (TWI) driver for Atmel AT91");
558 MODULE_LICENSE("GPL");
559 MODULE_ALIAS("platform:at91_i2c");