2 * Copyright (C) 2013 Broadcom Corporation
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation version 2.
8 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
9 * kind, whether express or implied; without even the implied warranty
10 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
11 * GNU General Public License for more details.
14 #include <linux/device.h>
15 #include <linux/kernel.h>
16 #include <linux/module.h>
17 #include <linux/sched.h>
18 #include <linux/i2c.h>
19 #include <linux/interrupt.h>
20 #include <linux/platform_device.h>
21 #include <linux/clk.h>
23 #include <linux/clk.h>
24 #include <linux/slab.h>
26 /* Hardware register offsets and field defintions */
27 #define CS_OFFSET 0x00000020
28 #define CS_ACK_SHIFT 3
29 #define CS_ACK_MASK 0x00000008
30 #define CS_ACK_CMD_GEN_START 0x00000000
31 #define CS_ACK_CMD_GEN_RESTART 0x00000001
32 #define CS_CMD_SHIFT 1
33 #define CS_CMD_CMD_NO_ACTION 0x00000000
34 #define CS_CMD_CMD_START_RESTART 0x00000001
35 #define CS_CMD_CMD_STOP 0x00000002
37 #define CS_EN_CMD_ENABLE_BSC 0x00000001
39 #define TIM_OFFSET 0x00000024
40 #define TIM_PRESCALE_SHIFT 6
42 #define TIM_NO_DIV_SHIFT 2
43 #define TIM_DIV_SHIFT 0
45 #define DAT_OFFSET 0x00000028
47 #define TOUT_OFFSET 0x0000002c
49 #define TXFCR_OFFSET 0x0000003c
50 #define TXFCR_FIFO_FLUSH_MASK 0x00000080
51 #define TXFCR_FIFO_EN_MASK 0x00000040
53 #define IER_OFFSET 0x00000044
54 #define IER_READ_COMPLETE_INT_MASK 0x00000010
55 #define IER_I2C_INT_EN_MASK 0x00000008
56 #define IER_FIFO_INT_EN_MASK 0x00000002
57 #define IER_NOACK_EN_MASK 0x00000001
59 #define ISR_OFFSET 0x00000048
60 #define ISR_RESERVED_MASK 0xffffff60
61 #define ISR_CMDBUSY_MASK 0x00000080
62 #define ISR_READ_COMPLETE_MASK 0x00000010
63 #define ISR_SES_DONE_MASK 0x00000008
64 #define ISR_ERR_MASK 0x00000004
65 #define ISR_TXFIFOEMPTY_MASK 0x00000002
66 #define ISR_NOACK_MASK 0x00000001
68 #define CLKEN_OFFSET 0x0000004C
69 #define CLKEN_AUTOSENSE_OFF_MASK 0x00000080
70 #define CLKEN_M_SHIFT 4
71 #define CLKEN_N_SHIFT 1
72 #define CLKEN_CLKEN_MASK 0x00000001
74 #define FIFO_STATUS_OFFSET 0x00000054
75 #define FIFO_STATUS_RXFIFO_EMPTY_MASK 0x00000004
76 #define FIFO_STATUS_TXFIFO_EMPTY_MASK 0x00000010
78 #define HSTIM_OFFSET 0x00000058
79 #define HSTIM_HS_MODE_MASK 0x00008000
80 #define HSTIM_HS_HOLD_SHIFT 10
81 #define HSTIM_HS_HIGH_PHASE_SHIFT 5
82 #define HSTIM_HS_SETUP_SHIFT 0
84 #define PADCTL_OFFSET 0x0000005c
85 #define PADCTL_PAD_OUT_EN_MASK 0x00000004
87 #define RXFCR_OFFSET 0x00000068
88 #define RXFCR_NACK_EN_SHIFT 7
89 #define RXFCR_READ_COUNT_SHIFT 0
90 #define RXFIFORDOUT_OFFSET 0x0000006c
92 /* Locally used constants */
93 #define MAX_RX_FIFO_SIZE 64U /* bytes */
94 #define MAX_TX_FIFO_SIZE 64U /* bytes */
96 #define STD_EXT_CLK_FREQ 13000000UL
97 #define HS_EXT_CLK_FREQ 104000000UL
99 #define MASTERCODE 0x08 /* Mastercodes are 0000_1xxxb */
101 #define I2C_TIMEOUT 100 /* msecs */
103 /* Operations that can be commanded to the controller */
104 enum bcm_kona_cmd_t {
105 BCM_CMD_NOACTION = 0,
111 enum bus_speed_index {
117 enum hs_bus_speed_index {
121 /* Internal divider settings for standard mode, fast mode and fast mode plus */
122 struct bus_speed_cfg {
123 uint8_t time_m; /* Number of cycles for setup time */
124 uint8_t time_n; /* Number of cycles for hold time */
125 uint8_t prescale; /* Prescale divider */
126 uint8_t time_p; /* Timing coefficient */
127 uint8_t no_div; /* Disable clock divider */
128 uint8_t time_div; /* Post-prescale divider */
131 /* Internal divider settings for high-speed mode */
132 struct hs_bus_speed_cfg {
133 uint8_t hs_hold; /* Number of clock cycles SCL stays low until
134 the end of bit period */
135 uint8_t hs_high_phase; /* Number of clock cycles SCL stays high
137 uint8_t hs_setup; /* Number of clock cycles SCL stays low
139 uint8_t prescale; /* Prescale divider */
140 uint8_t time_p; /* Timing coefficient */
141 uint8_t no_div; /* Disable clock divider */
142 uint8_t time_div; /* Post-prescale divider */
145 static const struct bus_speed_cfg std_cfg_table[] = {
146 [BCM_SPD_100K] = {0x01, 0x01, 0x03, 0x06, 0x00, 0x02},
147 [BCM_SPD_400K] = {0x05, 0x01, 0x03, 0x05, 0x01, 0x02},
148 [BCM_SPD_1MHZ] = {0x01, 0x01, 0x03, 0x01, 0x01, 0x03},
151 static const struct hs_bus_speed_cfg hs_cfg_table[] = {
152 [BCM_SPD_3P4MHZ] = {0x01, 0x08, 0x14, 0x00, 0x06, 0x01, 0x00},
155 struct bcm_kona_i2c_dev {
156 struct device *device;
160 struct clk *external_clk;
162 struct i2c_adapter adapter;
164 struct completion done;
166 const struct bus_speed_cfg *std_cfg;
167 const struct hs_bus_speed_cfg *hs_cfg;
170 static void bcm_kona_i2c_send_cmd_to_ctrl(struct bcm_kona_i2c_dev *dev,
171 enum bcm_kona_cmd_t cmd)
173 dev_dbg(dev->device, "%s, %d\n", __func__, cmd);
176 case BCM_CMD_NOACTION:
177 writel((CS_CMD_CMD_NO_ACTION << CS_CMD_SHIFT) |
178 (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
179 dev->base + CS_OFFSET);
183 writel((CS_ACK_CMD_GEN_START << CS_ACK_SHIFT) |
184 (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
185 (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
186 dev->base + CS_OFFSET);
189 case BCM_CMD_RESTART:
190 writel((CS_ACK_CMD_GEN_RESTART << CS_ACK_SHIFT) |
191 (CS_CMD_CMD_START_RESTART << CS_CMD_SHIFT) |
192 (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
193 dev->base + CS_OFFSET);
197 writel((CS_CMD_CMD_STOP << CS_CMD_SHIFT) |
198 (CS_EN_CMD_ENABLE_BSC << CS_EN_SHIFT),
199 dev->base + CS_OFFSET);
203 dev_err(dev->device, "Unknown command %d\n", cmd);
207 static void bcm_kona_i2c_enable_clock(struct bcm_kona_i2c_dev *dev)
209 writel(readl(dev->base + CLKEN_OFFSET) | CLKEN_CLKEN_MASK,
210 dev->base + CLKEN_OFFSET);
213 static void bcm_kona_i2c_disable_clock(struct bcm_kona_i2c_dev *dev)
215 writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_CLKEN_MASK,
216 dev->base + CLKEN_OFFSET);
219 static irqreturn_t bcm_kona_i2c_isr(int irq, void *devid)
221 struct bcm_kona_i2c_dev *dev = devid;
222 uint32_t status = readl(dev->base + ISR_OFFSET);
224 if ((status & ~ISR_RESERVED_MASK) == 0)
227 /* Must flush the TX FIFO when NAK detected */
228 if (status & ISR_NOACK_MASK)
229 writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
230 dev->base + TXFCR_OFFSET);
232 writel(status & ~ISR_RESERVED_MASK, dev->base + ISR_OFFSET);
233 complete_all(&dev->done);
238 /* Wait for ISR_CMDBUSY_MASK to go low before writing to CS, DAT, or RCD */
239 static int bcm_kona_i2c_wait_if_busy(struct bcm_kona_i2c_dev *dev)
241 unsigned long timeout = jiffies + msecs_to_jiffies(I2C_TIMEOUT);
243 while (readl(dev->base + ISR_OFFSET) & ISR_CMDBUSY_MASK)
244 if (time_after(jiffies, timeout)) {
245 dev_err(dev->device, "CMDBUSY timeout\n");
252 /* Send command to I2C bus */
253 static int bcm_kona_send_i2c_cmd(struct bcm_kona_i2c_dev *dev,
254 enum bcm_kona_cmd_t cmd)
257 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT);
259 /* Make sure the hardware is ready */
260 rc = bcm_kona_i2c_wait_if_busy(dev);
264 /* Unmask the session done interrupt */
265 writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET);
267 /* Mark as incomplete before sending the command */
268 reinit_completion(&dev->done);
270 /* Send the command */
271 bcm_kona_i2c_send_cmd_to_ctrl(dev, cmd);
273 /* Wait for transaction to finish or timeout */
274 time_left = wait_for_completion_timeout(&dev->done, time_left);
276 /* Mask all interrupts */
277 writel(0, dev->base + IER_OFFSET);
280 dev_err(dev->device, "controller timed out\n");
285 bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
290 /* Read a single RX FIFO worth of data from the i2c bus */
291 static int bcm_kona_i2c_read_fifo_single(struct bcm_kona_i2c_dev *dev,
292 uint8_t *buf, unsigned int len,
293 unsigned int last_byte_nak)
295 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT);
297 /* Mark as incomplete before starting the RX FIFO */
298 reinit_completion(&dev->done);
300 /* Unmask the read complete interrupt */
301 writel(IER_READ_COMPLETE_INT_MASK, dev->base + IER_OFFSET);
303 /* Start the RX FIFO */
304 writel((last_byte_nak << RXFCR_NACK_EN_SHIFT) |
305 (len << RXFCR_READ_COUNT_SHIFT),
306 dev->base + RXFCR_OFFSET);
308 /* Wait for FIFO read to complete */
309 time_left = wait_for_completion_timeout(&dev->done, time_left);
311 /* Mask all interrupts */
312 writel(0, dev->base + IER_OFFSET);
315 dev_err(dev->device, "RX FIFO time out\n");
319 /* Read data from FIFO */
320 for (; len > 0; len--, buf++)
321 *buf = readl(dev->base + RXFIFORDOUT_OFFSET);
326 /* Read any amount of data using the RX FIFO from the i2c bus */
327 static int bcm_kona_i2c_read_fifo(struct bcm_kona_i2c_dev *dev,
330 unsigned int bytes_to_read = MAX_RX_FIFO_SIZE;
331 unsigned int last_byte_nak = 0;
332 unsigned int bytes_read = 0;
335 uint8_t *tmp_buf = msg->buf;
337 while (bytes_read < msg->len) {
338 if (msg->len - bytes_read <= MAX_RX_FIFO_SIZE) {
339 last_byte_nak = 1; /* NAK last byte of transfer */
340 bytes_to_read = msg->len - bytes_read;
343 rc = bcm_kona_i2c_read_fifo_single(dev, tmp_buf, bytes_to_read,
348 bytes_read += bytes_to_read;
349 tmp_buf += bytes_to_read;
355 /* Write a single byte of data to the i2c bus */
356 static int bcm_kona_i2c_write_byte(struct bcm_kona_i2c_dev *dev, uint8_t data,
357 unsigned int nak_expected)
360 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT);
361 unsigned int nak_received;
363 /* Make sure the hardware is ready */
364 rc = bcm_kona_i2c_wait_if_busy(dev);
368 /* Clear pending session done interrupt */
369 writel(ISR_SES_DONE_MASK, dev->base + ISR_OFFSET);
371 /* Unmask the session done interrupt */
372 writel(IER_I2C_INT_EN_MASK, dev->base + IER_OFFSET);
374 /* Mark as incomplete before sending the data */
375 reinit_completion(&dev->done);
377 /* Send one byte of data */
378 writel(data, dev->base + DAT_OFFSET);
380 /* Wait for byte to be written */
381 time_left = wait_for_completion_timeout(&dev->done, time_left);
383 /* Mask all interrupts */
384 writel(0, dev->base + IER_OFFSET);
387 dev_dbg(dev->device, "controller timed out\n");
391 nak_received = readl(dev->base + CS_OFFSET) & CS_ACK_MASK ? 1 : 0;
393 if (nak_received ^ nak_expected) {
394 dev_dbg(dev->device, "unexpected NAK/ACK\n");
401 /* Write a single TX FIFO worth of data to the i2c bus */
402 static int bcm_kona_i2c_write_fifo_single(struct bcm_kona_i2c_dev *dev,
403 uint8_t *buf, unsigned int len)
406 unsigned long time_left = msecs_to_jiffies(I2C_TIMEOUT);
407 unsigned int fifo_status;
409 /* Mark as incomplete before sending data to the TX FIFO */
410 reinit_completion(&dev->done);
412 /* Unmask the fifo empty and nak interrupt */
413 writel(IER_FIFO_INT_EN_MASK | IER_NOACK_EN_MASK,
414 dev->base + IER_OFFSET);
416 /* Disable IRQ to load a FIFO worth of data without interruption */
417 disable_irq(dev->irq);
419 /* Write data into FIFO */
420 for (k = 0; k < len; k++)
421 writel(buf[k], (dev->base + DAT_OFFSET));
423 /* Enable IRQ now that data has been loaded */
424 enable_irq(dev->irq);
426 /* Wait for FIFO to empty */
428 time_left = wait_for_completion_timeout(&dev->done, time_left);
429 fifo_status = readl(dev->base + FIFO_STATUS_OFFSET);
430 } while (time_left && !(fifo_status & FIFO_STATUS_TXFIFO_EMPTY_MASK));
432 /* Mask all interrupts */
433 writel(0, dev->base + IER_OFFSET);
435 /* Check if there was a NAK */
436 if (readl(dev->base + CS_OFFSET) & CS_ACK_MASK) {
437 dev_err(dev->device, "unexpected NAK\n");
441 /* Check if a timeout occured */
443 dev_err(dev->device, "completion timed out\n");
451 /* Write any amount of data using TX FIFO to the i2c bus */
452 static int bcm_kona_i2c_write_fifo(struct bcm_kona_i2c_dev *dev,
455 unsigned int bytes_to_write = MAX_TX_FIFO_SIZE;
456 unsigned int bytes_written = 0;
459 uint8_t *tmp_buf = msg->buf;
461 while (bytes_written < msg->len) {
462 if (msg->len - bytes_written <= MAX_TX_FIFO_SIZE)
463 bytes_to_write = msg->len - bytes_written;
465 rc = bcm_kona_i2c_write_fifo_single(dev, tmp_buf,
470 bytes_written += bytes_to_write;
471 tmp_buf += bytes_to_write;
477 /* Send i2c address */
478 static int bcm_kona_i2c_do_addr(struct bcm_kona_i2c_dev *dev,
483 if (msg->flags & I2C_M_TEN) {
484 /* First byte is 11110XX0 where XX is upper 2 bits */
485 addr = 0xF0 | ((msg->addr & 0x300) >> 7);
486 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
489 /* Second byte is the remaining 8 bits */
490 addr = msg->addr & 0xFF;
491 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
494 if (msg->flags & I2C_M_RD) {
495 /* For read, send restart command */
496 if (bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART) < 0)
499 /* Then re-send the first byte with the read bit set */
500 addr = 0xF0 | ((msg->addr & 0x300) >> 7) | 0x01;
501 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
505 addr = msg->addr << 1;
507 if (msg->flags & I2C_M_RD)
510 if (bcm_kona_i2c_write_byte(dev, addr, 0) < 0)
517 static void bcm_kona_i2c_enable_autosense(struct bcm_kona_i2c_dev *dev)
519 writel(readl(dev->base + CLKEN_OFFSET) & ~CLKEN_AUTOSENSE_OFF_MASK,
520 dev->base + CLKEN_OFFSET);
523 static void bcm_kona_i2c_config_timing(struct bcm_kona_i2c_dev *dev)
525 writel(readl(dev->base + HSTIM_OFFSET) & ~HSTIM_HS_MODE_MASK,
526 dev->base + HSTIM_OFFSET);
528 writel((dev->std_cfg->prescale << TIM_PRESCALE_SHIFT) |
529 (dev->std_cfg->time_p << TIM_P_SHIFT) |
530 (dev->std_cfg->no_div << TIM_NO_DIV_SHIFT) |
531 (dev->std_cfg->time_div << TIM_DIV_SHIFT),
532 dev->base + TIM_OFFSET);
534 writel((dev->std_cfg->time_m << CLKEN_M_SHIFT) |
535 (dev->std_cfg->time_n << CLKEN_N_SHIFT) |
537 dev->base + CLKEN_OFFSET);
540 static void bcm_kona_i2c_config_timing_hs(struct bcm_kona_i2c_dev *dev)
542 writel((dev->hs_cfg->prescale << TIM_PRESCALE_SHIFT) |
543 (dev->hs_cfg->time_p << TIM_P_SHIFT) |
544 (dev->hs_cfg->no_div << TIM_NO_DIV_SHIFT) |
545 (dev->hs_cfg->time_div << TIM_DIV_SHIFT),
546 dev->base + TIM_OFFSET);
548 writel((dev->hs_cfg->hs_hold << HSTIM_HS_HOLD_SHIFT) |
549 (dev->hs_cfg->hs_high_phase << HSTIM_HS_HIGH_PHASE_SHIFT) |
550 (dev->hs_cfg->hs_setup << HSTIM_HS_SETUP_SHIFT),
551 dev->base + HSTIM_OFFSET);
553 writel(readl(dev->base + HSTIM_OFFSET) | HSTIM_HS_MODE_MASK,
554 dev->base + HSTIM_OFFSET);
557 static int bcm_kona_i2c_switch_to_hs(struct bcm_kona_i2c_dev *dev)
561 /* Send mastercode at standard speed */
562 rc = bcm_kona_i2c_write_byte(dev, MASTERCODE, 1);
564 pr_err("High speed handshake failed\n");
568 /* Configure external clock to higher frequency */
569 rc = clk_set_rate(dev->external_clk, HS_EXT_CLK_FREQ);
571 dev_err(dev->device, "%s: clk_set_rate returned %d\n",
576 /* Reconfigure internal dividers */
577 bcm_kona_i2c_config_timing_hs(dev);
579 /* Send a restart command */
580 rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART);
582 dev_err(dev->device, "High speed restart command failed\n");
587 static int bcm_kona_i2c_switch_to_std(struct bcm_kona_i2c_dev *dev)
591 /* Reconfigure internal dividers */
592 bcm_kona_i2c_config_timing(dev);
594 /* Configure external clock to lower frequency */
595 rc = clk_set_rate(dev->external_clk, STD_EXT_CLK_FREQ);
597 dev_err(dev->device, "%s: clk_set_rate returned %d\n",
604 /* Master transfer function */
605 static int bcm_kona_i2c_xfer(struct i2c_adapter *adapter,
606 struct i2c_msg msgs[], int num)
608 struct bcm_kona_i2c_dev *dev = i2c_get_adapdata(adapter);
609 struct i2c_msg *pmsg;
613 rc = clk_prepare_enable(dev->external_clk);
615 dev_err(dev->device, "%s: peri clock enable failed. err %d\n",
620 /* Enable pad output */
621 writel(0, dev->base + PADCTL_OFFSET);
623 /* Enable internal clocks */
624 bcm_kona_i2c_enable_clock(dev);
626 /* Send start command */
627 rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_START);
629 dev_err(dev->device, "Start command failed rc = %d\n", rc);
630 goto xfer_disable_pad;
633 /* Switch to high speed if applicable */
635 rc = bcm_kona_i2c_switch_to_hs(dev);
640 /* Loop through all messages */
641 for (i = 0; i < num; i++) {
644 /* Send restart for subsequent messages */
645 if ((i != 0) && ((pmsg->flags & I2C_M_NOSTART) == 0)) {
646 rc = bcm_kona_send_i2c_cmd(dev, BCM_CMD_RESTART);
649 "restart cmd failed rc = %d\n", rc);
654 /* Send slave address */
655 if (!(pmsg->flags & I2C_M_NOSTART)) {
656 rc = bcm_kona_i2c_do_addr(dev, pmsg);
659 "NAK from addr %2.2x msg#%d rc = %d\n",
665 /* Perform data transfer */
666 if (pmsg->flags & I2C_M_RD) {
667 rc = bcm_kona_i2c_read_fifo(dev, pmsg);
669 dev_err(dev->device, "read failure\n");
673 rc = bcm_kona_i2c_write_fifo(dev, pmsg);
675 dev_err(dev->device, "write failure");
684 /* Send a STOP command */
685 bcm_kona_send_i2c_cmd(dev, BCM_CMD_STOP);
687 /* Return from high speed if applicable */
689 int hs_rc = bcm_kona_i2c_switch_to_std(dev);
696 /* Disable pad output */
697 writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
699 /* Stop internal clock */
700 bcm_kona_i2c_disable_clock(dev);
702 clk_disable_unprepare(dev->external_clk);
707 static uint32_t bcm_kona_i2c_functionality(struct i2c_adapter *adap)
709 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_10BIT_ADDR |
713 static const struct i2c_algorithm bcm_algo = {
714 .master_xfer = bcm_kona_i2c_xfer,
715 .functionality = bcm_kona_i2c_functionality,
718 static int bcm_kona_i2c_assign_bus_speed(struct bcm_kona_i2c_dev *dev)
720 unsigned int bus_speed;
721 int ret = of_property_read_u32(dev->device->of_node, "clock-frequency",
724 dev_err(dev->device, "missing clock-frequency property\n");
730 dev->std_cfg = &std_cfg_table[BCM_SPD_100K];
733 dev->std_cfg = &std_cfg_table[BCM_SPD_400K];
736 dev->std_cfg = &std_cfg_table[BCM_SPD_1MHZ];
739 /* Send mastercode at 100k */
740 dev->std_cfg = &std_cfg_table[BCM_SPD_100K];
741 dev->hs_cfg = &hs_cfg_table[BCM_SPD_3P4MHZ];
744 pr_err("%d hz bus speed not supported\n", bus_speed);
745 pr_err("Valid speeds are 100khz, 400khz, 1mhz, and 3.4mhz\n");
752 static int bcm_kona_i2c_probe(struct platform_device *pdev)
755 struct bcm_kona_i2c_dev *dev;
756 struct i2c_adapter *adap;
757 struct resource *iomem;
759 /* Allocate memory for private data structure */
760 dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
764 platform_set_drvdata(pdev, dev);
765 dev->device = &pdev->dev;
766 init_completion(&dev->done);
768 /* Map hardware registers */
769 iomem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
770 dev->base = devm_ioremap_resource(dev->device, iomem);
771 if (IS_ERR(dev->base))
774 /* Get and enable external clock */
775 dev->external_clk = devm_clk_get(dev->device, NULL);
776 if (IS_ERR(dev->external_clk)) {
777 dev_err(dev->device, "couldn't get clock\n");
781 rc = clk_set_rate(dev->external_clk, STD_EXT_CLK_FREQ);
783 dev_err(dev->device, "%s: clk_set_rate returned %d\n",
788 rc = clk_prepare_enable(dev->external_clk);
790 dev_err(dev->device, "couldn't enable clock\n");
794 /* Parse bus speed */
795 rc = bcm_kona_i2c_assign_bus_speed(dev);
797 goto probe_disable_clk;
799 /* Enable internal clocks */
800 bcm_kona_i2c_enable_clock(dev);
802 /* Configure internal dividers */
803 bcm_kona_i2c_config_timing(dev);
805 /* Disable timeout */
806 writel(0, dev->base + TOUT_OFFSET);
808 /* Enable autosense */
809 bcm_kona_i2c_enable_autosense(dev);
812 writel(TXFCR_FIFO_FLUSH_MASK | TXFCR_FIFO_EN_MASK,
813 dev->base + TXFCR_OFFSET);
815 /* Mask all interrupts */
816 writel(0, dev->base + IER_OFFSET);
818 /* Clear all pending interrupts */
819 writel(ISR_CMDBUSY_MASK |
820 ISR_READ_COMPLETE_MASK |
823 ISR_TXFIFOEMPTY_MASK |
825 dev->base + ISR_OFFSET);
827 /* Get the interrupt number */
828 dev->irq = platform_get_irq(pdev, 0);
830 dev_err(dev->device, "no irq resource\n");
832 goto probe_disable_clk;
835 /* register the ISR handler */
836 rc = devm_request_irq(&pdev->dev, dev->irq, bcm_kona_i2c_isr,
837 IRQF_SHARED, pdev->name, dev);
839 dev_err(dev->device, "failed to request irq %i\n", dev->irq);
840 goto probe_disable_clk;
843 /* Enable the controller but leave it idle */
844 bcm_kona_i2c_send_cmd_to_ctrl(dev, BCM_CMD_NOACTION);
846 /* Disable pad output */
847 writel(PADCTL_PAD_OUT_EN_MASK, dev->base + PADCTL_OFFSET);
849 /* Disable internal clock */
850 bcm_kona_i2c_disable_clock(dev);
852 /* Disable external clock */
853 clk_disable_unprepare(dev->external_clk);
855 /* Add the i2c adapter */
856 adap = &dev->adapter;
857 i2c_set_adapdata(adap, dev);
858 adap->owner = THIS_MODULE;
859 strlcpy(adap->name, "Broadcom I2C adapter", sizeof(adap->name));
860 adap->algo = &bcm_algo;
861 adap->dev.parent = &pdev->dev;
862 adap->dev.of_node = pdev->dev.of_node;
864 rc = i2c_add_adapter(adap);
866 dev_err(dev->device, "failed to add adapter\n");
870 dev_info(dev->device, "device registered successfully\n");
875 bcm_kona_i2c_disable_clock(dev);
876 clk_disable_unprepare(dev->external_clk);
881 static int bcm_kona_i2c_remove(struct platform_device *pdev)
883 struct bcm_kona_i2c_dev *dev = platform_get_drvdata(pdev);
885 i2c_del_adapter(&dev->adapter);
890 static const struct of_device_id bcm_kona_i2c_of_match[] = {
891 {.compatible = "brcm,kona-i2c",},
894 MODULE_DEVICE_TABLE(of, kona_i2c_of_match);
896 static struct platform_driver bcm_kona_i2c_driver = {
898 .name = "bcm-kona-i2c",
899 .owner = THIS_MODULE,
900 .of_match_table = bcm_kona_i2c_of_match,
902 .probe = bcm_kona_i2c_probe,
903 .remove = bcm_kona_i2c_remove,
905 module_platform_driver(bcm_kona_i2c_driver);
907 MODULE_AUTHOR("Tim Kryger <tkryger@broadcom.com>");
908 MODULE_DESCRIPTION("Broadcom Kona I2C Driver");
909 MODULE_LICENSE("GPL v2");