drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007 - 2012  Jean Delvare <khali@linux-fr.org>
   6     Copyright (C) 2010         Intel Corporation,
   7                                David Woodhouse <dwmw2@infradead.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18
  19     You should have received a copy of the GNU General Public License
  20     along with this program; if not, write to the Free Software
  21     Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22 */
  23
  24 /*
  25   Supports the following Intel I/O Controller Hubs (ICH):
  26
  27                                   I/O                     Block   I2C
  28                                   region  SMBus   Block   proc.   block
  29   Chip name             PCI ID    size    PEC     buffer  call    read
  30   ----------------------------------------------------------------------
  31   82801AA  (ICH)        0x2413     16      no      no      no      no
  32   82801AB  (ICH0)       0x2423     16      no      no      no      no
  33   82801BA  (ICH2)       0x2443     16      no      no      no      no
  34   82801CA  (ICH3)       0x2483     32     soft     no      no      no
  35   82801DB  (ICH4)       0x24c3     32     hard     yes     no      no
  36   82801E   (ICH5)       0x24d3     32     hard     yes     yes     yes
  37   6300ESB               0x25a4     32     hard     yes     yes     yes
  38   82801F   (ICH6)       0x266a     32     hard     yes     yes     yes
  39   6310ESB/6320ESB       0x269b     32     hard     yes     yes     yes
  40   82801G   (ICH7)       0x27da     32     hard     yes     yes     yes
  41   82801H   (ICH8)       0x283e     32     hard     yes     yes     yes
  42   82801I   (ICH9)       0x2930     32     hard     yes     yes     yes
  43   EP80579 (Tolapai)     0x5032     32     hard     yes     yes     yes
  44   ICH10                 0x3a30     32     hard     yes     yes     yes
  45   ICH10                 0x3a60     32     hard     yes     yes     yes
  46   5/3400 Series (PCH)   0x3b30     32     hard     yes     yes     yes
  47   6 Series (PCH)        0x1c22     32     hard     yes     yes     yes
  48   Patsburg (PCH)        0x1d22     32     hard     yes     yes     yes
  49   Patsburg (PCH) IDF    0x1d70     32     hard     yes     yes     yes
  50   Patsburg (PCH) IDF    0x1d71     32     hard     yes     yes     yes
  51   Patsburg (PCH) IDF    0x1d72     32     hard     yes     yes     yes
  52   DH89xxCC (PCH)        0x2330     32     hard     yes     yes     yes
  53   Panther Point (PCH)   0x1e22     32     hard     yes     yes     yes
  54   Lynx Point (PCH)      0x8c22     32     hard     yes     yes     yes
  55
  56   Features supported by this driver:
  57   Software PEC                     no
  58   Hardware PEC                     yes
  59   Block buffer                     yes
  60   Block process call transaction   no
  61   I2C block read transaction       yes  (doesn't use the block buffer)
  62   Slave mode                       no
  63
  64   See the file Documentation/i2c/busses/i2c-i801 for details.
  65 */
  66
  67 #include <linux/module.h>
  68 #include <linux/pci.h>
  69 #include <linux/kernel.h>
  70 #include <linux/stddef.h>
  71 #include <linux/delay.h>
  72 #include <linux/ioport.h>
  73 #include <linux/init.h>
  74 #include <linux/i2c.h>
  75 #include <linux/acpi.h>
  76 #include <linux/io.h>
  77 #include <linux/dmi.h>
  78 #include <linux/slab.h>
  79
  80 /* I801 SMBus address offsets */
  81 #define SMBHSTSTS(p)    (0 + (p)->smba)
  82 #define SMBHSTCNT(p)    (2 + (p)->smba)
  83 #define SMBHSTCMD(p)    (3 + (p)->smba)
  84 #define SMBHSTADD(p)    (4 + (p)->smba)
  85 #define SMBHSTDAT0(p)   (5 + (p)->smba)
  86 #define SMBHSTDAT1(p)   (6 + (p)->smba)
  87 #define SMBBLKDAT(p)    (7 + (p)->smba)
  88 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
  89 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
  90 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
  91
  92 /* PCI Address Constants */
  93 #define SMBBAR          4
  94 #define SMBHSTCFG       0x040
  95
  96 /* Host configuration bits for SMBHSTCFG */
  97 #define SMBHSTCFG_HST_EN        1
  98 #define SMBHSTCFG_SMB_SMI_EN    2
  99 #define SMBHSTCFG_I2C_EN        4
 100
 101 /* Auxiliary control register bits, ICH4+ only */
 102 #define SMBAUXCTL_CRC           1
 103 #define SMBAUXCTL_E32B          2
 104
 105 /* kill bit for SMBHSTCNT */
 106 #define SMBHSTCNT_KILL          2
 107
 108 /* Other settings */
 109 #define MAX_RETRIES             400
 110 #define ENABLE_INT9             0       /* set to 0x01 to enable - untested */
 111
 112 /* I801 command constants */
 113 #define I801_QUICK              0x00
 114 #define I801_BYTE               0x04
 115 #define I801_BYTE_DATA          0x08
 116 #define I801_WORD_DATA          0x0C
 117 #define I801_PROC_CALL          0x10    /* unimplemented */
 118 #define I801_BLOCK_DATA         0x14
 119 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 120 #define I801_LAST_BYTE          0x20
 121 #define I801_START              0x40
 122 #define I801_PEC_EN             0x80    /* ICH3 and later */
 123
 124 /* I801 Hosts Status register bits */
 125 #define SMBHSTSTS_BYTE_DONE     0x80
 126 #define SMBHSTSTS_INUSE_STS     0x40
 127 #define SMBHSTSTS_SMBALERT_STS  0x20
 128 #define SMBHSTSTS_FAILED        0x10
 129 #define SMBHSTSTS_BUS_ERR       0x08
 130 #define SMBHSTSTS_DEV_ERR       0x04
 131 #define SMBHSTSTS_INTR          0x02
 132 #define SMBHSTSTS_HOST_BUSY     0x01
 133
 134 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
 135                                  SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
 136                                  SMBHSTSTS_INTR)
 137
 138 /* Older devices have their ID defined in <linux/pci_ids.h> */
 139 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS   0x1c22
 140 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS      0x1d22
 141 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 142 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
 143 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
 144 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
 145 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS  0x1e22
 146 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS      0x2330
 147 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
 148 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS     0x8c22
 149
 150 struct i801_priv {
 151         struct i2c_adapter adapter;
 152         unsigned long smba;
 153         unsigned char original_hstcfg;
 154         struct pci_dev *pci_dev;
 155         unsigned int features;
 156 };
 157
 158 static struct pci_driver i801_driver;
 159
 160 #define FEATURE_SMBUS_PEC       (1 << 0)
 161 #define FEATURE_BLOCK_BUFFER    (1 << 1)
 162 #define FEATURE_BLOCK_PROC      (1 << 2)
 163 #define FEATURE_I2C_BLOCK_READ  (1 << 3)
 164 /* Not really a feature, but it's convenient to handle it as such */
 165 #define FEATURE_IDF             (1 << 15)
 166
 167 static const char *i801_feature_names[] = {
 168         "SMBus PEC",
 169         "Block buffer",
 170         "Block process call",
 171         "I2C block read",
 172 };
 173
 174 static unsigned int disable_features;
 175 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 176 MODULE_PARM_DESC(disable_features, "Disable selected driver features");
 177
 178 /* Make sure the SMBus host is ready to start transmitting.
 179    Return 0 if it is, -EBUSY if it is not. */
 180 static int i801_check_pre(struct i801_priv *priv)
 181 {
 182         int status;
 183
 184         status = inb_p(SMBHSTSTS(priv));
 185         if (status & SMBHSTSTS_HOST_BUSY) {
 186                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 187                 return -EBUSY;
 188         }
 189
 190         status &= STATUS_FLAGS;
 191         if (status) {
 192                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 193                         status);
 194                 outb_p(status, SMBHSTSTS(priv));
 195                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 196                 if (status) {
 197                         dev_err(&priv->pci_dev->dev,
 198                                 "Failed clearing status flags (%02x)\n",
 199                                 status);
 200                         return -EBUSY;
 201                 }
 202         }
 203
 204         return 0;
 205 }
 206
 207 /* Convert the status register to an error code, and clear it. */
 208 static int i801_check_post(struct i801_priv *priv, int status, int timeout)
 209 {
 210         int result = 0;
 211
 212         /* If the SMBus is still busy, we give up */
 213         if (timeout) {
 214                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 215                 /* try to stop the current command */
 216                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 217                 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
 218                        SMBHSTCNT(priv));
 219                 usleep_range(1000, 2000);
 220                 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
 221                        SMBHSTCNT(priv));
 222
 223                 /* Check if it worked */
 224                 status = inb_p(SMBHSTSTS(priv));
 225                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 226                     !(status & SMBHSTSTS_FAILED))
 227                         dev_err(&priv->pci_dev->dev,
 228                                 "Failed terminating the transaction\n");
 229                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 230                 return -ETIMEDOUT;
 231         }
 232
 233         if (status & SMBHSTSTS_FAILED) {
 234                 result = -EIO;
 235                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 236         }
 237         if (status & SMBHSTSTS_DEV_ERR) {
 238                 result = -ENXIO;
 239                 dev_dbg(&priv->pci_dev->dev, "No response\n");
 240         }
 241         if (status & SMBHSTSTS_BUS_ERR) {
 242                 result = -EAGAIN;
 243                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 244         }
 245
 246         if (result) {
 247                 /* Clear error flags */
 248                 outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv));
 249                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 250                 if (status) {
 251                         dev_warn(&priv->pci_dev->dev, "Failed clearing status "
 252                                  "flags at end of transaction (%02x)\n",
 253                                  status);
 254                 }
 255         }
 256
 257         return result;
 258 }
 259
 260 static int i801_transaction(struct i801_priv *priv, int xact)
 261 {
 262         int status;
 263         int result;
 264         int timeout = 0;
 265
 266         result = i801_check_pre(priv);
 267         if (result < 0)
 268                 return result;
 269
 270         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 271          * INTREN, SMBSCMD are passed in xact */
 272         outb_p(xact | I801_START, SMBHSTCNT(priv));
 273
 274         /* We will always wait for a fraction of a second! */
 275         do {
 276                 usleep_range(250, 500);
 277                 status = inb_p(SMBHSTSTS(priv));
 278         } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_RETRIES));
 279
 280         result = i801_check_post(priv, status, timeout > MAX_RETRIES);
 281         if (result < 0)
 282                 return result;
 283
 284         outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 285         return 0;
 286 }
 287
 288 /* wait for INTR bit as advised by Intel */
 289 static void i801_wait_hwpec(struct i801_priv *priv)
 290 {
 291         int timeout = 0;
 292         int status;
 293
 294         do {
 295                 usleep_range(250, 500);
 296                 status = inb_p(SMBHSTSTS(priv));
 297         } while ((!(status & SMBHSTSTS_INTR))
 298                  && (timeout++ < MAX_RETRIES));
 299
 300         if (timeout > MAX_RETRIES)
 301                 dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n");
 302
 303         outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv));
 304 }
 305
 306 static int i801_block_transaction_by_block(struct i801_priv *priv,
 307                                            union i2c_smbus_data *data,
 308                                            char read_write, int hwpec)
 309 {
 310         int i, len;
 311         int status;
 312
 313         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 314
 315         /* Use 32-byte buffer to process this transaction */
 316         if (read_write == I2C_SMBUS_WRITE) {
 317                 len = data->block[0];
 318                 outb_p(len, SMBHSTDAT0(priv));
 319                 for (i = 0; i < len; i++)
 320                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 321         }
 322
 323         status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 |
 324                                   I801_PEC_EN * hwpec);
 325         if (status)
 326                 return status;
 327
 328         if (read_write == I2C_SMBUS_READ) {
 329                 len = inb_p(SMBHSTDAT0(priv));
 330                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 331                         return -EPROTO;
 332
 333                 data->block[0] = len;
 334                 for (i = 0; i < len; i++)
 335                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 336         }
 337         return 0;
 338 }
 339
 340 /*
 341  * For "byte-by-byte" block transactions:
 342  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 343  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 344  */
 345 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 346                                                union i2c_smbus_data *data,
 347                                                char read_write, int command,
 348                                                int hwpec)
 349 {
 350         int i, len;
 351         int smbcmd;
 352         int status;
 353         int result;
 354         int timeout;
 355
 356         result = i801_check_pre(priv);
 357         if (result < 0)
 358                 return result;
 359
 360         len = data->block[0];
 361
 362         if (read_write == I2C_SMBUS_WRITE) {
 363                 outb_p(len, SMBHSTDAT0(priv));
 364                 outb_p(data->block[1], SMBBLKDAT(priv));
 365         }
 366
 367         if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 368             read_write == I2C_SMBUS_READ)
 369                 smbcmd = I801_I2C_BLOCK_DATA;
 370         else
 371                 smbcmd = I801_BLOCK_DATA;
 372
 373         for (i = 1; i <= len; i++) {
 374                 if (i == len && read_write == I2C_SMBUS_READ)
 375                         smbcmd |= I801_LAST_BYTE;
 376                 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv));
 377
 378                 if (i == 1)
 379                         outb_p(inb(SMBHSTCNT(priv)) | I801_START,
 380                                SMBHSTCNT(priv));
 381
 382                 /* We will always wait for a fraction of a second! */
 383                 timeout = 0;
 384                 do {
 385                         usleep_range(250, 500);
 386                         status = inb_p(SMBHSTSTS(priv));
 387                 } while ((!(status & SMBHSTSTS_BYTE_DONE))
 388                          && (timeout++ < MAX_RETRIES));
 389
 390                 result = i801_check_post(priv, status, timeout > MAX_RETRIES);
 391                 if (result < 0)
 392                         return result;
 393
 394                 if (i == 1 && read_write == I2C_SMBUS_READ
 395                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 396                         len = inb_p(SMBHSTDAT0(priv));
 397                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 398                                 dev_err(&priv->pci_dev->dev,
 399                                         "Illegal SMBus block read size %d\n",
 400                                         len);
 401                                 /* Recover */
 402                                 while (inb_p(SMBHSTSTS(priv)) &
 403                                        SMBHSTSTS_HOST_BUSY)
 404                                         outb_p(SMBHSTSTS_BYTE_DONE,
 405                                                SMBHSTSTS(priv));
 406                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 407                                 return -EPROTO;
 408                         }
 409                         data->block[0] = len;
 410                 }
 411
 412                 /* Retrieve/store value in SMBBLKDAT */
 413                 if (read_write == I2C_SMBUS_READ)
 414                         data->block[i] = inb_p(SMBBLKDAT(priv));
 415                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 416                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 417
 418                 /* signals SMBBLKDAT ready */
 419                 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv));
 420         }
 421
 422         return 0;
 423 }
 424
 425 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 426 {
 427         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 428         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 429                 return -EIO;
 430         return 0;
 431 }
 432
 433 /* Block transaction function */
 434 static int i801_block_transaction(struct i801_priv *priv,
 435                                   union i2c_smbus_data *data, char read_write,
 436                                   int command, int hwpec)
 437 {
 438         int result = 0;
 439         unsigned char hostc;
 440
 441         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 442                 if (read_write == I2C_SMBUS_WRITE) {
 443                         /* set I2C_EN bit in configuration register */
 444                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 445                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 446                                               hostc | SMBHSTCFG_I2C_EN);
 447                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 448                         dev_err(&priv->pci_dev->dev,
 449                                 "I2C block read is unsupported!\n");
 450                         return -EOPNOTSUPP;
 451                 }
 452         }
 453
 454         if (read_write == I2C_SMBUS_WRITE
 455          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 456                 if (data->block[0] < 1)
 457                         data->block[0] = 1;
 458                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 459                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 460         } else {
 461                 data->block[0] = 32;    /* max for SMBus block reads */
 462         }
 463
 464         /* Experience has shown that the block buffer can only be used for
 465            SMBus (not I2C) block transactions, even though the datasheet
 466            doesn't mention this limitation. */
 467         if ((priv->features & FEATURE_BLOCK_BUFFER)
 468          && command != I2C_SMBUS_I2C_BLOCK_DATA
 469          && i801_set_block_buffer_mode(priv) == 0)
 470                 result = i801_block_transaction_by_block(priv, data,
 471                                                          read_write, hwpec);
 472         else
 473                 result = i801_block_transaction_byte_by_byte(priv, data,
 474                                                              read_write,
 475                                                              command, hwpec);
 476
 477         if (result == 0 && hwpec)
 478                 i801_wait_hwpec(priv);
 479
 480         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 481          && read_write == I2C_SMBUS_WRITE) {
 482                 /* restore saved configuration register value */
 483                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 484         }
 485         return result;
 486 }
 487
 488 /* Return negative errno on error. */
 489 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 490                        unsigned short flags, char read_write, u8 command,
 491                        int size, union i2c_smbus_data *data)
 492 {
 493         int hwpec;
 494         int block = 0;
 495         int ret, xact = 0;
 496         struct i801_priv *priv = i2c_get_adapdata(adap);
 497
 498         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 499                 && size != I2C_SMBUS_QUICK
 500                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 501
 502         switch (size) {
 503         case I2C_SMBUS_QUICK:
 504                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 505                        SMBHSTADD(priv));
 506                 xact = I801_QUICK;
 507                 break;
 508         case I2C_SMBUS_BYTE:
 509                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 510                        SMBHSTADD(priv));
 511                 if (read_write == I2C_SMBUS_WRITE)
 512                         outb_p(command, SMBHSTCMD(priv));
 513                 xact = I801_BYTE;
 514                 break;
 515         case I2C_SMBUS_BYTE_DATA:
 516                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 517                        SMBHSTADD(priv));
 518                 outb_p(command, SMBHSTCMD(priv));
 519                 if (read_write == I2C_SMBUS_WRITE)
 520                         outb_p(data->byte, SMBHSTDAT0(priv));
 521                 xact = I801_BYTE_DATA;
 522                 break;
 523         case I2C_SMBUS_WORD_DATA:
 524                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 525                        SMBHSTADD(priv));
 526                 outb_p(command, SMBHSTCMD(priv));
 527                 if (read_write == I2C_SMBUS_WRITE) {
 528                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 529                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 530                 }
 531                 xact = I801_WORD_DATA;
 532                 break;
 533         case I2C_SMBUS_BLOCK_DATA:
 534                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 535                        SMBHSTADD(priv));
 536                 outb_p(command, SMBHSTCMD(priv));
 537                 block = 1;
 538                 break;
 539         case I2C_SMBUS_I2C_BLOCK_DATA:
 540                 /* NB: page 240 of ICH5 datasheet shows that the R/#W
 541                  * bit should be cleared here, even when reading */
 542                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 543                 if (read_write == I2C_SMBUS_READ) {
 544                         /* NB: page 240 of ICH5 datasheet also shows
 545                          * that DATA1 is the cmd field when reading */
 546                         outb_p(command, SMBHSTDAT1(priv));
 547                 } else
 548                         outb_p(command, SMBHSTCMD(priv));
 549                 block = 1;
 550                 break;
 551         default:
 552                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 553                         size);
 554                 return -EOPNOTSUPP;
 555         }
 556
 557         if (hwpec)      /* enable/disable hardware PEC */
 558                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 559         else
 560                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 561                        SMBAUXCTL(priv));
 562
 563         if (block)
 564                 ret = i801_block_transaction(priv, data, read_write, size,
 565                                              hwpec);
 566         else
 567                 ret = i801_transaction(priv, xact | ENABLE_INT9);
 568
 569         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 570            time, so we forcibly disable it after every transaction. Turn off
 571            E32B for the same reason. */
 572         if (hwpec || block)
 573                 outb_p(inb_p(SMBAUXCTL(priv)) &
 574                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 575
 576         if (block)
 577                 return ret;
 578         if (ret)
 579                 return ret;
 580         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 581                 return 0;
 582
 583         switch (xact & 0x7f) {
 584         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 585         case I801_BYTE_DATA:
 586                 data->byte = inb_p(SMBHSTDAT0(priv));
 587                 break;
 588         case I801_WORD_DATA:
 589                 data->word = inb_p(SMBHSTDAT0(priv)) +
 590                              (inb_p(SMBHSTDAT1(priv)) << 8);
 591                 break;
 592         }
 593         return 0;
 594 }
 595
 596
 597 static u32 i801_func(struct i2c_adapter *adapter)
 598 {
 599         struct i801_priv *priv = i2c_get_adapdata(adapter);
 600
 601         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 602                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 603                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 604                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 605                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 606                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
 607 }
 608
 609 static const struct i2c_algorithm smbus_algorithm = {
 610         .smbus_xfer     = i801_access,
 611         .functionality  = i801_func,
 612 };
 613
 614 static DEFINE_PCI_DEVICE_TABLE(i801_ids) = {
 615         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 616         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 617         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 618         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 619         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 620         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 621         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 622         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 623         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 624         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 625         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 626         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
 627         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
 628         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
 629         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
 630         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
 631         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
 632         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
 633         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
 634         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
 635         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
 636         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
 637         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
 638         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
 639         { 0, }
 640 };
 641
 642 MODULE_DEVICE_TABLE(pci, i801_ids);
 643
 644 #if defined CONFIG_X86 && defined CONFIG_DMI
 645 static unsigned char apanel_addr;
 646
 647 /* Scan the system ROM for the signature "FJKEYINF" */
 648 static __init const void __iomem *bios_signature(const void __iomem *bios)
 649 {
 650         ssize_t offset;
 651         const unsigned char signature[] = "FJKEYINF";
 652
 653         for (offset = 0; offset < 0x10000; offset += 0x10) {
 654                 if (check_signature(bios + offset, signature,
 655                                     sizeof(signature)-1))
 656                         return bios + offset;
 657         }
 658         return NULL;
 659 }
 660
 661 static void __init input_apanel_init(void)
 662 {
 663         void __iomem *bios;
 664         const void __iomem *p;
 665
 666         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
 667         p = bios_signature(bios);
 668         if (p) {
 669                 /* just use the first address */
 670                 apanel_addr = readb(p + 8 + 3) >> 1;
 671         }
 672         iounmap(bios);
 673 }
 674
 675 struct dmi_onboard_device_info {
 676         const char *name;
 677         u8 type;
 678         unsigned short i2c_addr;
 679         const char *i2c_type;
 680 };
 681
 682 static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
 683         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
 684         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
 685         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
 686 };
 687
 688 static void __devinit dmi_check_onboard_device(u8 type, const char *name,
 689                                                struct i2c_adapter *adap)
 690 {
 691         int i;
 692         struct i2c_board_info info;
 693
 694         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
 695                 /* & ~0x80, ignore enabled/disabled bit */
 696                 if ((type & ~0x80) != dmi_devices[i].type)
 697                         continue;
 698                 if (strcasecmp(name, dmi_devices[i].name))
 699                         continue;
 700
 701                 memset(&info, 0, sizeof(struct i2c_board_info));
 702                 info.addr = dmi_devices[i].i2c_addr;
 703                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
 704                 i2c_new_device(adap, &info);
 705                 break;
 706         }
 707 }
 708
 709 /* We use our own function to check for onboard devices instead of
 710    dmi_find_device() as some buggy BIOS's have the devices we are interested
 711    in marked as disabled */
 712 static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
 713                                                 void *adap)
 714 {
 715         int i, count;
 716
 717         if (dm->type != 10)
 718                 return;
 719
 720         count = (dm->length - sizeof(struct dmi_header)) / 2;
 721         for (i = 0; i < count; i++) {
 722                 const u8 *d = (char *)(dm + 1) + (i * 2);
 723                 const char *name = ((char *) dm) + dm->length;
 724                 u8 type = d[0];
 725                 u8 s = d[1];
 726
 727                 if (!s)
 728                         continue;
 729                 s--;
 730                 while (s > 0 && name[0]) {
 731                         name += strlen(name) + 1;
 732                         s--;
 733                 }
 734                 if (name[0] == 0) /* Bogus string reference */
 735                         continue;
 736
 737                 dmi_check_onboard_device(type, name, adap);
 738         }
 739 }
 740
 741 /* Register optional slaves */
 742 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv)
 743 {
 744         /* Only register slaves on main SMBus channel */
 745         if (priv->features & FEATURE_IDF)
 746                 return;
 747
 748         if (apanel_addr) {
 749                 struct i2c_board_info info;
 750
 751                 memset(&info, 0, sizeof(struct i2c_board_info));
 752                 info.addr = apanel_addr;
 753                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
 754                 i2c_new_device(&priv->adapter, &info);
 755         }
 756
 757         if (dmi_name_in_vendors("FUJITSU"))
 758                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
 759 }
 760 #else
 761 static void __init input_apanel_init(void) {}
 762 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) {}
 763 #endif  /* CONFIG_X86 && CONFIG_DMI */
 764
 765 static int __devinit i801_probe(struct pci_dev *dev,
 766                                 const struct pci_device_id *id)
 767 {
 768         unsigned char temp;
 769         int err, i;
 770         struct i801_priv *priv;
 771
 772         priv = kzalloc(sizeof(*priv), GFP_KERNEL);
 773         if (!priv)
 774                 return -ENOMEM;
 775
 776         i2c_set_adapdata(&priv->adapter, priv);
 777         priv->adapter.owner = THIS_MODULE;
 778         priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
 779         priv->adapter.algo = &smbus_algorithm;
 780
 781         priv->pci_dev = dev;
 782         switch (dev->device) {
 783         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
 784         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
 785         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
 786                 priv->features |= FEATURE_IDF;
 787                 /* fall through */
 788         default:
 789                 priv->features |= FEATURE_I2C_BLOCK_READ;
 790                 /* fall through */
 791         case PCI_DEVICE_ID_INTEL_82801DB_3:
 792                 priv->features |= FEATURE_SMBUS_PEC;
 793                 priv->features |= FEATURE_BLOCK_BUFFER;
 794                 /* fall through */
 795         case PCI_DEVICE_ID_INTEL_82801CA_3:
 796         case PCI_DEVICE_ID_INTEL_82801BA_2:
 797         case PCI_DEVICE_ID_INTEL_82801AB_3:
 798         case PCI_DEVICE_ID_INTEL_82801AA_3:
 799                 break;
 800         }
 801
 802         /* Disable features on user request */
 803         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
 804                 if (priv->features & disable_features & (1 << i))
 805                         dev_notice(&dev->dev, "%s disabled by user\n",
 806                                    i801_feature_names[i]);
 807         }
 808         priv->features &= ~disable_features;
 809
 810         err = pci_enable_device(dev);
 811         if (err) {
 812                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
 813                         err);
 814                 goto exit;
 815         }
 816
 817         /* Determine the address of the SMBus area */
 818         priv->smba = pci_resource_start(dev, SMBBAR);
 819         if (!priv->smba) {
 820                 dev_err(&dev->dev, "SMBus base address uninitialized, "
 821                         "upgrade BIOS\n");
 822                 err = -ENODEV;
 823                 goto exit;
 824         }
 825
 826         err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
 827         if (err) {
 828                 err = -ENODEV;
 829                 goto exit;
 830         }
 831
 832         err = pci_request_region(dev, SMBBAR, i801_driver.name);
 833         if (err) {
 834                 dev_err(&dev->dev, "Failed to request SMBus region "
 835                         "0x%lx-0x%Lx\n", priv->smba,
 836                         (unsigned long long)pci_resource_end(dev, SMBBAR));
 837                 goto exit;
 838         }
 839
 840         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
 841         priv->original_hstcfg = temp;
 842         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
 843         if (!(temp & SMBHSTCFG_HST_EN)) {
 844                 dev_info(&dev->dev, "Enabling SMBus device\n");
 845                 temp |= SMBHSTCFG_HST_EN;
 846         }
 847         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
 848
 849         if (temp & SMBHSTCFG_SMB_SMI_EN)
 850                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
 851         else
 852                 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
 853
 854         /* Clear special mode bits */
 855         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
 856                 outb_p(inb_p(SMBAUXCTL(priv)) &
 857                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 858
 859         /* set up the sysfs linkage to our parent device */
 860         priv->adapter.dev.parent = &dev->dev;
 861
 862         /* Retry up to 3 times on lost arbitration */
 863         priv->adapter.retries = 3;
 864
 865         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
 866                 "SMBus I801 adapter at %04lx", priv->smba);
 867         err = i2c_add_adapter(&priv->adapter);
 868         if (err) {
 869                 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
 870                 goto exit_release;
 871         }
 872
 873         i801_probe_optional_slaves(priv);
 874
 875         pci_set_drvdata(dev, priv);
 876         return 0;
 877
 878 exit_release:
 879         pci_release_region(dev, SMBBAR);
 880 exit:
 881         kfree(priv);
 882         return err;
 883 }
 884
 885 static void __devexit i801_remove(struct pci_dev *dev)
 886 {
 887         struct i801_priv *priv = pci_get_drvdata(dev);
 888
 889         i2c_del_adapter(&priv->adapter);
 890         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
 891         pci_release_region(dev, SMBBAR);
 892         pci_set_drvdata(dev, NULL);
 893         kfree(priv);
 894         /*
 895          * do not call pci_disable_device(dev) since it can cause hard hangs on
 896          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
 897          */
 898 }
 899
 900 #ifdef CONFIG_PM
 901 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
 902 {
 903         struct i801_priv *priv = pci_get_drvdata(dev);
 904
 905         pci_save_state(dev);
 906         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
 907         pci_set_power_state(dev, pci_choose_state(dev, mesg));
 908         return 0;
 909 }
 910
 911 static int i801_resume(struct pci_dev *dev)
 912 {
 913         pci_set_power_state(dev, PCI_D0);
 914         pci_restore_state(dev);
 915         return pci_enable_device(dev);
 916 }
 917 #else
 918 #define i801_suspend NULL
 919 #define i801_resume NULL
 920 #endif
 921
 922 static struct pci_driver i801_driver = {
 923         .name           = "i801_smbus",
 924         .id_table       = i801_ids,
 925         .probe          = i801_probe,
 926         .remove         = __devexit_p(i801_remove),
 927         .suspend        = i801_suspend,
 928         .resume         = i801_resume,
 929 };
 930
 931 static int __init i2c_i801_init(void)
 932 {
 933         if (dmi_name_in_vendors("FUJITSU"))
 934                 input_apanel_init();
 935         return pci_register_driver(&i801_driver);
 936 }
 937
 938 static void __exit i2c_i801_exit(void)
 939 {
 940         pci_unregister_driver(&i801_driver);
 941 }
 942
 943 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
 944               "Jean Delvare <khali@linux-fr.org>");
 945 MODULE_DESCRIPTION("I801 SMBus driver");
 946 MODULE_LICENSE("GPL");
 947
 948 module_init(i2c_i801_init);
 949 module_exit(i2c_i801_exit);