2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 Copyright (C) 2007 - 2012 Jean Delvare <khali@linux-fr.org>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 Supports the following Intel I/O Controller Hubs (ICH):
28 region SMBus Block proc. block
29 Chip name PCI ID size PEC buffer call read
30 ----------------------------------------------------------------------
31 82801AA (ICH) 0x2413 16 no no no no
32 82801AB (ICH0) 0x2423 16 no no no no
33 82801BA (ICH2) 0x2443 16 no no no no
34 82801CA (ICH3) 0x2483 32 soft no no no
35 82801DB (ICH4) 0x24c3 32 hard yes no no
36 82801E (ICH5) 0x24d3 32 hard yes yes yes
37 6300ESB 0x25a4 32 hard yes yes yes
38 82801F (ICH6) 0x266a 32 hard yes yes yes
39 6310ESB/6320ESB 0x269b 32 hard yes yes yes
40 82801G (ICH7) 0x27da 32 hard yes yes yes
41 82801H (ICH8) 0x283e 32 hard yes yes yes
42 82801I (ICH9) 0x2930 32 hard yes yes yes
43 EP80579 (Tolapai) 0x5032 32 hard yes yes yes
44 ICH10 0x3a30 32 hard yes yes yes
45 ICH10 0x3a60 32 hard yes yes yes
46 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
47 6 Series (PCH) 0x1c22 32 hard yes yes yes
48 Patsburg (PCH) 0x1d22 32 hard yes yes yes
49 Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
50 Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
51 Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
52 DH89xxCC (PCH) 0x2330 32 hard yes yes yes
53 Panther Point (PCH) 0x1e22 32 hard yes yes yes
54 Lynx Point (PCH) 0x8c22 32 hard yes yes yes
56 Features supported by this driver:
60 Block process call transaction no
61 I2C block read transaction yes (doesn't use the block buffer)
64 See the file Documentation/i2c/busses/i2c-i801 for details.
67 #include <linux/module.h>
68 #include <linux/pci.h>
69 #include <linux/kernel.h>
70 #include <linux/stddef.h>
71 #include <linux/delay.h>
72 #include <linux/ioport.h>
73 #include <linux/init.h>
74 #include <linux/i2c.h>
75 #include <linux/acpi.h>
77 #include <linux/dmi.h>
78 #include <linux/slab.h>
80 /* I801 SMBus address offsets */
81 #define SMBHSTSTS(p) (0 + (p)->smba)
82 #define SMBHSTCNT(p) (2 + (p)->smba)
83 #define SMBHSTCMD(p) (3 + (p)->smba)
84 #define SMBHSTADD(p) (4 + (p)->smba)
85 #define SMBHSTDAT0(p) (5 + (p)->smba)
86 #define SMBHSTDAT1(p) (6 + (p)->smba)
87 #define SMBBLKDAT(p) (7 + (p)->smba)
88 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
89 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
90 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
92 /* PCI Address Constants */
94 #define SMBHSTCFG 0x040
96 /* Host configuration bits for SMBHSTCFG */
97 #define SMBHSTCFG_HST_EN 1
98 #define SMBHSTCFG_SMB_SMI_EN 2
99 #define SMBHSTCFG_I2C_EN 4
101 /* Auxiliary control register bits, ICH4+ only */
102 #define SMBAUXCTL_CRC 1
103 #define SMBAUXCTL_E32B 2
105 /* kill bit for SMBHSTCNT */
106 #define SMBHSTCNT_KILL 2
109 #define MAX_RETRIES 400
110 #define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
112 /* I801 command constants */
113 #define I801_QUICK 0x00
114 #define I801_BYTE 0x04
115 #define I801_BYTE_DATA 0x08
116 #define I801_WORD_DATA 0x0C
117 #define I801_PROC_CALL 0x10 /* unimplemented */
118 #define I801_BLOCK_DATA 0x14
119 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
120 #define I801_LAST_BYTE 0x20
121 #define I801_START 0x40
122 #define I801_PEC_EN 0x80 /* ICH3 and later */
124 /* I801 Hosts Status register bits */
125 #define SMBHSTSTS_BYTE_DONE 0x80
126 #define SMBHSTSTS_INUSE_STS 0x40
127 #define SMBHSTSTS_SMBALERT_STS 0x20
128 #define SMBHSTSTS_FAILED 0x10
129 #define SMBHSTSTS_BUS_ERR 0x08
130 #define SMBHSTSTS_DEV_ERR 0x04
131 #define SMBHSTSTS_INTR 0x02
132 #define SMBHSTSTS_HOST_BUSY 0x01
134 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
137 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
140 /* Older devices have their ID defined in <linux/pci_ids.h> */
141 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
142 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
143 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
144 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
145 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
146 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
147 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
148 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
149 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
150 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
153 struct i2c_adapter adapter;
155 unsigned char original_hstcfg;
156 struct pci_dev *pci_dev;
157 unsigned int features;
160 static struct pci_driver i801_driver;
162 #define FEATURE_SMBUS_PEC (1 << 0)
163 #define FEATURE_BLOCK_BUFFER (1 << 1)
164 #define FEATURE_BLOCK_PROC (1 << 2)
165 #define FEATURE_I2C_BLOCK_READ (1 << 3)
166 /* Not really a feature, but it's convenient to handle it as such */
167 #define FEATURE_IDF (1 << 15)
169 static const char *i801_feature_names[] = {
172 "Block process call",
176 static unsigned int disable_features;
177 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
178 MODULE_PARM_DESC(disable_features, "Disable selected driver features");
180 /* Make sure the SMBus host is ready to start transmitting.
181 Return 0 if it is, -EBUSY if it is not. */
182 static int i801_check_pre(struct i801_priv *priv)
186 status = inb_p(SMBHSTSTS(priv));
187 if (status & SMBHSTSTS_HOST_BUSY) {
188 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
192 status &= STATUS_FLAGS;
194 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
196 outb_p(status, SMBHSTSTS(priv));
197 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
199 dev_err(&priv->pci_dev->dev,
200 "Failed clearing status flags (%02x)\n",
209 /* Convert the status register to an error code, and clear it. */
210 static int i801_check_post(struct i801_priv *priv, int status, int timeout)
214 /* If the SMBus is still busy, we give up */
216 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
217 /* try to stop the current command */
218 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
219 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
221 usleep_range(1000, 2000);
222 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
225 /* Check if it worked */
226 status = inb_p(SMBHSTSTS(priv));
227 if ((status & SMBHSTSTS_HOST_BUSY) ||
228 !(status & SMBHSTSTS_FAILED))
229 dev_err(&priv->pci_dev->dev,
230 "Failed terminating the transaction\n");
231 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
235 if (status & SMBHSTSTS_FAILED) {
237 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
239 if (status & SMBHSTSTS_DEV_ERR) {
241 dev_dbg(&priv->pci_dev->dev, "No response\n");
243 if (status & SMBHSTSTS_BUS_ERR) {
245 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
249 /* Clear error flags */
250 outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv));
251 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
253 dev_warn(&priv->pci_dev->dev, "Failed clearing status "
254 "flags at end of transaction (%02x)\n",
262 static int i801_transaction(struct i801_priv *priv, int xact)
268 result = i801_check_pre(priv);
272 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
273 * INTREN, SMBSCMD are passed in xact */
274 outb_p(xact | I801_START, SMBHSTCNT(priv));
276 /* We will always wait for a fraction of a second! */
278 usleep_range(250, 500);
279 status = inb_p(SMBHSTSTS(priv));
280 } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_RETRIES));
282 result = i801_check_post(priv, status, timeout > MAX_RETRIES);
286 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
290 /* wait for INTR bit as advised by Intel */
291 static void i801_wait_hwpec(struct i801_priv *priv)
297 usleep_range(250, 500);
298 status = inb_p(SMBHSTSTS(priv));
299 } while ((!(status & SMBHSTSTS_INTR))
300 && (timeout++ < MAX_RETRIES));
302 if (timeout > MAX_RETRIES)
303 dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n");
305 outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv));
308 static int i801_block_transaction_by_block(struct i801_priv *priv,
309 union i2c_smbus_data *data,
310 char read_write, int hwpec)
315 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
317 /* Use 32-byte buffer to process this transaction */
318 if (read_write == I2C_SMBUS_WRITE) {
319 len = data->block[0];
320 outb_p(len, SMBHSTDAT0(priv));
321 for (i = 0; i < len; i++)
322 outb_p(data->block[i+1], SMBBLKDAT(priv));
325 status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 |
326 I801_PEC_EN * hwpec);
330 if (read_write == I2C_SMBUS_READ) {
331 len = inb_p(SMBHSTDAT0(priv));
332 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
335 data->block[0] = len;
336 for (i = 0; i < len; i++)
337 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
343 * For "byte-by-byte" block transactions:
344 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
345 * I2C read uses cmd=I801_I2C_BLOCK_DATA
347 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
348 union i2c_smbus_data *data,
349 char read_write, int command,
358 result = i801_check_pre(priv);
362 len = data->block[0];
364 if (read_write == I2C_SMBUS_WRITE) {
365 outb_p(len, SMBHSTDAT0(priv));
366 outb_p(data->block[1], SMBBLKDAT(priv));
369 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
370 read_write == I2C_SMBUS_READ)
371 smbcmd = I801_I2C_BLOCK_DATA;
373 smbcmd = I801_BLOCK_DATA;
375 for (i = 1; i <= len; i++) {
376 if (i == len && read_write == I2C_SMBUS_READ)
377 smbcmd |= I801_LAST_BYTE;
378 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv));
381 outb_p(inb(SMBHSTCNT(priv)) | I801_START,
384 /* We will always wait for a fraction of a second! */
387 usleep_range(250, 500);
388 status = inb_p(SMBHSTSTS(priv));
389 } while (!(status & (SMBHSTSTS_BYTE_DONE | STATUS_ERROR_FLAGS))
390 && (timeout++ < MAX_RETRIES));
392 result = i801_check_post(priv, status, timeout > MAX_RETRIES);
396 if (i == 1 && read_write == I2C_SMBUS_READ
397 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
398 len = inb_p(SMBHSTDAT0(priv));
399 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
400 dev_err(&priv->pci_dev->dev,
401 "Illegal SMBus block read size %d\n",
404 while (inb_p(SMBHSTSTS(priv)) &
406 outb_p(SMBHSTSTS_BYTE_DONE,
408 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
411 data->block[0] = len;
414 /* Retrieve/store value in SMBBLKDAT */
415 if (read_write == I2C_SMBUS_READ)
416 data->block[i] = inb_p(SMBBLKDAT(priv));
417 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
418 outb_p(data->block[i+1], SMBBLKDAT(priv));
420 /* signals SMBBLKDAT ready */
421 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv));
427 static int i801_set_block_buffer_mode(struct i801_priv *priv)
429 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
430 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
435 /* Block transaction function */
436 static int i801_block_transaction(struct i801_priv *priv,
437 union i2c_smbus_data *data, char read_write,
438 int command, int hwpec)
443 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
444 if (read_write == I2C_SMBUS_WRITE) {
445 /* set I2C_EN bit in configuration register */
446 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
447 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
448 hostc | SMBHSTCFG_I2C_EN);
449 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
450 dev_err(&priv->pci_dev->dev,
451 "I2C block read is unsupported!\n");
456 if (read_write == I2C_SMBUS_WRITE
457 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
458 if (data->block[0] < 1)
460 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
461 data->block[0] = I2C_SMBUS_BLOCK_MAX;
463 data->block[0] = 32; /* max for SMBus block reads */
466 /* Experience has shown that the block buffer can only be used for
467 SMBus (not I2C) block transactions, even though the datasheet
468 doesn't mention this limitation. */
469 if ((priv->features & FEATURE_BLOCK_BUFFER)
470 && command != I2C_SMBUS_I2C_BLOCK_DATA
471 && i801_set_block_buffer_mode(priv) == 0)
472 result = i801_block_transaction_by_block(priv, data,
475 result = i801_block_transaction_byte_by_byte(priv, data,
479 if (result == 0 && hwpec)
480 i801_wait_hwpec(priv);
482 if (command == I2C_SMBUS_I2C_BLOCK_DATA
483 && read_write == I2C_SMBUS_WRITE) {
484 /* restore saved configuration register value */
485 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
490 /* Return negative errno on error. */
491 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
492 unsigned short flags, char read_write, u8 command,
493 int size, union i2c_smbus_data *data)
498 struct i801_priv *priv = i2c_get_adapdata(adap);
500 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
501 && size != I2C_SMBUS_QUICK
502 && size != I2C_SMBUS_I2C_BLOCK_DATA;
505 case I2C_SMBUS_QUICK:
506 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
511 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
513 if (read_write == I2C_SMBUS_WRITE)
514 outb_p(command, SMBHSTCMD(priv));
517 case I2C_SMBUS_BYTE_DATA:
518 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
520 outb_p(command, SMBHSTCMD(priv));
521 if (read_write == I2C_SMBUS_WRITE)
522 outb_p(data->byte, SMBHSTDAT0(priv));
523 xact = I801_BYTE_DATA;
525 case I2C_SMBUS_WORD_DATA:
526 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
528 outb_p(command, SMBHSTCMD(priv));
529 if (read_write == I2C_SMBUS_WRITE) {
530 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
531 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
533 xact = I801_WORD_DATA;
535 case I2C_SMBUS_BLOCK_DATA:
536 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
538 outb_p(command, SMBHSTCMD(priv));
541 case I2C_SMBUS_I2C_BLOCK_DATA:
542 /* NB: page 240 of ICH5 datasheet shows that the R/#W
543 * bit should be cleared here, even when reading */
544 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
545 if (read_write == I2C_SMBUS_READ) {
546 /* NB: page 240 of ICH5 datasheet also shows
547 * that DATA1 is the cmd field when reading */
548 outb_p(command, SMBHSTDAT1(priv));
550 outb_p(command, SMBHSTCMD(priv));
554 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
559 if (hwpec) /* enable/disable hardware PEC */
560 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
562 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
566 ret = i801_block_transaction(priv, data, read_write, size,
569 ret = i801_transaction(priv, xact | ENABLE_INT9);
571 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
572 time, so we forcibly disable it after every transaction. Turn off
573 E32B for the same reason. */
575 outb_p(inb_p(SMBAUXCTL(priv)) &
576 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
582 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
585 switch (xact & 0x7f) {
586 case I801_BYTE: /* Result put in SMBHSTDAT0 */
588 data->byte = inb_p(SMBHSTDAT0(priv));
591 data->word = inb_p(SMBHSTDAT0(priv)) +
592 (inb_p(SMBHSTDAT1(priv)) << 8);
599 static u32 i801_func(struct i2c_adapter *adapter)
601 struct i801_priv *priv = i2c_get_adapdata(adapter);
603 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
604 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
605 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
606 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
607 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
608 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
611 static const struct i2c_algorithm smbus_algorithm = {
612 .smbus_xfer = i801_access,
613 .functionality = i801_func,
616 static DEFINE_PCI_DEVICE_TABLE(i801_ids) = {
617 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
618 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
619 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
620 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
621 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
622 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
623 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
624 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
625 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
626 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
627 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
628 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
629 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
630 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
631 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
632 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
633 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
634 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
635 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
636 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
637 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
638 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
639 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
640 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
644 MODULE_DEVICE_TABLE(pci, i801_ids);
646 #if defined CONFIG_X86 && defined CONFIG_DMI
647 static unsigned char apanel_addr;
649 /* Scan the system ROM for the signature "FJKEYINF" */
650 static __init const void __iomem *bios_signature(const void __iomem *bios)
653 const unsigned char signature[] = "FJKEYINF";
655 for (offset = 0; offset < 0x10000; offset += 0x10) {
656 if (check_signature(bios + offset, signature,
657 sizeof(signature)-1))
658 return bios + offset;
663 static void __init input_apanel_init(void)
666 const void __iomem *p;
668 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
669 p = bios_signature(bios);
671 /* just use the first address */
672 apanel_addr = readb(p + 8 + 3) >> 1;
677 struct dmi_onboard_device_info {
680 unsigned short i2c_addr;
681 const char *i2c_type;
684 static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
685 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
686 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
687 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
690 static void __devinit dmi_check_onboard_device(u8 type, const char *name,
691 struct i2c_adapter *adap)
694 struct i2c_board_info info;
696 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
697 /* & ~0x80, ignore enabled/disabled bit */
698 if ((type & ~0x80) != dmi_devices[i].type)
700 if (strcasecmp(name, dmi_devices[i].name))
703 memset(&info, 0, sizeof(struct i2c_board_info));
704 info.addr = dmi_devices[i].i2c_addr;
705 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
706 i2c_new_device(adap, &info);
711 /* We use our own function to check for onboard devices instead of
712 dmi_find_device() as some buggy BIOS's have the devices we are interested
713 in marked as disabled */
714 static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
722 count = (dm->length - sizeof(struct dmi_header)) / 2;
723 for (i = 0; i < count; i++) {
724 const u8 *d = (char *)(dm + 1) + (i * 2);
725 const char *name = ((char *) dm) + dm->length;
732 while (s > 0 && name[0]) {
733 name += strlen(name) + 1;
736 if (name[0] == 0) /* Bogus string reference */
739 dmi_check_onboard_device(type, name, adap);
743 /* Register optional slaves */
744 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv)
746 /* Only register slaves on main SMBus channel */
747 if (priv->features & FEATURE_IDF)
751 struct i2c_board_info info;
753 memset(&info, 0, sizeof(struct i2c_board_info));
754 info.addr = apanel_addr;
755 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
756 i2c_new_device(&priv->adapter, &info);
759 if (dmi_name_in_vendors("FUJITSU"))
760 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
763 static void __init input_apanel_init(void) {}
764 static void __devinit i801_probe_optional_slaves(struct i801_priv *priv) {}
765 #endif /* CONFIG_X86 && CONFIG_DMI */
767 static int __devinit i801_probe(struct pci_dev *dev,
768 const struct pci_device_id *id)
772 struct i801_priv *priv;
774 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
778 i2c_set_adapdata(&priv->adapter, priv);
779 priv->adapter.owner = THIS_MODULE;
780 priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
781 priv->adapter.algo = &smbus_algorithm;
784 switch (dev->device) {
785 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
786 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
787 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
788 priv->features |= FEATURE_IDF;
791 priv->features |= FEATURE_I2C_BLOCK_READ;
793 case PCI_DEVICE_ID_INTEL_82801DB_3:
794 priv->features |= FEATURE_SMBUS_PEC;
795 priv->features |= FEATURE_BLOCK_BUFFER;
797 case PCI_DEVICE_ID_INTEL_82801CA_3:
798 case PCI_DEVICE_ID_INTEL_82801BA_2:
799 case PCI_DEVICE_ID_INTEL_82801AB_3:
800 case PCI_DEVICE_ID_INTEL_82801AA_3:
804 /* Disable features on user request */
805 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
806 if (priv->features & disable_features & (1 << i))
807 dev_notice(&dev->dev, "%s disabled by user\n",
808 i801_feature_names[i]);
810 priv->features &= ~disable_features;
812 err = pci_enable_device(dev);
814 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
819 /* Determine the address of the SMBus area */
820 priv->smba = pci_resource_start(dev, SMBBAR);
822 dev_err(&dev->dev, "SMBus base address uninitialized, "
828 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
834 err = pci_request_region(dev, SMBBAR, i801_driver.name);
836 dev_err(&dev->dev, "Failed to request SMBus region "
837 "0x%lx-0x%Lx\n", priv->smba,
838 (unsigned long long)pci_resource_end(dev, SMBBAR));
842 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
843 priv->original_hstcfg = temp;
844 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
845 if (!(temp & SMBHSTCFG_HST_EN)) {
846 dev_info(&dev->dev, "Enabling SMBus device\n");
847 temp |= SMBHSTCFG_HST_EN;
849 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
851 if (temp & SMBHSTCFG_SMB_SMI_EN)
852 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
854 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
856 /* Clear special mode bits */
857 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
858 outb_p(inb_p(SMBAUXCTL(priv)) &
859 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
861 /* set up the sysfs linkage to our parent device */
862 priv->adapter.dev.parent = &dev->dev;
864 /* Retry up to 3 times on lost arbitration */
865 priv->adapter.retries = 3;
867 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
868 "SMBus I801 adapter at %04lx", priv->smba);
869 err = i2c_add_adapter(&priv->adapter);
871 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
875 i801_probe_optional_slaves(priv);
877 pci_set_drvdata(dev, priv);
881 pci_release_region(dev, SMBBAR);
887 static void __devexit i801_remove(struct pci_dev *dev)
889 struct i801_priv *priv = pci_get_drvdata(dev);
891 i2c_del_adapter(&priv->adapter);
892 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
893 pci_release_region(dev, SMBBAR);
894 pci_set_drvdata(dev, NULL);
897 * do not call pci_disable_device(dev) since it can cause hard hangs on
898 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
903 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
905 struct i801_priv *priv = pci_get_drvdata(dev);
908 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
909 pci_set_power_state(dev, pci_choose_state(dev, mesg));
913 static int i801_resume(struct pci_dev *dev)
915 pci_set_power_state(dev, PCI_D0);
916 pci_restore_state(dev);
917 return pci_enable_device(dev);
920 #define i801_suspend NULL
921 #define i801_resume NULL
924 static struct pci_driver i801_driver = {
925 .name = "i801_smbus",
926 .id_table = i801_ids,
928 .remove = __devexit_p(i801_remove),
929 .suspend = i801_suspend,
930 .resume = i801_resume,
933 static int __init i2c_i801_init(void)
935 if (dmi_name_in_vendors("FUJITSU"))
937 return pci_register_driver(&i801_driver);
940 static void __exit i2c_i801_exit(void)
942 pci_unregister_driver(&i801_driver);
945 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
946 "Jean Delvare <khali@linux-fr.org>");
947 MODULE_DESCRIPTION("I801 SMBus driver");
948 MODULE_LICENSE("GPL");
950 module_init(i2c_i801_init);
951 module_exit(i2c_i801_exit);