drivers/i2c/busses/i2c-i801.c

   1 /*
   2     Copyright (c) 1998 - 2002  Frodo Looijaard <frodol@dds.nl>,
   3     Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
   4     <mdsxyz123@yahoo.com>
   5     Copyright (C) 2007 - 2014  Jean Delvare <jdelvare@suse.de>
   6     Copyright (C) 2010         Intel Corporation,
   7                                David Woodhouse <dwmw2@infradead.org>
   8
   9     This program is free software; you can redistribute it and/or modify
  10     it under the terms of the GNU General Public License as published by
  11     the Free Software Foundation; either version 2 of the License, or
  12     (at your option) any later version.
  13
  14     This program is distributed in the hope that it will be useful,
  15     but WITHOUT ANY WARRANTY; without even the implied warranty of
  16     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17     GNU General Public License for more details.
  18 */
  19
  20 /*
  21  * Supports the following Intel I/O Controller Hubs (ICH):
  22  *
  23  *                                      I/O                     Block   I2C
  24  *                                      region  SMBus   Block   proc.   block
  25  * Chip name                    PCI ID  size    PEC     buffer  call    read
  26  * ---------------------------------------------------------------------------
  27  * 82801AA (ICH)                0x2413  16      no      no      no      no
  28  * 82801AB (ICH0)               0x2423  16      no      no      no      no
  29  * 82801BA (ICH2)               0x2443  16      no      no      no      no
  30  * 82801CA (ICH3)               0x2483  32      soft    no      no      no
  31  * 82801DB (ICH4)               0x24c3  32      hard    yes     no      no
  32  * 82801E (ICH5)                0x24d3  32      hard    yes     yes     yes
  33  * 6300ESB                      0x25a4  32      hard    yes     yes     yes
  34  * 82801F (ICH6)                0x266a  32      hard    yes     yes     yes
  35  * 6310ESB/6320ESB              0x269b  32      hard    yes     yes     yes
  36  * 82801G (ICH7)                0x27da  32      hard    yes     yes     yes
  37  * 82801H (ICH8)                0x283e  32      hard    yes     yes     yes
  38  * 82801I (ICH9)                0x2930  32      hard    yes     yes     yes
  39  * EP80579 (Tolapai)            0x5032  32      hard    yes     yes     yes
  40  * ICH10                        0x3a30  32      hard    yes     yes     yes
  41  * ICH10                        0x3a60  32      hard    yes     yes     yes
  42  * 5/3400 Series (PCH)          0x3b30  32      hard    yes     yes     yes
  43  * 6 Series (PCH)               0x1c22  32      hard    yes     yes     yes
  44  * Patsburg (PCH)               0x1d22  32      hard    yes     yes     yes
  45  * Patsburg (PCH) IDF           0x1d70  32      hard    yes     yes     yes
  46  * Patsburg (PCH) IDF           0x1d71  32      hard    yes     yes     yes
  47  * Patsburg (PCH) IDF           0x1d72  32      hard    yes     yes     yes
  48  * DH89xxCC (PCH)               0x2330  32      hard    yes     yes     yes
  49  * Panther Point (PCH)          0x1e22  32      hard    yes     yes     yes
  50  * Lynx Point (PCH)             0x8c22  32      hard    yes     yes     yes
  51  * Lynx Point-LP (PCH)          0x9c22  32      hard    yes     yes     yes
  52  * Avoton (SOC)                 0x1f3c  32      hard    yes     yes     yes
  53  * Wellsburg (PCH)              0x8d22  32      hard    yes     yes     yes
  54  * Wellsburg (PCH) MS           0x8d7d  32      hard    yes     yes     yes
  55  * Wellsburg (PCH) MS           0x8d7e  32      hard    yes     yes     yes
  56  * Wellsburg (PCH) MS           0x8d7f  32      hard    yes     yes     yes
  57  * Coleto Creek (PCH)           0x23b0  32      hard    yes     yes     yes
  58  * Wildcat Point (PCH)          0x8ca2  32      hard    yes     yes     yes
  59  * Wildcat Point-LP (PCH)       0x9ca2  32      hard    yes     yes     yes
  60  * BayTrail (SOC)               0x0f12  32      hard    yes     yes     yes
  61  * Sunrise Point-H (PCH)        0xa123  32      hard    yes     yes     yes
  62  * Sunrise Point-LP (PCH)       0x9d23  32      hard    yes     yes     yes
  63  * DNV (SOC)                    0x19df  32      hard    yes     yes     yes
  64  *
  65  * Features supported by this driver:
  66  * Software PEC                         no
  67  * Hardware PEC                         yes
  68  * Block buffer                         yes
  69  * Block process call transaction       no
  70  * I2C block read transaction           yes (doesn't use the block buffer)
  71  * Slave mode                           no
  72  * Interrupt processing                 yes
  73  *
  74  * See the file Documentation/i2c/busses/i2c-i801 for details.
  75  */
  76
  77 #include <linux/interrupt.h>
  78 #include <linux/module.h>
  79 #include <linux/pci.h>
  80 #include <linux/kernel.h>
  81 #include <linux/stddef.h>
  82 #include <linux/delay.h>
  83 #include <linux/ioport.h>
  84 #include <linux/init.h>
  85 #include <linux/i2c.h>
  86 #include <linux/acpi.h>
  87 #include <linux/io.h>
  88 #include <linux/dmi.h>
  89 #include <linux/slab.h>
  90 #include <linux/wait.h>
  91 #include <linux/err.h>
  92 #include <linux/platform_device.h>
  93 #include <linux/platform_data/itco_wdt.h>
  94
  95 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
  96                 defined CONFIG_DMI
  97 #include <linux/gpio.h>
  98 #include <linux/i2c-mux-gpio.h>
  99 #endif
 100
 101 /* I801 SMBus address offsets */
 102 #define SMBHSTSTS(p)    (0 + (p)->smba)
 103 #define SMBHSTCNT(p)    (2 + (p)->smba)
 104 #define SMBHSTCMD(p)    (3 + (p)->smba)
 105 #define SMBHSTADD(p)    (4 + (p)->smba)
 106 #define SMBHSTDAT0(p)   (5 + (p)->smba)
 107 #define SMBHSTDAT1(p)   (6 + (p)->smba)
 108 #define SMBBLKDAT(p)    (7 + (p)->smba)
 109 #define SMBPEC(p)       (8 + (p)->smba)         /* ICH3 and later */
 110 #define SMBAUXSTS(p)    (12 + (p)->smba)        /* ICH4 and later */
 111 #define SMBAUXCTL(p)    (13 + (p)->smba)        /* ICH4 and later */
 112
 113 /* PCI Address Constants */
 114 #define SMBBAR          4
 115 #define SMBPCICTL       0x004
 116 #define SMBPCISTS       0x006
 117 #define SMBHSTCFG       0x040
 118 #define TCOBASE         0x050
 119 #define TCOCTL          0x054
 120
 121 #define ACPIBASE                0x040
 122 #define ACPIBASE_SMI_OFF        0x030
 123 #define ACPICTRL                0x044
 124 #define ACPICTRL_EN             0x080
 125
 126 #define SBREG_BAR               0x10
 127 #define SBREG_SMBCTRL           0xc6000c
 128
 129 /* Host status bits for SMBPCISTS */
 130 #define SMBPCISTS_INTS          0x08
 131
 132 /* Control bits for SMBPCICTL */
 133 #define SMBPCICTL_INTDIS        0x0400
 134
 135 /* Host configuration bits for SMBHSTCFG */
 136 #define SMBHSTCFG_HST_EN        1
 137 #define SMBHSTCFG_SMB_SMI_EN    2
 138 #define SMBHSTCFG_I2C_EN        4
 139
 140 /* TCO configuration bits for TCOCTL */
 141 #define TCOCTL_EN               0x0100
 142
 143 /* Auxiliary control register bits, ICH4+ only */
 144 #define SMBAUXCTL_CRC           1
 145 #define SMBAUXCTL_E32B          2
 146
 147 /* Other settings */
 148 #define MAX_RETRIES             400
 149
 150 /* I801 command constants */
 151 #define I801_QUICK              0x00
 152 #define I801_BYTE               0x04
 153 #define I801_BYTE_DATA          0x08
 154 #define I801_WORD_DATA          0x0C
 155 #define I801_PROC_CALL          0x10    /* unimplemented */
 156 #define I801_BLOCK_DATA         0x14
 157 #define I801_I2C_BLOCK_DATA     0x18    /* ICH5 and later */
 158
 159 /* I801 Host Control register bits */
 160 #define SMBHSTCNT_INTREN        0x01
 161 #define SMBHSTCNT_KILL          0x02
 162 #define SMBHSTCNT_LAST_BYTE     0x20
 163 #define SMBHSTCNT_START         0x40
 164 #define SMBHSTCNT_PEC_EN        0x80    /* ICH3 and later */
 165
 166 /* I801 Hosts Status register bits */
 167 #define SMBHSTSTS_BYTE_DONE     0x80
 168 #define SMBHSTSTS_INUSE_STS     0x40
 169 #define SMBHSTSTS_SMBALERT_STS  0x20
 170 #define SMBHSTSTS_FAILED        0x10
 171 #define SMBHSTSTS_BUS_ERR       0x08
 172 #define SMBHSTSTS_DEV_ERR       0x04
 173 #define SMBHSTSTS_INTR          0x02
 174 #define SMBHSTSTS_HOST_BUSY     0x01
 175
 176 #define STATUS_ERROR_FLAGS      (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
 177                                  SMBHSTSTS_DEV_ERR)
 178
 179 #define STATUS_FLAGS            (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
 180                                  STATUS_ERROR_FLAGS)
 181
 182 /* Older devices have their ID defined in <linux/pci_ids.h> */
 183 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS              0x0f12
 184 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS              0x2292
 185 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS           0x1c22
 186 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS              0x1d22
 187 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
 188 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0         0x1d70
 189 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1         0x1d71
 190 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2         0x1d72
 191 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS          0x1e22
 192 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS                0x1f3c
 193 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS              0x2330
 194 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS           0x23b0
 195 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS         0x3b30
 196 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS             0x8c22
 197 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS          0x8ca2
 198 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS             0x8d22
 199 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0         0x8d7d
 200 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1         0x8d7e
 201 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2         0x8d7f
 202 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS          0x9c22
 203 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS       0x9ca2
 204 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS        0xa123
 205 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS       0x9d23
 206 #define PCI_DEVICE_ID_INTEL_DNV_SMBUS                   0x19df
 207
 208 struct i801_mux_config {
 209         char *gpio_chip;
 210         unsigned values[3];
 211         int n_values;
 212         unsigned classes[3];
 213         unsigned gpios[2];              /* Relative to gpio_chip->base */
 214         int n_gpios;
 215 };
 216
 217 struct i801_priv {
 218         struct i2c_adapter adapter;
 219         unsigned long smba;
 220         unsigned char original_hstcfg;
 221         struct pci_dev *pci_dev;
 222         unsigned int features;
 223
 224         /* isr processing */
 225         wait_queue_head_t waitq;
 226         u8 status;
 227
 228         /* Command state used by isr for byte-by-byte block transactions */
 229         u8 cmd;
 230         bool is_read;
 231         int count;
 232         int len;
 233         u8 *data;
 234
 235 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
 236                 defined CONFIG_DMI
 237         const struct i801_mux_config *mux_drvdata;
 238         struct platform_device *mux_pdev;
 239 #endif
 240         struct platform_device *tco_pdev;
 241 };
 242
 243 #define FEATURE_SMBUS_PEC       (1 << 0)
 244 #define FEATURE_BLOCK_BUFFER    (1 << 1)
 245 #define FEATURE_BLOCK_PROC      (1 << 2)
 246 #define FEATURE_I2C_BLOCK_READ  (1 << 3)
 247 #define FEATURE_IRQ             (1 << 4)
 248 /* Not really a feature, but it's convenient to handle it as such */
 249 #define FEATURE_IDF             (1 << 15)
 250 #define FEATURE_TCO             (1 << 16)
 251
 252 static const char *i801_feature_names[] = {
 253         "SMBus PEC",
 254         "Block buffer",
 255         "Block process call",
 256         "I2C block read",
 257         "Interrupt",
 258 };
 259
 260 static unsigned int disable_features;
 261 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
 262 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
 263         "\t\t  0x01  disable SMBus PEC\n"
 264         "\t\t  0x02  disable the block buffer\n"
 265         "\t\t  0x08  disable the I2C block read functionality\n"
 266         "\t\t  0x10  don't use interrupts ");
 267
 268 /* Make sure the SMBus host is ready to start transmitting.
 269    Return 0 if it is, -EBUSY if it is not. */
 270 static int i801_check_pre(struct i801_priv *priv)
 271 {
 272         int status;
 273
 274         status = inb_p(SMBHSTSTS(priv));
 275         if (status & SMBHSTSTS_HOST_BUSY) {
 276                 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
 277                 return -EBUSY;
 278         }
 279
 280         status &= STATUS_FLAGS;
 281         if (status) {
 282                 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
 283                         status);
 284                 outb_p(status, SMBHSTSTS(priv));
 285                 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
 286                 if (status) {
 287                         dev_err(&priv->pci_dev->dev,
 288                                 "Failed clearing status flags (%02x)\n",
 289                                 status);
 290                         return -EBUSY;
 291                 }
 292         }
 293
 294         return 0;
 295 }
 296
 297 /*
 298  * Convert the status register to an error code, and clear it.
 299  * Note that status only contains the bits we want to clear, not the
 300  * actual register value.
 301  */
 302 static int i801_check_post(struct i801_priv *priv, int status)
 303 {
 304         int result = 0;
 305
 306         /*
 307          * If the SMBus is still busy, we give up
 308          * Note: This timeout condition only happens when using polling
 309          * transactions.  For interrupt operation, NAK/timeout is indicated by
 310          * DEV_ERR.
 311          */
 312         if (unlikely(status < 0)) {
 313                 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
 314                 /* try to stop the current command */
 315                 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
 316                 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
 317                        SMBHSTCNT(priv));
 318                 usleep_range(1000, 2000);
 319                 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
 320                        SMBHSTCNT(priv));
 321
 322                 /* Check if it worked */
 323                 status = inb_p(SMBHSTSTS(priv));
 324                 if ((status & SMBHSTSTS_HOST_BUSY) ||
 325                     !(status & SMBHSTSTS_FAILED))
 326                         dev_err(&priv->pci_dev->dev,
 327                                 "Failed terminating the transaction\n");
 328                 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
 329                 return -ETIMEDOUT;
 330         }
 331
 332         if (status & SMBHSTSTS_FAILED) {
 333                 result = -EIO;
 334                 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
 335         }
 336         if (status & SMBHSTSTS_DEV_ERR) {
 337                 result = -ENXIO;
 338                 dev_dbg(&priv->pci_dev->dev, "No response\n");
 339         }
 340         if (status & SMBHSTSTS_BUS_ERR) {
 341                 result = -EAGAIN;
 342                 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
 343         }
 344
 345         /* Clear status flags except BYTE_DONE, to be cleared by caller */
 346         outb_p(status, SMBHSTSTS(priv));
 347
 348         return result;
 349 }
 350
 351 /* Wait for BUSY being cleared and either INTR or an error flag being set */
 352 static int i801_wait_intr(struct i801_priv *priv)
 353 {
 354         int timeout = 0;
 355         int status;
 356
 357         /* We will always wait for a fraction of a second! */
 358         do {
 359                 usleep_range(250, 500);
 360                 status = inb_p(SMBHSTSTS(priv));
 361         } while (((status & SMBHSTSTS_HOST_BUSY) ||
 362                   !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
 363                  (timeout++ < MAX_RETRIES));
 364
 365         if (timeout > MAX_RETRIES) {
 366                 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
 367                 return -ETIMEDOUT;
 368         }
 369         return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
 370 }
 371
 372 /* Wait for either BYTE_DONE or an error flag being set */
 373 static int i801_wait_byte_done(struct i801_priv *priv)
 374 {
 375         int timeout = 0;
 376         int status;
 377
 378         /* We will always wait for a fraction of a second! */
 379         do {
 380                 usleep_range(250, 500);
 381                 status = inb_p(SMBHSTSTS(priv));
 382         } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
 383                  (timeout++ < MAX_RETRIES));
 384
 385         if (timeout > MAX_RETRIES) {
 386                 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
 387                 return -ETIMEDOUT;
 388         }
 389         return status & STATUS_ERROR_FLAGS;
 390 }
 391
 392 static int i801_transaction(struct i801_priv *priv, int xact)
 393 {
 394         int status;
 395         int result;
 396         const struct i2c_adapter *adap = &priv->adapter;
 397
 398         result = i801_check_pre(priv);
 399         if (result < 0)
 400                 return result;
 401
 402         if (priv->features & FEATURE_IRQ) {
 403                 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
 404                        SMBHSTCNT(priv));
 405                 result = wait_event_timeout(priv->waitq,
 406                                             (status = priv->status),
 407                                             adap->timeout);
 408                 if (!result) {
 409                         status = -ETIMEDOUT;
 410                         dev_warn(&priv->pci_dev->dev,
 411                                  "Timeout waiting for interrupt!\n");
 412                 }
 413                 priv->status = 0;
 414                 return i801_check_post(priv, status);
 415         }
 416
 417         /* the current contents of SMBHSTCNT can be overwritten, since PEC,
 418          * SMBSCMD are passed in xact */
 419         outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
 420
 421         status = i801_wait_intr(priv);
 422         return i801_check_post(priv, status);
 423 }
 424
 425 static int i801_block_transaction_by_block(struct i801_priv *priv,
 426                                            union i2c_smbus_data *data,
 427                                            char read_write, int hwpec)
 428 {
 429         int i, len;
 430         int status;
 431
 432         inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
 433
 434         /* Use 32-byte buffer to process this transaction */
 435         if (read_write == I2C_SMBUS_WRITE) {
 436                 len = data->block[0];
 437                 outb_p(len, SMBHSTDAT0(priv));
 438                 for (i = 0; i < len; i++)
 439                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 440         }
 441
 442         status = i801_transaction(priv, I801_BLOCK_DATA |
 443                                   (hwpec ? SMBHSTCNT_PEC_EN : 0));
 444         if (status)
 445                 return status;
 446
 447         if (read_write == I2C_SMBUS_READ) {
 448                 len = inb_p(SMBHSTDAT0(priv));
 449                 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
 450                         return -EPROTO;
 451
 452                 data->block[0] = len;
 453                 for (i = 0; i < len; i++)
 454                         data->block[i + 1] = inb_p(SMBBLKDAT(priv));
 455         }
 456         return 0;
 457 }
 458
 459 static void i801_isr_byte_done(struct i801_priv *priv)
 460 {
 461         if (priv->is_read) {
 462                 /* For SMBus block reads, length is received with first byte */
 463                 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
 464                     (priv->count == 0)) {
 465                         priv->len = inb_p(SMBHSTDAT0(priv));
 466                         if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
 467                                 dev_err(&priv->pci_dev->dev,
 468                                         "Illegal SMBus block read size %d\n",
 469                                         priv->len);
 470                                 /* FIXME: Recover */
 471                                 priv->len = I2C_SMBUS_BLOCK_MAX;
 472                         } else {
 473                                 dev_dbg(&priv->pci_dev->dev,
 474                                         "SMBus block read size is %d\n",
 475                                         priv->len);
 476                         }
 477                         priv->data[-1] = priv->len;
 478                 }
 479
 480                 /* Read next byte */
 481                 if (priv->count < priv->len)
 482                         priv->data[priv->count++] = inb(SMBBLKDAT(priv));
 483                 else
 484                         dev_dbg(&priv->pci_dev->dev,
 485                                 "Discarding extra byte on block read\n");
 486
 487                 /* Set LAST_BYTE for last byte of read transaction */
 488                 if (priv->count == priv->len - 1)
 489                         outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
 490                                SMBHSTCNT(priv));
 491         } else if (priv->count < priv->len - 1) {
 492                 /* Write next byte, except for IRQ after last byte */
 493                 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
 494         }
 495
 496         /* Clear BYTE_DONE to continue with next byte */
 497         outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 498 }
 499
 500 /*
 501  * There are two kinds of interrupts:
 502  *
 503  * 1) i801 signals transaction completion with one of these interrupts:
 504  *      INTR - Success
 505  *      DEV_ERR - Invalid command, NAK or communication timeout
 506  *      BUS_ERR - SMI# transaction collision
 507  *      FAILED - transaction was canceled due to a KILL request
 508  *    When any of these occur, update ->status and wake up the waitq.
 509  *    ->status must be cleared before kicking off the next transaction.
 510  *
 511  * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
 512  *    occurs for each byte of a byte-by-byte to prepare the next byte.
 513  */
 514 static irqreturn_t i801_isr(int irq, void *dev_id)
 515 {
 516         struct i801_priv *priv = dev_id;
 517         u16 pcists;
 518         u8 status;
 519
 520         /* Confirm this is our interrupt */
 521         pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
 522         if (!(pcists & SMBPCISTS_INTS))
 523                 return IRQ_NONE;
 524
 525         status = inb_p(SMBHSTSTS(priv));
 526         if (status & SMBHSTSTS_BYTE_DONE)
 527                 i801_isr_byte_done(priv);
 528
 529         /*
 530          * Clear irq sources and report transaction result.
 531          * ->status must be cleared before the next transaction is started.
 532          */
 533         status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
 534         if (status) {
 535                 outb_p(status, SMBHSTSTS(priv));
 536                 priv->status |= status;
 537                 wake_up(&priv->waitq);
 538         }
 539
 540         return IRQ_HANDLED;
 541 }
 542
 543 /*
 544  * For "byte-by-byte" block transactions:
 545  *   I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
 546  *   I2C read uses cmd=I801_I2C_BLOCK_DATA
 547  */
 548 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
 549                                                union i2c_smbus_data *data,
 550                                                char read_write, int command,
 551                                                int hwpec)
 552 {
 553         int i, len;
 554         int smbcmd;
 555         int status;
 556         int result;
 557         const struct i2c_adapter *adap = &priv->adapter;
 558
 559         result = i801_check_pre(priv);
 560         if (result < 0)
 561                 return result;
 562
 563         len = data->block[0];
 564
 565         if (read_write == I2C_SMBUS_WRITE) {
 566                 outb_p(len, SMBHSTDAT0(priv));
 567                 outb_p(data->block[1], SMBBLKDAT(priv));
 568         }
 569
 570         if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
 571             read_write == I2C_SMBUS_READ)
 572                 smbcmd = I801_I2C_BLOCK_DATA;
 573         else
 574                 smbcmd = I801_BLOCK_DATA;
 575
 576         if (priv->features & FEATURE_IRQ) {
 577                 priv->is_read = (read_write == I2C_SMBUS_READ);
 578                 if (len == 1 && priv->is_read)
 579                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 580                 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
 581                 priv->len = len;
 582                 priv->count = 0;
 583                 priv->data = &data->block[1];
 584
 585                 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
 586                 result = wait_event_timeout(priv->waitq,
 587                                             (status = priv->status),
 588                                             adap->timeout);
 589                 if (!result) {
 590                         status = -ETIMEDOUT;
 591                         dev_warn(&priv->pci_dev->dev,
 592                                  "Timeout waiting for interrupt!\n");
 593                 }
 594                 priv->status = 0;
 595                 return i801_check_post(priv, status);
 596         }
 597
 598         for (i = 1; i <= len; i++) {
 599                 if (i == len && read_write == I2C_SMBUS_READ)
 600                         smbcmd |= SMBHSTCNT_LAST_BYTE;
 601                 outb_p(smbcmd, SMBHSTCNT(priv));
 602
 603                 if (i == 1)
 604                         outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
 605                                SMBHSTCNT(priv));
 606
 607                 status = i801_wait_byte_done(priv);
 608                 if (status)
 609                         goto exit;
 610
 611                 if (i == 1 && read_write == I2C_SMBUS_READ
 612                  && command != I2C_SMBUS_I2C_BLOCK_DATA) {
 613                         len = inb_p(SMBHSTDAT0(priv));
 614                         if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
 615                                 dev_err(&priv->pci_dev->dev,
 616                                         "Illegal SMBus block read size %d\n",
 617                                         len);
 618                                 /* Recover */
 619                                 while (inb_p(SMBHSTSTS(priv)) &
 620                                        SMBHSTSTS_HOST_BUSY)
 621                                         outb_p(SMBHSTSTS_BYTE_DONE,
 622                                                SMBHSTSTS(priv));
 623                                 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
 624                                 return -EPROTO;
 625                         }
 626                         data->block[0] = len;
 627                 }
 628
 629                 /* Retrieve/store value in SMBBLKDAT */
 630                 if (read_write == I2C_SMBUS_READ)
 631                         data->block[i] = inb_p(SMBBLKDAT(priv));
 632                 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
 633                         outb_p(data->block[i+1], SMBBLKDAT(priv));
 634
 635                 /* signals SMBBLKDAT ready */
 636                 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
 637         }
 638
 639         status = i801_wait_intr(priv);
 640 exit:
 641         return i801_check_post(priv, status);
 642 }
 643
 644 static int i801_set_block_buffer_mode(struct i801_priv *priv)
 645 {
 646         outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
 647         if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
 648                 return -EIO;
 649         return 0;
 650 }
 651
 652 /* Block transaction function */
 653 static int i801_block_transaction(struct i801_priv *priv,
 654                                   union i2c_smbus_data *data, char read_write,
 655                                   int command, int hwpec)
 656 {
 657         int result = 0;
 658         unsigned char hostc;
 659
 660         if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
 661                 if (read_write == I2C_SMBUS_WRITE) {
 662                         /* set I2C_EN bit in configuration register */
 663                         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
 664                         pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
 665                                               hostc | SMBHSTCFG_I2C_EN);
 666                 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
 667                         dev_err(&priv->pci_dev->dev,
 668                                 "I2C block read is unsupported!\n");
 669                         return -EOPNOTSUPP;
 670                 }
 671         }
 672
 673         if (read_write == I2C_SMBUS_WRITE
 674          || command == I2C_SMBUS_I2C_BLOCK_DATA) {
 675                 if (data->block[0] < 1)
 676                         data->block[0] = 1;
 677                 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
 678                         data->block[0] = I2C_SMBUS_BLOCK_MAX;
 679         } else {
 680                 data->block[0] = 32;    /* max for SMBus block reads */
 681         }
 682
 683         /* Experience has shown that the block buffer can only be used for
 684            SMBus (not I2C) block transactions, even though the datasheet
 685            doesn't mention this limitation. */
 686         if ((priv->features & FEATURE_BLOCK_BUFFER)
 687          && command != I2C_SMBUS_I2C_BLOCK_DATA
 688          && i801_set_block_buffer_mode(priv) == 0)
 689                 result = i801_block_transaction_by_block(priv, data,
 690                                                          read_write, hwpec);
 691         else
 692                 result = i801_block_transaction_byte_by_byte(priv, data,
 693                                                              read_write,
 694                                                              command, hwpec);
 695
 696         if (command == I2C_SMBUS_I2C_BLOCK_DATA
 697          && read_write == I2C_SMBUS_WRITE) {
 698                 /* restore saved configuration register value */
 699                 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
 700         }
 701         return result;
 702 }
 703
 704 /* Return negative errno on error. */
 705 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
 706                        unsigned short flags, char read_write, u8 command,
 707                        int size, union i2c_smbus_data *data)
 708 {
 709         int hwpec;
 710         int block = 0;
 711         int ret, xact = 0;
 712         struct i801_priv *priv = i2c_get_adapdata(adap);
 713
 714         hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
 715                 && size != I2C_SMBUS_QUICK
 716                 && size != I2C_SMBUS_I2C_BLOCK_DATA;
 717
 718         switch (size) {
 719         case I2C_SMBUS_QUICK:
 720                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 721                        SMBHSTADD(priv));
 722                 xact = I801_QUICK;
 723                 break;
 724         case I2C_SMBUS_BYTE:
 725                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 726                        SMBHSTADD(priv));
 727                 if (read_write == I2C_SMBUS_WRITE)
 728                         outb_p(command, SMBHSTCMD(priv));
 729                 xact = I801_BYTE;
 730                 break;
 731         case I2C_SMBUS_BYTE_DATA:
 732                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 733                        SMBHSTADD(priv));
 734                 outb_p(command, SMBHSTCMD(priv));
 735                 if (read_write == I2C_SMBUS_WRITE)
 736                         outb_p(data->byte, SMBHSTDAT0(priv));
 737                 xact = I801_BYTE_DATA;
 738                 break;
 739         case I2C_SMBUS_WORD_DATA:
 740                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 741                        SMBHSTADD(priv));
 742                 outb_p(command, SMBHSTCMD(priv));
 743                 if (read_write == I2C_SMBUS_WRITE) {
 744                         outb_p(data->word & 0xff, SMBHSTDAT0(priv));
 745                         outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
 746                 }
 747                 xact = I801_WORD_DATA;
 748                 break;
 749         case I2C_SMBUS_BLOCK_DATA:
 750                 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
 751                        SMBHSTADD(priv));
 752                 outb_p(command, SMBHSTCMD(priv));
 753                 block = 1;
 754                 break;
 755         case I2C_SMBUS_I2C_BLOCK_DATA:
 756                 /* NB: page 240 of ICH5 datasheet shows that the R/#W
 757                  * bit should be cleared here, even when reading */
 758                 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
 759                 if (read_write == I2C_SMBUS_READ) {
 760                         /* NB: page 240 of ICH5 datasheet also shows
 761                          * that DATA1 is the cmd field when reading */
 762                         outb_p(command, SMBHSTDAT1(priv));
 763                 } else
 764                         outb_p(command, SMBHSTCMD(priv));
 765                 block = 1;
 766                 break;
 767         default:
 768                 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
 769                         size);
 770                 return -EOPNOTSUPP;
 771         }
 772
 773         if (hwpec)      /* enable/disable hardware PEC */
 774                 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
 775         else
 776                 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
 777                        SMBAUXCTL(priv));
 778
 779         if (block)
 780                 ret = i801_block_transaction(priv, data, read_write, size,
 781                                              hwpec);
 782         else
 783                 ret = i801_transaction(priv, xact);
 784
 785         /* Some BIOSes don't like it when PEC is enabled at reboot or resume
 786            time, so we forcibly disable it after every transaction. Turn off
 787            E32B for the same reason. */
 788         if (hwpec || block)
 789                 outb_p(inb_p(SMBAUXCTL(priv)) &
 790                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
 791
 792         if (block)
 793                 return ret;
 794         if (ret)
 795                 return ret;
 796         if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
 797                 return 0;
 798
 799         switch (xact & 0x7f) {
 800         case I801_BYTE: /* Result put in SMBHSTDAT0 */
 801         case I801_BYTE_DATA:
 802                 data->byte = inb_p(SMBHSTDAT0(priv));
 803                 break;
 804         case I801_WORD_DATA:
 805                 data->word = inb_p(SMBHSTDAT0(priv)) +
 806                              (inb_p(SMBHSTDAT1(priv)) << 8);
 807                 break;
 808         }
 809         return 0;
 810 }
 811
 812
 813 static u32 i801_func(struct i2c_adapter *adapter)
 814 {
 815         struct i801_priv *priv = i2c_get_adapdata(adapter);
 816
 817         return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
 818                I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
 819                I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
 820                ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
 821                ((priv->features & FEATURE_I2C_BLOCK_READ) ?
 822                 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
 823 }
 824
 825 static const struct i2c_algorithm smbus_algorithm = {
 826         .smbus_xfer     = i801_access,
 827         .functionality  = i801_func,
 828 };
 829
 830 static const struct pci_device_id i801_ids[] = {
 831         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
 832         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
 833         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
 834         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
 835         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
 836         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
 837         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
 838         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
 839         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
 840         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
 841         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
 842         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
 843         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
 844         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
 845         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
 846         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
 847         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
 848         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
 849         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
 850         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
 851         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
 852         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
 853         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
 854         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
 855         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
 856         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
 857         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
 858         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
 859         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
 860         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
 861         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
 862         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
 863         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
 864         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
 865         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
 866         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
 867         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
 868         { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DNV_SMBUS) },
 869         { 0, }
 870 };
 871
 872 MODULE_DEVICE_TABLE(pci, i801_ids);
 873
 874 #if defined CONFIG_X86 && defined CONFIG_DMI
 875 static unsigned char apanel_addr;
 876
 877 /* Scan the system ROM for the signature "FJKEYINF" */
 878 static __init const void __iomem *bios_signature(const void __iomem *bios)
 879 {
 880         ssize_t offset;
 881         const unsigned char signature[] = "FJKEYINF";
 882
 883         for (offset = 0; offset < 0x10000; offset += 0x10) {
 884                 if (check_signature(bios + offset, signature,
 885                                     sizeof(signature)-1))
 886                         return bios + offset;
 887         }
 888         return NULL;
 889 }
 890
 891 static void __init input_apanel_init(void)
 892 {
 893         void __iomem *bios;
 894         const void __iomem *p;
 895
 896         bios = ioremap(0xF0000, 0x10000); /* Can't fail */
 897         p = bios_signature(bios);
 898         if (p) {
 899                 /* just use the first address */
 900                 apanel_addr = readb(p + 8 + 3) >> 1;
 901         }
 902         iounmap(bios);
 903 }
 904
 905 struct dmi_onboard_device_info {
 906         const char *name;
 907         u8 type;
 908         unsigned short i2c_addr;
 909         const char *i2c_type;
 910 };
 911
 912 static const struct dmi_onboard_device_info dmi_devices[] = {
 913         { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
 914         { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
 915         { "Hades",  DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
 916 };
 917
 918 static void dmi_check_onboard_device(u8 type, const char *name,
 919                                      struct i2c_adapter *adap)
 920 {
 921         int i;
 922         struct i2c_board_info info;
 923
 924         for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
 925                 /* & ~0x80, ignore enabled/disabled bit */
 926                 if ((type & ~0x80) != dmi_devices[i].type)
 927                         continue;
 928                 if (strcasecmp(name, dmi_devices[i].name))
 929                         continue;
 930
 931                 memset(&info, 0, sizeof(struct i2c_board_info));
 932                 info.addr = dmi_devices[i].i2c_addr;
 933                 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
 934                 i2c_new_device(adap, &info);
 935                 break;
 936         }
 937 }
 938
 939 /* We use our own function to check for onboard devices instead of
 940    dmi_find_device() as some buggy BIOS's have the devices we are interested
 941    in marked as disabled */
 942 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
 943 {
 944         int i, count;
 945
 946         if (dm->type != 10)
 947                 return;
 948
 949         count = (dm->length - sizeof(struct dmi_header)) / 2;
 950         for (i = 0; i < count; i++) {
 951                 const u8 *d = (char *)(dm + 1) + (i * 2);
 952                 const char *name = ((char *) dm) + dm->length;
 953                 u8 type = d[0];
 954                 u8 s = d[1];
 955
 956                 if (!s)
 957                         continue;
 958                 s--;
 959                 while (s > 0 && name[0]) {
 960                         name += strlen(name) + 1;
 961                         s--;
 962                 }
 963                 if (name[0] == 0) /* Bogus string reference */
 964                         continue;
 965
 966                 dmi_check_onboard_device(type, name, adap);
 967         }
 968 }
 969
 970 /* Register optional slaves */
 971 static void i801_probe_optional_slaves(struct i801_priv *priv)
 972 {
 973         /* Only register slaves on main SMBus channel */
 974         if (priv->features & FEATURE_IDF)
 975                 return;
 976
 977         if (apanel_addr) {
 978                 struct i2c_board_info info;
 979
 980                 memset(&info, 0, sizeof(struct i2c_board_info));
 981                 info.addr = apanel_addr;
 982                 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
 983                 i2c_new_device(&priv->adapter, &info);
 984         }
 985
 986         if (dmi_name_in_vendors("FUJITSU"))
 987                 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
 988 }
 989 #else
 990 static void __init input_apanel_init(void) {}
 991 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
 992 #endif  /* CONFIG_X86 && CONFIG_DMI */
 993
 994 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
 995                 defined CONFIG_DMI
 996 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
 997         .gpio_chip = "gpio_ich",
 998         .values = { 0x02, 0x03 },
 999         .n_values = 2,
1000         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1001         .gpios = { 52, 53 },
1002         .n_gpios = 2,
1003 };
1004
1005 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1006         .gpio_chip = "gpio_ich",
1007         .values = { 0x02, 0x03, 0x01 },
1008         .n_values = 3,
1009         .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1010         .gpios = { 52, 53 },
1011         .n_gpios = 2,
1012 };
1013
1014 static const struct dmi_system_id mux_dmi_table[] = {
1015         {
1016                 .matches = {
1017                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1018                         DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1019                 },
1020                 .driver_data = &i801_mux_config_asus_z8_d12,
1021         },
1022         {
1023                 .matches = {
1024                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1025                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1026                 },
1027                 .driver_data = &i801_mux_config_asus_z8_d12,
1028         },
1029         {
1030                 .matches = {
1031                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1032                         DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1033                 },
1034                 .driver_data = &i801_mux_config_asus_z8_d12,
1035         },
1036         {
1037                 .matches = {
1038                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1039                         DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1040                 },
1041                 .driver_data = &i801_mux_config_asus_z8_d12,
1042         },
1043         {
1044                 .matches = {
1045                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1046                         DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1047                 },
1048                 .driver_data = &i801_mux_config_asus_z8_d12,
1049         },
1050         {
1051                 .matches = {
1052                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1053                         DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1054                 },
1055                 .driver_data = &i801_mux_config_asus_z8_d12,
1056         },
1057         {
1058                 .matches = {
1059                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1060                         DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1061                 },
1062                 .driver_data = &i801_mux_config_asus_z8_d18,
1063         },
1064         {
1065                 .matches = {
1066                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1067                         DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1068                 },
1069                 .driver_data = &i801_mux_config_asus_z8_d18,
1070         },
1071         {
1072                 .matches = {
1073                         DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1074                         DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1075                 },
1076                 .driver_data = &i801_mux_config_asus_z8_d12,
1077         },
1078         { }
1079 };
1080
1081 /* Setup multiplexing if needed */
1082 static int i801_add_mux(struct i801_priv *priv)
1083 {
1084         struct device *dev = &priv->adapter.dev;
1085         const struct i801_mux_config *mux_config;
1086         struct i2c_mux_gpio_platform_data gpio_data;
1087         int err;
1088
1089         if (!priv->mux_drvdata)
1090                 return 0;
1091         mux_config = priv->mux_drvdata;
1092
1093         /* Prepare the platform data */
1094         memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1095         gpio_data.parent = priv->adapter.nr;
1096         gpio_data.values = mux_config->values;
1097         gpio_data.n_values = mux_config->n_values;
1098         gpio_data.classes = mux_config->classes;
1099         gpio_data.gpio_chip = mux_config->gpio_chip;
1100         gpio_data.gpios = mux_config->gpios;
1101         gpio_data.n_gpios = mux_config->n_gpios;
1102         gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1103
1104         /* Register the mux device */
1105         priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1106                                 PLATFORM_DEVID_AUTO, &gpio_data,
1107                                 sizeof(struct i2c_mux_gpio_platform_data));
1108         if (IS_ERR(priv->mux_pdev)) {
1109                 err = PTR_ERR(priv->mux_pdev);
1110                 priv->mux_pdev = NULL;
1111                 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1112                 return err;
1113         }
1114
1115         return 0;
1116 }
1117
1118 static void i801_del_mux(struct i801_priv *priv)
1119 {
1120         if (priv->mux_pdev)
1121                 platform_device_unregister(priv->mux_pdev);
1122 }
1123
1124 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1125 {
1126         const struct dmi_system_id *id;
1127         const struct i801_mux_config *mux_config;
1128         unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1129         int i;
1130
1131         id = dmi_first_match(mux_dmi_table);
1132         if (id) {
1133                 /* Remove branch classes from trunk */
1134                 mux_config = id->driver_data;
1135                 for (i = 0; i < mux_config->n_values; i++)
1136                         class &= ~mux_config->classes[i];
1137
1138                 /* Remember for later */
1139                 priv->mux_drvdata = mux_config;
1140         }
1141
1142         return class;
1143 }
1144 #else
1145 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1146 static inline void i801_del_mux(struct i801_priv *priv) { }
1147
1148 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1149 {
1150         return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1151 }
1152 #endif
1153
1154 static const struct itco_wdt_platform_data tco_platform_data = {
1155         .name = "Intel PCH",
1156         .version = 4,
1157 };
1158
1159 static DEFINE_SPINLOCK(p2sb_spinlock);
1160
1161 static void i801_add_tco(struct i801_priv *priv)
1162 {
1163         struct pci_dev *pci_dev = priv->pci_dev;
1164         struct resource tco_res[3], *res;
1165         struct platform_device *pdev;
1166         unsigned int devfn;
1167         u32 tco_base, tco_ctl;
1168         u32 base_addr, ctrl_val;
1169         u64 base64_addr;
1170
1171         if (!(priv->features & FEATURE_TCO))
1172                 return;
1173
1174         pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1175         pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1176         if (!(tco_ctl & TCOCTL_EN))
1177                 return;
1178
1179         memset(tco_res, 0, sizeof(tco_res));
1180
1181         res = &tco_res[ICH_RES_IO_TCO];
1182         res->start = tco_base & ~1;
1183         res->end = res->start + 32 - 1;
1184         res->flags = IORESOURCE_IO;
1185
1186         /*
1187          * Power Management registers.
1188          */
1189         devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);
1190         pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr);
1191
1192         res = &tco_res[ICH_RES_IO_SMI];
1193         res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
1194         res->end = res->start + 3;
1195         res->flags = IORESOURCE_IO;
1196
1197         /*
1198          * Enable the ACPI I/O space.
1199          */
1200         pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val);
1201         ctrl_val |= ACPICTRL_EN;
1202         pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
1203
1204         /*
1205          * We must access the NO_REBOOT bit over the Primary to Sideband
1206          * bridge (P2SB). The BIOS prevents the P2SB device from being
1207          * enumerated by the PCI subsystem, so we need to unhide/hide it
1208          * to lookup the P2SB BAR.
1209          */
1210         spin_lock(&p2sb_spinlock);
1211
1212         devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1213
1214         /* Unhide the P2SB device */
1215         pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1216
1217         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1218         base64_addr = base_addr & 0xfffffff0;
1219
1220         pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1221         base64_addr |= (u64)base_addr << 32;
1222
1223         /* Hide the P2SB device */
1224         pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x1);
1225         spin_unlock(&p2sb_spinlock);
1226
1227         res = &tco_res[ICH_RES_MEM_OFF];
1228         res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1229         res->end = res->start + 3;
1230         res->flags = IORESOURCE_MEM;
1231
1232         pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1233                                                  tco_res, 3, &tco_platform_data,
1234                                                  sizeof(tco_platform_data));
1235         if (IS_ERR(pdev)) {
1236                 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1237                 return;
1238         }
1239
1240         priv->tco_pdev = pdev;
1241 }
1242
1243 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1244 {
1245         unsigned char temp;
1246         int err, i;
1247         struct i801_priv *priv;
1248
1249         priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1250         if (!priv)
1251                 return -ENOMEM;
1252
1253         i2c_set_adapdata(&priv->adapter, priv);
1254         priv->adapter.owner = THIS_MODULE;
1255         priv->adapter.class = i801_get_adapter_class(priv);
1256         priv->adapter.algo = &smbus_algorithm;
1257
1258         priv->pci_dev = dev;
1259         switch (dev->device) {
1260         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1261         case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1262         case PCI_DEVICE_ID_INTEL_DNV_SMBUS:
1263                 priv->features |= FEATURE_I2C_BLOCK_READ;
1264                 priv->features |= FEATURE_IRQ;
1265                 priv->features |= FEATURE_SMBUS_PEC;
1266                 priv->features |= FEATURE_BLOCK_BUFFER;
1267                 priv->features |= FEATURE_TCO;
1268                 break;
1269
1270         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1271         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1272         case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1273         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1274         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1275         case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1276                 priv->features |= FEATURE_IDF;
1277                 /* fall through */
1278         default:
1279                 priv->features |= FEATURE_I2C_BLOCK_READ;
1280                 priv->features |= FEATURE_IRQ;
1281                 /* fall through */
1282         case PCI_DEVICE_ID_INTEL_82801DB_3:
1283                 priv->features |= FEATURE_SMBUS_PEC;
1284                 priv->features |= FEATURE_BLOCK_BUFFER;
1285                 /* fall through */
1286         case PCI_DEVICE_ID_INTEL_82801CA_3:
1287         case PCI_DEVICE_ID_INTEL_82801BA_2:
1288         case PCI_DEVICE_ID_INTEL_82801AB_3:
1289         case PCI_DEVICE_ID_INTEL_82801AA_3:
1290                 break;
1291         }
1292
1293         /* Disable features on user request */
1294         for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1295                 if (priv->features & disable_features & (1 << i))
1296                         dev_notice(&dev->dev, "%s disabled by user\n",
1297                                    i801_feature_names[i]);
1298         }
1299         priv->features &= ~disable_features;
1300
1301         err = pcim_enable_device(dev);
1302         if (err) {
1303                 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1304                         err);
1305                 return err;
1306         }
1307         pcim_pin_device(dev);
1308
1309         /* Determine the address of the SMBus area */
1310         priv->smba = pci_resource_start(dev, SMBBAR);
1311         if (!priv->smba) {
1312                 dev_err(&dev->dev,
1313                         "SMBus base address uninitialized, upgrade BIOS\n");
1314                 return -ENODEV;
1315         }
1316
1317         err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
1318         if (err) {
1319                 return -ENODEV;
1320         }
1321
1322         err = pcim_iomap_regions(dev, 1 << SMBBAR,
1323                                  dev_driver_string(&dev->dev));
1324         if (err) {
1325                 dev_err(&dev->dev,
1326                         "Failed to request SMBus region 0x%lx-0x%Lx\n",
1327                         priv->smba,
1328                         (unsigned long long)pci_resource_end(dev, SMBBAR));
1329                 return err;
1330         }
1331
1332         pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1333         priv->original_hstcfg = temp;
1334         temp &= ~SMBHSTCFG_I2C_EN;      /* SMBus timing */
1335         if (!(temp & SMBHSTCFG_HST_EN)) {
1336                 dev_info(&dev->dev, "Enabling SMBus device\n");
1337                 temp |= SMBHSTCFG_HST_EN;
1338         }
1339         pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1340
1341         if (temp & SMBHSTCFG_SMB_SMI_EN) {
1342                 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1343                 /* Disable SMBus interrupt feature if SMBus using SMI# */
1344                 priv->features &= ~FEATURE_IRQ;
1345         }
1346
1347         /* Clear special mode bits */
1348         if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1349                 outb_p(inb_p(SMBAUXCTL(priv)) &
1350                        ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1351
1352         /* Default timeout in interrupt mode: 200 ms */
1353         priv->adapter.timeout = HZ / 5;
1354
1355         if (priv->features & FEATURE_IRQ) {
1356                 u16 pcictl, pcists;
1357
1358                 /* Complain if an interrupt is already pending */
1359                 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1360                 if (pcists & SMBPCISTS_INTS)
1361                         dev_warn(&dev->dev, "An interrupt is pending!\n");
1362
1363                 /* Check if interrupts have been disabled */
1364                 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1365                 if (pcictl & SMBPCICTL_INTDIS) {
1366                         dev_info(&dev->dev, "Interrupts are disabled\n");
1367                         priv->features &= ~FEATURE_IRQ;
1368                 }
1369         }
1370
1371         if (priv->features & FEATURE_IRQ) {
1372                 init_waitqueue_head(&priv->waitq);
1373
1374                 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1375                                        IRQF_SHARED,
1376                                        dev_driver_string(&dev->dev), priv);
1377                 if (err) {
1378                         dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1379                                 dev->irq, err);
1380                         priv->features &= ~FEATURE_IRQ;
1381                 }
1382         }
1383         dev_info(&dev->dev, "SMBus using %s\n",
1384                  priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1385
1386         i801_add_tco(priv);
1387
1388         /* set up the sysfs linkage to our parent device */
1389         priv->adapter.dev.parent = &dev->dev;
1390
1391         /* Retry up to 3 times on lost arbitration */
1392         priv->adapter.retries = 3;
1393
1394         snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1395                 "SMBus I801 adapter at %04lx", priv->smba);
1396         err = i2c_add_adapter(&priv->adapter);
1397         if (err) {
1398                 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
1399                 return err;
1400         }
1401
1402         i801_probe_optional_slaves(priv);
1403         /* We ignore errors - multiplexing is optional */
1404         i801_add_mux(priv);
1405
1406         pci_set_drvdata(dev, priv);
1407
1408         return 0;
1409 }
1410
1411 static void i801_remove(struct pci_dev *dev)
1412 {
1413         struct i801_priv *priv = pci_get_drvdata(dev);
1414
1415         i801_del_mux(priv);
1416         i2c_del_adapter(&priv->adapter);
1417         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1418
1419         platform_device_unregister(priv->tco_pdev);
1420
1421         /*
1422          * do not call pci_disable_device(dev) since it can cause hard hangs on
1423          * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1424          */
1425 }
1426
1427 #ifdef CONFIG_PM
1428 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
1429 {
1430         struct i801_priv *priv = pci_get_drvdata(dev);
1431
1432         pci_save_state(dev);
1433         pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1434         pci_set_power_state(dev, pci_choose_state(dev, mesg));
1435         return 0;
1436 }
1437
1438 static int i801_resume(struct pci_dev *dev)
1439 {
1440         pci_set_power_state(dev, PCI_D0);
1441         pci_restore_state(dev);
1442         return 0;
1443 }
1444 #else
1445 #define i801_suspend NULL
1446 #define i801_resume NULL
1447 #endif
1448
1449 static struct pci_driver i801_driver = {
1450         .name           = "i801_smbus",
1451         .id_table       = i801_ids,
1452         .probe          = i801_probe,
1453         .remove         = i801_remove,
1454         .suspend        = i801_suspend,
1455         .resume         = i801_resume,
1456 };
1457
1458 static int __init i2c_i801_init(void)
1459 {
1460         if (dmi_name_in_vendors("FUJITSU"))
1461                 input_apanel_init();
1462         return pci_register_driver(&i801_driver);
1463 }
1464
1465 static void __exit i2c_i801_exit(void)
1466 {
1467         pci_unregister_driver(&i801_driver);
1468 }
1469
1470 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1471 MODULE_DESCRIPTION("I801 SMBus driver");
1472 MODULE_LICENSE("GPL");
1473
1474 module_init(i2c_i801_init);
1475 module_exit(i2c_i801_exit);