2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 Copyright (C) 2007, 2008 Jean Delvare <khali@linux-fr.org>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, write to the Free Software
21 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
25 Supports the following Intel I/O Controller Hubs (ICH):
28 region SMBus Block proc. block
29 Chip name PCI ID size PEC buffer call read
30 ----------------------------------------------------------------------
31 82801AA (ICH) 0x2413 16 no no no no
32 82801AB (ICH0) 0x2423 16 no no no no
33 82801BA (ICH2) 0x2443 16 no no no no
34 82801CA (ICH3) 0x2483 32 soft no no no
35 82801DB (ICH4) 0x24c3 32 hard yes no no
36 82801E (ICH5) 0x24d3 32 hard yes yes yes
37 6300ESB 0x25a4 32 hard yes yes yes
38 82801F (ICH6) 0x266a 32 hard yes yes yes
39 6310ESB/6320ESB 0x269b 32 hard yes yes yes
40 82801G (ICH7) 0x27da 32 hard yes yes yes
41 82801H (ICH8) 0x283e 32 hard yes yes yes
42 82801I (ICH9) 0x2930 32 hard yes yes yes
43 EP80579 (Tolapai) 0x5032 32 hard yes yes yes
44 ICH10 0x3a30 32 hard yes yes yes
45 ICH10 0x3a60 32 hard yes yes yes
46 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
47 6 Series (PCH) 0x1c22 32 hard yes yes yes
48 Patsburg (PCH) 0x1d22 32 hard yes yes yes
49 Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
50 Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
51 Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
52 DH89xxCC (PCH) 0x2330 32 hard yes yes yes
53 Panther Point (PCH) 0x1e22 32 hard yes yes yes
55 Features supported by this driver:
59 Block process call transaction no
60 I2C block read transaction yes (doesn't use the block buffer)
63 See the file Documentation/i2c/busses/i2c-i801 for details.
66 #include <linux/module.h>
67 #include <linux/pci.h>
68 #include <linux/kernel.h>
69 #include <linux/stddef.h>
70 #include <linux/delay.h>
71 #include <linux/ioport.h>
72 #include <linux/init.h>
73 #include <linux/i2c.h>
74 #include <linux/acpi.h>
76 #include <linux/dmi.h>
77 #include <linux/slab.h>
79 /* I801 SMBus address offsets */
80 #define SMBHSTSTS(p) (0 + (p)->smba)
81 #define SMBHSTCNT(p) (2 + (p)->smba)
82 #define SMBHSTCMD(p) (3 + (p)->smba)
83 #define SMBHSTADD(p) (4 + (p)->smba)
84 #define SMBHSTDAT0(p) (5 + (p)->smba)
85 #define SMBHSTDAT1(p) (6 + (p)->smba)
86 #define SMBBLKDAT(p) (7 + (p)->smba)
87 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
88 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
89 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
91 /* PCI Address Constants */
93 #define SMBHSTCFG 0x040
95 /* Host configuration bits for SMBHSTCFG */
96 #define SMBHSTCFG_HST_EN 1
97 #define SMBHSTCFG_SMB_SMI_EN 2
98 #define SMBHSTCFG_I2C_EN 4
100 /* Auxiliary control register bits, ICH4+ only */
101 #define SMBAUXCTL_CRC 1
102 #define SMBAUXCTL_E32B 2
104 /* kill bit for SMBHSTCNT */
105 #define SMBHSTCNT_KILL 2
108 #define MAX_TIMEOUT 100
109 #define ENABLE_INT9 0 /* set to 0x01 to enable - untested */
111 /* I801 command constants */
112 #define I801_QUICK 0x00
113 #define I801_BYTE 0x04
114 #define I801_BYTE_DATA 0x08
115 #define I801_WORD_DATA 0x0C
116 #define I801_PROC_CALL 0x10 /* unimplemented */
117 #define I801_BLOCK_DATA 0x14
118 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
119 #define I801_BLOCK_LAST 0x34
120 #define I801_I2C_BLOCK_LAST 0x38 /* ICH5 and later */
121 #define I801_START 0x40
122 #define I801_PEC_EN 0x80 /* ICH3 and later */
124 /* I801 Hosts Status register bits */
125 #define SMBHSTSTS_BYTE_DONE 0x80
126 #define SMBHSTSTS_INUSE_STS 0x40
127 #define SMBHSTSTS_SMBALERT_STS 0x20
128 #define SMBHSTSTS_FAILED 0x10
129 #define SMBHSTSTS_BUS_ERR 0x08
130 #define SMBHSTSTS_DEV_ERR 0x04
131 #define SMBHSTSTS_INTR 0x02
132 #define SMBHSTSTS_HOST_BUSY 0x01
134 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_FAILED | \
135 SMBHSTSTS_BUS_ERR | SMBHSTSTS_DEV_ERR | \
138 /* Older devices have their ID defined in <linux/pci_ids.h> */
139 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
140 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
141 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
142 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
143 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
144 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
145 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
146 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
147 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
150 struct i2c_adapter adapter;
152 unsigned char original_hstcfg;
153 struct pci_dev *pci_dev;
154 unsigned int features;
157 static struct pci_driver i801_driver;
159 #define FEATURE_SMBUS_PEC (1 << 0)
160 #define FEATURE_BLOCK_BUFFER (1 << 1)
161 #define FEATURE_BLOCK_PROC (1 << 2)
162 #define FEATURE_I2C_BLOCK_READ (1 << 3)
164 static const char *i801_feature_names[] = {
167 "Block process call",
171 static unsigned int disable_features;
172 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
173 MODULE_PARM_DESC(disable_features, "Disable selected driver features");
175 /* Make sure the SMBus host is ready to start transmitting.
176 Return 0 if it is, -EBUSY if it is not. */
177 static int i801_check_pre(struct i801_priv *priv)
181 status = inb_p(SMBHSTSTS(priv));
182 if (status & SMBHSTSTS_HOST_BUSY) {
183 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
187 status &= STATUS_FLAGS;
189 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
191 outb_p(status, SMBHSTSTS(priv));
192 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
194 dev_err(&priv->pci_dev->dev,
195 "Failed clearing status flags (%02x)\n",
204 /* Convert the status register to an error code, and clear it. */
205 static int i801_check_post(struct i801_priv *priv, int status, int timeout)
209 /* If the SMBus is still busy, we give up */
211 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
212 /* try to stop the current command */
213 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
214 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
217 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
220 /* Check if it worked */
221 status = inb_p(SMBHSTSTS(priv));
222 if ((status & SMBHSTSTS_HOST_BUSY) ||
223 !(status & SMBHSTSTS_FAILED))
224 dev_err(&priv->pci_dev->dev,
225 "Failed terminating the transaction\n");
226 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
230 if (status & SMBHSTSTS_FAILED) {
232 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
234 if (status & SMBHSTSTS_DEV_ERR) {
236 dev_dbg(&priv->pci_dev->dev, "No response\n");
238 if (status & SMBHSTSTS_BUS_ERR) {
240 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
244 /* Clear error flags */
245 outb_p(status & STATUS_FLAGS, SMBHSTSTS(priv));
246 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
248 dev_warn(&priv->pci_dev->dev, "Failed clearing status "
249 "flags at end of transaction (%02x)\n",
257 static int i801_transaction(struct i801_priv *priv, int xact)
263 result = i801_check_pre(priv);
267 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
268 * INTREN, SMBSCMD are passed in xact */
269 outb_p(xact | I801_START, SMBHSTCNT(priv));
271 /* We will always wait for a fraction of a second! */
274 status = inb_p(SMBHSTSTS(priv));
275 } while ((status & SMBHSTSTS_HOST_BUSY) && (timeout++ < MAX_TIMEOUT));
277 result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
281 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
285 /* wait for INTR bit as advised by Intel */
286 static void i801_wait_hwpec(struct i801_priv *priv)
293 status = inb_p(SMBHSTSTS(priv));
294 } while ((!(status & SMBHSTSTS_INTR))
295 && (timeout++ < MAX_TIMEOUT));
297 if (timeout > MAX_TIMEOUT)
298 dev_dbg(&priv->pci_dev->dev, "PEC Timeout!\n");
300 outb_p(status, SMBHSTSTS(priv));
303 static int i801_block_transaction_by_block(struct i801_priv *priv,
304 union i2c_smbus_data *data,
305 char read_write, int hwpec)
310 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
312 /* Use 32-byte buffer to process this transaction */
313 if (read_write == I2C_SMBUS_WRITE) {
314 len = data->block[0];
315 outb_p(len, SMBHSTDAT0(priv));
316 for (i = 0; i < len; i++)
317 outb_p(data->block[i+1], SMBBLKDAT(priv));
320 status = i801_transaction(priv, I801_BLOCK_DATA | ENABLE_INT9 |
321 I801_PEC_EN * hwpec);
325 if (read_write == I2C_SMBUS_READ) {
326 len = inb_p(SMBHSTDAT0(priv));
327 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
330 data->block[0] = len;
331 for (i = 0; i < len; i++)
332 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
337 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
338 union i2c_smbus_data *data,
339 char read_write, int command,
348 result = i801_check_pre(priv);
352 len = data->block[0];
354 if (read_write == I2C_SMBUS_WRITE) {
355 outb_p(len, SMBHSTDAT0(priv));
356 outb_p(data->block[1], SMBBLKDAT(priv));
359 for (i = 1; i <= len; i++) {
360 if (i == len && read_write == I2C_SMBUS_READ) {
361 if (command == I2C_SMBUS_I2C_BLOCK_DATA)
362 smbcmd = I801_I2C_BLOCK_LAST;
364 smbcmd = I801_BLOCK_LAST;
366 if (command == I2C_SMBUS_I2C_BLOCK_DATA
367 && read_write == I2C_SMBUS_READ)
368 smbcmd = I801_I2C_BLOCK_DATA;
370 smbcmd = I801_BLOCK_DATA;
372 outb_p(smbcmd | ENABLE_INT9, SMBHSTCNT(priv));
375 outb_p(inb(SMBHSTCNT(priv)) | I801_START,
378 /* We will always wait for a fraction of a second! */
382 status = inb_p(SMBHSTSTS(priv));
383 } while ((!(status & SMBHSTSTS_BYTE_DONE))
384 && (timeout++ < MAX_TIMEOUT));
386 result = i801_check_post(priv, status, timeout > MAX_TIMEOUT);
390 if (i == 1 && read_write == I2C_SMBUS_READ
391 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
392 len = inb_p(SMBHSTDAT0(priv));
393 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
394 dev_err(&priv->pci_dev->dev,
395 "Illegal SMBus block read size %d\n",
398 while (inb_p(SMBHSTSTS(priv)) &
400 outb_p(SMBHSTSTS_BYTE_DONE,
402 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
405 data->block[0] = len;
408 /* Retrieve/store value in SMBBLKDAT */
409 if (read_write == I2C_SMBUS_READ)
410 data->block[i] = inb_p(SMBBLKDAT(priv));
411 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
412 outb_p(data->block[i+1], SMBBLKDAT(priv));
414 /* signals SMBBLKDAT ready */
415 outb_p(SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR, SMBHSTSTS(priv));
421 static int i801_set_block_buffer_mode(struct i801_priv *priv)
423 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
424 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
429 /* Block transaction function */
430 static int i801_block_transaction(struct i801_priv *priv,
431 union i2c_smbus_data *data, char read_write,
432 int command, int hwpec)
437 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
438 if (read_write == I2C_SMBUS_WRITE) {
439 /* set I2C_EN bit in configuration register */
440 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
441 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
442 hostc | SMBHSTCFG_I2C_EN);
443 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
444 dev_err(&priv->pci_dev->dev,
445 "I2C block read is unsupported!\n");
450 if (read_write == I2C_SMBUS_WRITE
451 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
452 if (data->block[0] < 1)
454 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
455 data->block[0] = I2C_SMBUS_BLOCK_MAX;
457 data->block[0] = 32; /* max for SMBus block reads */
460 /* Experience has shown that the block buffer can only be used for
461 SMBus (not I2C) block transactions, even though the datasheet
462 doesn't mention this limitation. */
463 if ((priv->features & FEATURE_BLOCK_BUFFER)
464 && command != I2C_SMBUS_I2C_BLOCK_DATA
465 && i801_set_block_buffer_mode(priv) == 0)
466 result = i801_block_transaction_by_block(priv, data,
469 result = i801_block_transaction_byte_by_byte(priv, data,
473 if (result == 0 && hwpec)
474 i801_wait_hwpec(priv);
476 if (command == I2C_SMBUS_I2C_BLOCK_DATA
477 && read_write == I2C_SMBUS_WRITE) {
478 /* restore saved configuration register value */
479 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
484 /* Return negative errno on error. */
485 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
486 unsigned short flags, char read_write, u8 command,
487 int size, union i2c_smbus_data *data)
492 struct i801_priv *priv = i2c_get_adapdata(adap);
494 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
495 && size != I2C_SMBUS_QUICK
496 && size != I2C_SMBUS_I2C_BLOCK_DATA;
499 case I2C_SMBUS_QUICK:
500 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
505 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
507 if (read_write == I2C_SMBUS_WRITE)
508 outb_p(command, SMBHSTCMD(priv));
511 case I2C_SMBUS_BYTE_DATA:
512 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
514 outb_p(command, SMBHSTCMD(priv));
515 if (read_write == I2C_SMBUS_WRITE)
516 outb_p(data->byte, SMBHSTDAT0(priv));
517 xact = I801_BYTE_DATA;
519 case I2C_SMBUS_WORD_DATA:
520 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
522 outb_p(command, SMBHSTCMD(priv));
523 if (read_write == I2C_SMBUS_WRITE) {
524 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
525 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
527 xact = I801_WORD_DATA;
529 case I2C_SMBUS_BLOCK_DATA:
530 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
532 outb_p(command, SMBHSTCMD(priv));
535 case I2C_SMBUS_I2C_BLOCK_DATA:
536 /* NB: page 240 of ICH5 datasheet shows that the R/#W
537 * bit should be cleared here, even when reading */
538 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
539 if (read_write == I2C_SMBUS_READ) {
540 /* NB: page 240 of ICH5 datasheet also shows
541 * that DATA1 is the cmd field when reading */
542 outb_p(command, SMBHSTDAT1(priv));
544 outb_p(command, SMBHSTCMD(priv));
548 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
553 if (hwpec) /* enable/disable hardware PEC */
554 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
556 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
560 ret = i801_block_transaction(priv, data, read_write, size,
563 ret = i801_transaction(priv, xact | ENABLE_INT9);
565 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
566 time, so we forcibly disable it after every transaction. Turn off
567 E32B for the same reason. */
569 outb_p(inb_p(SMBAUXCTL(priv)) &
570 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
576 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
579 switch (xact & 0x7f) {
580 case I801_BYTE: /* Result put in SMBHSTDAT0 */
582 data->byte = inb_p(SMBHSTDAT0(priv));
585 data->word = inb_p(SMBHSTDAT0(priv)) +
586 (inb_p(SMBHSTDAT1(priv)) << 8);
593 static u32 i801_func(struct i2c_adapter *adapter)
595 struct i801_priv *priv = i2c_get_adapdata(adapter);
597 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
598 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
599 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
600 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
601 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
602 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
605 static const struct i2c_algorithm smbus_algorithm = {
606 .smbus_xfer = i801_access,
607 .functionality = i801_func,
610 static const struct pci_device_id i801_ids[] = {
611 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
612 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
613 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
614 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
615 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
616 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
617 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
618 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
619 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
620 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
621 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
622 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
623 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
624 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
625 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
626 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
627 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
628 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
629 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
630 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
631 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
632 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
633 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
637 MODULE_DEVICE_TABLE(pci, i801_ids);
639 #if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE
640 static unsigned char apanel_addr;
642 /* Scan the system ROM for the signature "FJKEYINF" */
643 static __init const void __iomem *bios_signature(const void __iomem *bios)
646 const unsigned char signature[] = "FJKEYINF";
648 for (offset = 0; offset < 0x10000; offset += 0x10) {
649 if (check_signature(bios + offset, signature,
650 sizeof(signature)-1))
651 return bios + offset;
656 static void __init input_apanel_init(void)
659 const void __iomem *p;
661 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
662 p = bios_signature(bios);
664 /* just use the first address */
665 apanel_addr = readb(p + 8 + 3) >> 1;
670 static void __init input_apanel_init(void) {}
673 #if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE
674 struct dmi_onboard_device_info {
677 unsigned short i2c_addr;
678 const char *i2c_type;
681 static struct dmi_onboard_device_info __devinitdata dmi_devices[] = {
682 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
683 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
684 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
687 static void __devinit dmi_check_onboard_device(u8 type, const char *name,
688 struct i2c_adapter *adap)
691 struct i2c_board_info info;
693 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
694 /* & ~0x80, ignore enabled/disabled bit */
695 if ((type & ~0x80) != dmi_devices[i].type)
697 if (strcasecmp(name, dmi_devices[i].name))
700 memset(&info, 0, sizeof(struct i2c_board_info));
701 info.addr = dmi_devices[i].i2c_addr;
702 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
703 i2c_new_device(adap, &info);
708 /* We use our own function to check for onboard devices instead of
709 dmi_find_device() as some buggy BIOS's have the devices we are interested
710 in marked as disabled */
711 static void __devinit dmi_check_onboard_devices(const struct dmi_header *dm,
719 count = (dm->length - sizeof(struct dmi_header)) / 2;
720 for (i = 0; i < count; i++) {
721 const u8 *d = (char *)(dm + 1) + (i * 2);
722 const char *name = ((char *) dm) + dm->length;
729 while (s > 0 && name[0]) {
730 name += strlen(name) + 1;
733 if (name[0] == 0) /* Bogus string reference */
736 dmi_check_onboard_device(type, name, adap);
741 static int __devinit i801_probe(struct pci_dev *dev,
742 const struct pci_device_id *id)
746 struct i801_priv *priv;
748 priv = kzalloc(sizeof(*priv), GFP_KERNEL);
752 i2c_set_adapdata(&priv->adapter, priv);
753 priv->adapter.owner = THIS_MODULE;
754 priv->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
755 priv->adapter.algo = &smbus_algorithm;
758 switch (dev->device) {
760 priv->features |= FEATURE_I2C_BLOCK_READ;
762 case PCI_DEVICE_ID_INTEL_82801DB_3:
763 priv->features |= FEATURE_SMBUS_PEC;
764 priv->features |= FEATURE_BLOCK_BUFFER;
766 case PCI_DEVICE_ID_INTEL_82801CA_3:
767 case PCI_DEVICE_ID_INTEL_82801BA_2:
768 case PCI_DEVICE_ID_INTEL_82801AB_3:
769 case PCI_DEVICE_ID_INTEL_82801AA_3:
773 /* Disable features on user request */
774 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
775 if (priv->features & disable_features & (1 << i))
776 dev_notice(&dev->dev, "%s disabled by user\n",
777 i801_feature_names[i]);
779 priv->features &= ~disable_features;
781 err = pci_enable_device(dev);
783 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
788 /* Determine the address of the SMBus area */
789 priv->smba = pci_resource_start(dev, SMBBAR);
791 dev_err(&dev->dev, "SMBus base address uninitialized, "
797 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
803 err = pci_request_region(dev, SMBBAR, i801_driver.name);
805 dev_err(&dev->dev, "Failed to request SMBus region "
806 "0x%lx-0x%Lx\n", priv->smba,
807 (unsigned long long)pci_resource_end(dev, SMBBAR));
811 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
812 priv->original_hstcfg = temp;
813 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
814 if (!(temp & SMBHSTCFG_HST_EN)) {
815 dev_info(&dev->dev, "Enabling SMBus device\n");
816 temp |= SMBHSTCFG_HST_EN;
818 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
820 if (temp & SMBHSTCFG_SMB_SMI_EN)
821 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
823 dev_dbg(&dev->dev, "SMBus using PCI Interrupt\n");
825 /* Clear special mode bits */
826 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
827 outb_p(inb_p(SMBAUXCTL(priv)) &
828 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
830 /* set up the sysfs linkage to our parent device */
831 priv->adapter.dev.parent = &dev->dev;
833 /* Retry up to 3 times on lost arbitration */
834 priv->adapter.retries = 3;
836 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
837 "SMBus I801 adapter at %04lx", priv->smba);
838 err = i2c_add_adapter(&priv->adapter);
840 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
844 /* Register optional slaves */
845 #if defined CONFIG_INPUT_APANEL || defined CONFIG_INPUT_APANEL_MODULE
847 struct i2c_board_info info;
849 memset(&info, 0, sizeof(struct i2c_board_info));
850 info.addr = apanel_addr;
851 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
852 i2c_new_device(&priv->adapter, &info);
855 #if defined CONFIG_SENSORS_FSCHMD || defined CONFIG_SENSORS_FSCHMD_MODULE
856 if (dmi_name_in_vendors("FUJITSU"))
857 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
860 pci_set_drvdata(dev, priv);
864 pci_release_region(dev, SMBBAR);
870 static void __devexit i801_remove(struct pci_dev *dev)
872 struct i801_priv *priv = pci_get_drvdata(dev);
874 i2c_del_adapter(&priv->adapter);
875 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
876 pci_release_region(dev, SMBBAR);
877 pci_set_drvdata(dev, NULL);
880 * do not call pci_disable_device(dev) since it can cause hard hangs on
881 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
886 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
888 struct i801_priv *priv = pci_get_drvdata(dev);
891 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
892 pci_set_power_state(dev, pci_choose_state(dev, mesg));
896 static int i801_resume(struct pci_dev *dev)
898 pci_set_power_state(dev, PCI_D0);
899 pci_restore_state(dev);
900 return pci_enable_device(dev);
903 #define i801_suspend NULL
904 #define i801_resume NULL
907 static struct pci_driver i801_driver = {
908 .name = "i801_smbus",
909 .id_table = i801_ids,
911 .remove = __devexit_p(i801_remove),
912 .suspend = i801_suspend,
913 .resume = i801_resume,
916 static int __init i2c_i801_init(void)
919 return pci_register_driver(&i801_driver);
922 static void __exit i2c_i801_exit(void)
924 pci_unregister_driver(&i801_driver);
927 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, "
928 "Jean Delvare <khali@linux-fr.org>");
929 MODULE_DESCRIPTION("I801 SMBus driver");
930 MODULE_LICENSE("GPL");
932 module_init(i2c_i801_init);
933 module_exit(i2c_i801_exit);