2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl>,
3 Philip Edelbrock <phil@netroedge.com>, and Mark D. Studebaker
5 Copyright (C) 2007 - 2014 Jean Delvare <jdelvare@suse.de>
6 Copyright (C) 2010 Intel Corporation,
7 David Woodhouse <dwmw2@infradead.org>
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
21 * Supports the following Intel I/O Controller Hubs (ICH):
24 * region SMBus Block proc. block
25 * Chip name PCI ID size PEC buffer call read
26 * ---------------------------------------------------------------------------
27 * 82801AA (ICH) 0x2413 16 no no no no
28 * 82801AB (ICH0) 0x2423 16 no no no no
29 * 82801BA (ICH2) 0x2443 16 no no no no
30 * 82801CA (ICH3) 0x2483 32 soft no no no
31 * 82801DB (ICH4) 0x24c3 32 hard yes no no
32 * 82801E (ICH5) 0x24d3 32 hard yes yes yes
33 * 6300ESB 0x25a4 32 hard yes yes yes
34 * 82801F (ICH6) 0x266a 32 hard yes yes yes
35 * 6310ESB/6320ESB 0x269b 32 hard yes yes yes
36 * 82801G (ICH7) 0x27da 32 hard yes yes yes
37 * 82801H (ICH8) 0x283e 32 hard yes yes yes
38 * 82801I (ICH9) 0x2930 32 hard yes yes yes
39 * EP80579 (Tolapai) 0x5032 32 hard yes yes yes
40 * ICH10 0x3a30 32 hard yes yes yes
41 * ICH10 0x3a60 32 hard yes yes yes
42 * 5/3400 Series (PCH) 0x3b30 32 hard yes yes yes
43 * 6 Series (PCH) 0x1c22 32 hard yes yes yes
44 * Patsburg (PCH) 0x1d22 32 hard yes yes yes
45 * Patsburg (PCH) IDF 0x1d70 32 hard yes yes yes
46 * Patsburg (PCH) IDF 0x1d71 32 hard yes yes yes
47 * Patsburg (PCH) IDF 0x1d72 32 hard yes yes yes
48 * DH89xxCC (PCH) 0x2330 32 hard yes yes yes
49 * Panther Point (PCH) 0x1e22 32 hard yes yes yes
50 * Lynx Point (PCH) 0x8c22 32 hard yes yes yes
51 * Lynx Point-LP (PCH) 0x9c22 32 hard yes yes yes
52 * Avoton (SOC) 0x1f3c 32 hard yes yes yes
53 * Wellsburg (PCH) 0x8d22 32 hard yes yes yes
54 * Wellsburg (PCH) MS 0x8d7d 32 hard yes yes yes
55 * Wellsburg (PCH) MS 0x8d7e 32 hard yes yes yes
56 * Wellsburg (PCH) MS 0x8d7f 32 hard yes yes yes
57 * Coleto Creek (PCH) 0x23b0 32 hard yes yes yes
58 * Wildcat Point (PCH) 0x8ca2 32 hard yes yes yes
59 * Wildcat Point-LP (PCH) 0x9ca2 32 hard yes yes yes
60 * BayTrail (SOC) 0x0f12 32 hard yes yes yes
61 * Sunrise Point-H (PCH) 0xa123 32 hard yes yes yes
62 * Sunrise Point-LP (PCH) 0x9d23 32 hard yes yes yes
64 * Features supported by this driver:
68 * Block process call transaction no
69 * I2C block read transaction yes (doesn't use the block buffer)
71 * Interrupt processing yes
73 * See the file Documentation/i2c/busses/i2c-i801 for details.
76 #include <linux/interrupt.h>
77 #include <linux/module.h>
78 #include <linux/pci.h>
79 #include <linux/kernel.h>
80 #include <linux/stddef.h>
81 #include <linux/delay.h>
82 #include <linux/ioport.h>
83 #include <linux/init.h>
84 #include <linux/i2c.h>
85 #include <linux/acpi.h>
87 #include <linux/dmi.h>
88 #include <linux/slab.h>
89 #include <linux/wait.h>
90 #include <linux/err.h>
91 #include <linux/platform_device.h>
92 #include <linux/platform_data/itco_wdt.h>
94 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
96 #include <linux/gpio.h>
97 #include <linux/i2c-mux-gpio.h>
100 /* I801 SMBus address offsets */
101 #define SMBHSTSTS(p) (0 + (p)->smba)
102 #define SMBHSTCNT(p) (2 + (p)->smba)
103 #define SMBHSTCMD(p) (3 + (p)->smba)
104 #define SMBHSTADD(p) (4 + (p)->smba)
105 #define SMBHSTDAT0(p) (5 + (p)->smba)
106 #define SMBHSTDAT1(p) (6 + (p)->smba)
107 #define SMBBLKDAT(p) (7 + (p)->smba)
108 #define SMBPEC(p) (8 + (p)->smba) /* ICH3 and later */
109 #define SMBAUXSTS(p) (12 + (p)->smba) /* ICH4 and later */
110 #define SMBAUXCTL(p) (13 + (p)->smba) /* ICH4 and later */
112 /* PCI Address Constants */
114 #define SMBPCICTL 0x004
115 #define SMBPCISTS 0x006
116 #define SMBHSTCFG 0x040
117 #define TCOBASE 0x050
120 #define ACPIBASE 0x040
121 #define ACPIBASE_SMI_OFF 0x030
122 #define ACPICTRL 0x044
123 #define ACPICTRL_EN 0x080
125 #define SBREG_BAR 0x10
126 #define SBREG_SMBCTRL 0xc6000c
128 /* Host status bits for SMBPCISTS */
129 #define SMBPCISTS_INTS 0x08
131 /* Control bits for SMBPCICTL */
132 #define SMBPCICTL_INTDIS 0x0400
134 /* Host configuration bits for SMBHSTCFG */
135 #define SMBHSTCFG_HST_EN 1
136 #define SMBHSTCFG_SMB_SMI_EN 2
137 #define SMBHSTCFG_I2C_EN 4
139 /* TCO configuration bits for TCOCTL */
140 #define TCOCTL_EN 0x0100
142 /* Auxiliary control register bits, ICH4+ only */
143 #define SMBAUXCTL_CRC 1
144 #define SMBAUXCTL_E32B 2
147 #define MAX_RETRIES 400
149 /* I801 command constants */
150 #define I801_QUICK 0x00
151 #define I801_BYTE 0x04
152 #define I801_BYTE_DATA 0x08
153 #define I801_WORD_DATA 0x0C
154 #define I801_PROC_CALL 0x10 /* unimplemented */
155 #define I801_BLOCK_DATA 0x14
156 #define I801_I2C_BLOCK_DATA 0x18 /* ICH5 and later */
158 /* I801 Host Control register bits */
159 #define SMBHSTCNT_INTREN 0x01
160 #define SMBHSTCNT_KILL 0x02
161 #define SMBHSTCNT_LAST_BYTE 0x20
162 #define SMBHSTCNT_START 0x40
163 #define SMBHSTCNT_PEC_EN 0x80 /* ICH3 and later */
165 /* I801 Hosts Status register bits */
166 #define SMBHSTSTS_BYTE_DONE 0x80
167 #define SMBHSTSTS_INUSE_STS 0x40
168 #define SMBHSTSTS_SMBALERT_STS 0x20
169 #define SMBHSTSTS_FAILED 0x10
170 #define SMBHSTSTS_BUS_ERR 0x08
171 #define SMBHSTSTS_DEV_ERR 0x04
172 #define SMBHSTSTS_INTR 0x02
173 #define SMBHSTSTS_HOST_BUSY 0x01
175 #define STATUS_ERROR_FLAGS (SMBHSTSTS_FAILED | SMBHSTSTS_BUS_ERR | \
178 #define STATUS_FLAGS (SMBHSTSTS_BYTE_DONE | SMBHSTSTS_INTR | \
181 /* Older devices have their ID defined in <linux/pci_ids.h> */
182 #define PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS 0x0f12
183 #define PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS 0x2292
184 #define PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS 0x1c22
185 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS 0x1d22
186 /* Patsburg also has three 'Integrated Device Function' SMBus controllers */
187 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0 0x1d70
188 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1 0x1d71
189 #define PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2 0x1d72
190 #define PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS 0x1e22
191 #define PCI_DEVICE_ID_INTEL_AVOTON_SMBUS 0x1f3c
192 #define PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS 0x2330
193 #define PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS 0x23b0
194 #define PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS 0x3b30
195 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS 0x8c22
196 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS 0x8ca2
197 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS 0x8d22
198 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0 0x8d7d
199 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1 0x8d7e
200 #define PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2 0x8d7f
201 #define PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS 0x9c22
202 #define PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS 0x9ca2
203 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS 0xa123
204 #define PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS 0x9d23
206 struct i801_mux_config {
211 unsigned gpios[2]; /* Relative to gpio_chip->base */
216 struct i2c_adapter adapter;
218 unsigned char original_hstcfg;
219 struct pci_dev *pci_dev;
220 unsigned int features;
223 wait_queue_head_t waitq;
226 /* Command state used by isr for byte-by-byte block transactions */
233 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
235 const struct i801_mux_config *mux_drvdata;
236 struct platform_device *mux_pdev;
238 struct platform_device *tco_pdev;
241 #define FEATURE_SMBUS_PEC (1 << 0)
242 #define FEATURE_BLOCK_BUFFER (1 << 1)
243 #define FEATURE_BLOCK_PROC (1 << 2)
244 #define FEATURE_I2C_BLOCK_READ (1 << 3)
245 #define FEATURE_IRQ (1 << 4)
246 /* Not really a feature, but it's convenient to handle it as such */
247 #define FEATURE_IDF (1 << 15)
248 #define FEATURE_TCO (1 << 16)
250 static const char *i801_feature_names[] = {
253 "Block process call",
258 static unsigned int disable_features;
259 module_param(disable_features, uint, S_IRUGO | S_IWUSR);
260 MODULE_PARM_DESC(disable_features, "Disable selected driver features:\n"
261 "\t\t 0x01 disable SMBus PEC\n"
262 "\t\t 0x02 disable the block buffer\n"
263 "\t\t 0x08 disable the I2C block read functionality\n"
264 "\t\t 0x10 don't use interrupts ");
266 /* Make sure the SMBus host is ready to start transmitting.
267 Return 0 if it is, -EBUSY if it is not. */
268 static int i801_check_pre(struct i801_priv *priv)
272 status = inb_p(SMBHSTSTS(priv));
273 if (status & SMBHSTSTS_HOST_BUSY) {
274 dev_err(&priv->pci_dev->dev, "SMBus is busy, can't use it!\n");
278 status &= STATUS_FLAGS;
280 dev_dbg(&priv->pci_dev->dev, "Clearing status flags (%02x)\n",
282 outb_p(status, SMBHSTSTS(priv));
283 status = inb_p(SMBHSTSTS(priv)) & STATUS_FLAGS;
285 dev_err(&priv->pci_dev->dev,
286 "Failed clearing status flags (%02x)\n",
296 * Convert the status register to an error code, and clear it.
297 * Note that status only contains the bits we want to clear, not the
298 * actual register value.
300 static int i801_check_post(struct i801_priv *priv, int status)
305 * If the SMBus is still busy, we give up
306 * Note: This timeout condition only happens when using polling
307 * transactions. For interrupt operation, NAK/timeout is indicated by
310 if (unlikely(status < 0)) {
311 dev_err(&priv->pci_dev->dev, "Transaction timeout\n");
312 /* try to stop the current command */
313 dev_dbg(&priv->pci_dev->dev, "Terminating the current operation\n");
314 outb_p(inb_p(SMBHSTCNT(priv)) | SMBHSTCNT_KILL,
316 usleep_range(1000, 2000);
317 outb_p(inb_p(SMBHSTCNT(priv)) & (~SMBHSTCNT_KILL),
320 /* Check if it worked */
321 status = inb_p(SMBHSTSTS(priv));
322 if ((status & SMBHSTSTS_HOST_BUSY) ||
323 !(status & SMBHSTSTS_FAILED))
324 dev_err(&priv->pci_dev->dev,
325 "Failed terminating the transaction\n");
326 outb_p(STATUS_FLAGS, SMBHSTSTS(priv));
330 if (status & SMBHSTSTS_FAILED) {
332 dev_err(&priv->pci_dev->dev, "Transaction failed\n");
334 if (status & SMBHSTSTS_DEV_ERR) {
336 dev_dbg(&priv->pci_dev->dev, "No response\n");
338 if (status & SMBHSTSTS_BUS_ERR) {
340 dev_dbg(&priv->pci_dev->dev, "Lost arbitration\n");
343 /* Clear status flags except BYTE_DONE, to be cleared by caller */
344 outb_p(status, SMBHSTSTS(priv));
349 /* Wait for BUSY being cleared and either INTR or an error flag being set */
350 static int i801_wait_intr(struct i801_priv *priv)
355 /* We will always wait for a fraction of a second! */
357 usleep_range(250, 500);
358 status = inb_p(SMBHSTSTS(priv));
359 } while (((status & SMBHSTSTS_HOST_BUSY) ||
360 !(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR))) &&
361 (timeout++ < MAX_RETRIES));
363 if (timeout > MAX_RETRIES) {
364 dev_dbg(&priv->pci_dev->dev, "INTR Timeout!\n");
367 return status & (STATUS_ERROR_FLAGS | SMBHSTSTS_INTR);
370 /* Wait for either BYTE_DONE or an error flag being set */
371 static int i801_wait_byte_done(struct i801_priv *priv)
376 /* We will always wait for a fraction of a second! */
378 usleep_range(250, 500);
379 status = inb_p(SMBHSTSTS(priv));
380 } while (!(status & (STATUS_ERROR_FLAGS | SMBHSTSTS_BYTE_DONE)) &&
381 (timeout++ < MAX_RETRIES));
383 if (timeout > MAX_RETRIES) {
384 dev_dbg(&priv->pci_dev->dev, "BYTE_DONE Timeout!\n");
387 return status & STATUS_ERROR_FLAGS;
390 static int i801_transaction(struct i801_priv *priv, int xact)
394 const struct i2c_adapter *adap = &priv->adapter;
396 result = i801_check_pre(priv);
400 if (priv->features & FEATURE_IRQ) {
401 outb_p(xact | SMBHSTCNT_INTREN | SMBHSTCNT_START,
403 result = wait_event_timeout(priv->waitq,
404 (status = priv->status),
408 dev_warn(&priv->pci_dev->dev,
409 "Timeout waiting for interrupt!\n");
412 return i801_check_post(priv, status);
415 /* the current contents of SMBHSTCNT can be overwritten, since PEC,
416 * SMBSCMD are passed in xact */
417 outb_p(xact | SMBHSTCNT_START, SMBHSTCNT(priv));
419 status = i801_wait_intr(priv);
420 return i801_check_post(priv, status);
423 static int i801_block_transaction_by_block(struct i801_priv *priv,
424 union i2c_smbus_data *data,
425 char read_write, int hwpec)
430 inb_p(SMBHSTCNT(priv)); /* reset the data buffer index */
432 /* Use 32-byte buffer to process this transaction */
433 if (read_write == I2C_SMBUS_WRITE) {
434 len = data->block[0];
435 outb_p(len, SMBHSTDAT0(priv));
436 for (i = 0; i < len; i++)
437 outb_p(data->block[i+1], SMBBLKDAT(priv));
440 status = i801_transaction(priv, I801_BLOCK_DATA |
441 (hwpec ? SMBHSTCNT_PEC_EN : 0));
445 if (read_write == I2C_SMBUS_READ) {
446 len = inb_p(SMBHSTDAT0(priv));
447 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX)
450 data->block[0] = len;
451 for (i = 0; i < len; i++)
452 data->block[i + 1] = inb_p(SMBBLKDAT(priv));
457 static void i801_isr_byte_done(struct i801_priv *priv)
460 /* For SMBus block reads, length is received with first byte */
461 if (((priv->cmd & 0x1c) == I801_BLOCK_DATA) &&
462 (priv->count == 0)) {
463 priv->len = inb_p(SMBHSTDAT0(priv));
464 if (priv->len < 1 || priv->len > I2C_SMBUS_BLOCK_MAX) {
465 dev_err(&priv->pci_dev->dev,
466 "Illegal SMBus block read size %d\n",
469 priv->len = I2C_SMBUS_BLOCK_MAX;
471 dev_dbg(&priv->pci_dev->dev,
472 "SMBus block read size is %d\n",
475 priv->data[-1] = priv->len;
479 if (priv->count < priv->len)
480 priv->data[priv->count++] = inb(SMBBLKDAT(priv));
482 dev_dbg(&priv->pci_dev->dev,
483 "Discarding extra byte on block read\n");
485 /* Set LAST_BYTE for last byte of read transaction */
486 if (priv->count == priv->len - 1)
487 outb_p(priv->cmd | SMBHSTCNT_LAST_BYTE,
489 } else if (priv->count < priv->len - 1) {
490 /* Write next byte, except for IRQ after last byte */
491 outb_p(priv->data[++priv->count], SMBBLKDAT(priv));
494 /* Clear BYTE_DONE to continue with next byte */
495 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
499 * There are two kinds of interrupts:
501 * 1) i801 signals transaction completion with one of these interrupts:
503 * DEV_ERR - Invalid command, NAK or communication timeout
504 * BUS_ERR - SMI# transaction collision
505 * FAILED - transaction was canceled due to a KILL request
506 * When any of these occur, update ->status and wake up the waitq.
507 * ->status must be cleared before kicking off the next transaction.
509 * 2) For byte-by-byte (I2C read/write) transactions, one BYTE_DONE interrupt
510 * occurs for each byte of a byte-by-byte to prepare the next byte.
512 static irqreturn_t i801_isr(int irq, void *dev_id)
514 struct i801_priv *priv = dev_id;
518 /* Confirm this is our interrupt */
519 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
520 if (!(pcists & SMBPCISTS_INTS))
523 status = inb_p(SMBHSTSTS(priv));
524 if (status & SMBHSTSTS_BYTE_DONE)
525 i801_isr_byte_done(priv);
528 * Clear irq sources and report transaction result.
529 * ->status must be cleared before the next transaction is started.
531 status &= SMBHSTSTS_INTR | STATUS_ERROR_FLAGS;
533 outb_p(status, SMBHSTSTS(priv));
534 priv->status |= status;
535 wake_up(&priv->waitq);
542 * For "byte-by-byte" block transactions:
543 * I2C write uses cmd=I801_BLOCK_DATA, I2C_EN=1
544 * I2C read uses cmd=I801_I2C_BLOCK_DATA
546 static int i801_block_transaction_byte_by_byte(struct i801_priv *priv,
547 union i2c_smbus_data *data,
548 char read_write, int command,
555 const struct i2c_adapter *adap = &priv->adapter;
557 result = i801_check_pre(priv);
561 len = data->block[0];
563 if (read_write == I2C_SMBUS_WRITE) {
564 outb_p(len, SMBHSTDAT0(priv));
565 outb_p(data->block[1], SMBBLKDAT(priv));
568 if (command == I2C_SMBUS_I2C_BLOCK_DATA &&
569 read_write == I2C_SMBUS_READ)
570 smbcmd = I801_I2C_BLOCK_DATA;
572 smbcmd = I801_BLOCK_DATA;
574 if (priv->features & FEATURE_IRQ) {
575 priv->is_read = (read_write == I2C_SMBUS_READ);
576 if (len == 1 && priv->is_read)
577 smbcmd |= SMBHSTCNT_LAST_BYTE;
578 priv->cmd = smbcmd | SMBHSTCNT_INTREN;
581 priv->data = &data->block[1];
583 outb_p(priv->cmd | SMBHSTCNT_START, SMBHSTCNT(priv));
584 result = wait_event_timeout(priv->waitq,
585 (status = priv->status),
589 dev_warn(&priv->pci_dev->dev,
590 "Timeout waiting for interrupt!\n");
593 return i801_check_post(priv, status);
596 for (i = 1; i <= len; i++) {
597 if (i == len && read_write == I2C_SMBUS_READ)
598 smbcmd |= SMBHSTCNT_LAST_BYTE;
599 outb_p(smbcmd, SMBHSTCNT(priv));
602 outb_p(inb(SMBHSTCNT(priv)) | SMBHSTCNT_START,
605 status = i801_wait_byte_done(priv);
609 if (i == 1 && read_write == I2C_SMBUS_READ
610 && command != I2C_SMBUS_I2C_BLOCK_DATA) {
611 len = inb_p(SMBHSTDAT0(priv));
612 if (len < 1 || len > I2C_SMBUS_BLOCK_MAX) {
613 dev_err(&priv->pci_dev->dev,
614 "Illegal SMBus block read size %d\n",
617 while (inb_p(SMBHSTSTS(priv)) &
619 outb_p(SMBHSTSTS_BYTE_DONE,
621 outb_p(SMBHSTSTS_INTR, SMBHSTSTS(priv));
624 data->block[0] = len;
627 /* Retrieve/store value in SMBBLKDAT */
628 if (read_write == I2C_SMBUS_READ)
629 data->block[i] = inb_p(SMBBLKDAT(priv));
630 if (read_write == I2C_SMBUS_WRITE && i+1 <= len)
631 outb_p(data->block[i+1], SMBBLKDAT(priv));
633 /* signals SMBBLKDAT ready */
634 outb_p(SMBHSTSTS_BYTE_DONE, SMBHSTSTS(priv));
637 status = i801_wait_intr(priv);
639 return i801_check_post(priv, status);
642 static int i801_set_block_buffer_mode(struct i801_priv *priv)
644 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_E32B, SMBAUXCTL(priv));
645 if ((inb_p(SMBAUXCTL(priv)) & SMBAUXCTL_E32B) == 0)
650 /* Block transaction function */
651 static int i801_block_transaction(struct i801_priv *priv,
652 union i2c_smbus_data *data, char read_write,
653 int command, int hwpec)
658 if (command == I2C_SMBUS_I2C_BLOCK_DATA) {
659 if (read_write == I2C_SMBUS_WRITE) {
660 /* set I2C_EN bit in configuration register */
661 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &hostc);
662 pci_write_config_byte(priv->pci_dev, SMBHSTCFG,
663 hostc | SMBHSTCFG_I2C_EN);
664 } else if (!(priv->features & FEATURE_I2C_BLOCK_READ)) {
665 dev_err(&priv->pci_dev->dev,
666 "I2C block read is unsupported!\n");
671 if (read_write == I2C_SMBUS_WRITE
672 || command == I2C_SMBUS_I2C_BLOCK_DATA) {
673 if (data->block[0] < 1)
675 if (data->block[0] > I2C_SMBUS_BLOCK_MAX)
676 data->block[0] = I2C_SMBUS_BLOCK_MAX;
678 data->block[0] = 32; /* max for SMBus block reads */
681 /* Experience has shown that the block buffer can only be used for
682 SMBus (not I2C) block transactions, even though the datasheet
683 doesn't mention this limitation. */
684 if ((priv->features & FEATURE_BLOCK_BUFFER)
685 && command != I2C_SMBUS_I2C_BLOCK_DATA
686 && i801_set_block_buffer_mode(priv) == 0)
687 result = i801_block_transaction_by_block(priv, data,
690 result = i801_block_transaction_byte_by_byte(priv, data,
694 if (command == I2C_SMBUS_I2C_BLOCK_DATA
695 && read_write == I2C_SMBUS_WRITE) {
696 /* restore saved configuration register value */
697 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, hostc);
702 /* Return negative errno on error. */
703 static s32 i801_access(struct i2c_adapter *adap, u16 addr,
704 unsigned short flags, char read_write, u8 command,
705 int size, union i2c_smbus_data *data)
710 struct i801_priv *priv = i2c_get_adapdata(adap);
712 hwpec = (priv->features & FEATURE_SMBUS_PEC) && (flags & I2C_CLIENT_PEC)
713 && size != I2C_SMBUS_QUICK
714 && size != I2C_SMBUS_I2C_BLOCK_DATA;
717 case I2C_SMBUS_QUICK:
718 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
723 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
725 if (read_write == I2C_SMBUS_WRITE)
726 outb_p(command, SMBHSTCMD(priv));
729 case I2C_SMBUS_BYTE_DATA:
730 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
732 outb_p(command, SMBHSTCMD(priv));
733 if (read_write == I2C_SMBUS_WRITE)
734 outb_p(data->byte, SMBHSTDAT0(priv));
735 xact = I801_BYTE_DATA;
737 case I2C_SMBUS_WORD_DATA:
738 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
740 outb_p(command, SMBHSTCMD(priv));
741 if (read_write == I2C_SMBUS_WRITE) {
742 outb_p(data->word & 0xff, SMBHSTDAT0(priv));
743 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1(priv));
745 xact = I801_WORD_DATA;
747 case I2C_SMBUS_BLOCK_DATA:
748 outb_p(((addr & 0x7f) << 1) | (read_write & 0x01),
750 outb_p(command, SMBHSTCMD(priv));
753 case I2C_SMBUS_I2C_BLOCK_DATA:
754 /* NB: page 240 of ICH5 datasheet shows that the R/#W
755 * bit should be cleared here, even when reading */
756 outb_p((addr & 0x7f) << 1, SMBHSTADD(priv));
757 if (read_write == I2C_SMBUS_READ) {
758 /* NB: page 240 of ICH5 datasheet also shows
759 * that DATA1 is the cmd field when reading */
760 outb_p(command, SMBHSTDAT1(priv));
762 outb_p(command, SMBHSTCMD(priv));
766 dev_err(&priv->pci_dev->dev, "Unsupported transaction %d\n",
771 if (hwpec) /* enable/disable hardware PEC */
772 outb_p(inb_p(SMBAUXCTL(priv)) | SMBAUXCTL_CRC, SMBAUXCTL(priv));
774 outb_p(inb_p(SMBAUXCTL(priv)) & (~SMBAUXCTL_CRC),
778 ret = i801_block_transaction(priv, data, read_write, size,
781 ret = i801_transaction(priv, xact);
783 /* Some BIOSes don't like it when PEC is enabled at reboot or resume
784 time, so we forcibly disable it after every transaction. Turn off
785 E32B for the same reason. */
787 outb_p(inb_p(SMBAUXCTL(priv)) &
788 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
794 if ((read_write == I2C_SMBUS_WRITE) || (xact == I801_QUICK))
797 switch (xact & 0x7f) {
798 case I801_BYTE: /* Result put in SMBHSTDAT0 */
800 data->byte = inb_p(SMBHSTDAT0(priv));
803 data->word = inb_p(SMBHSTDAT0(priv)) +
804 (inb_p(SMBHSTDAT1(priv)) << 8);
811 static u32 i801_func(struct i2c_adapter *adapter)
813 struct i801_priv *priv = i2c_get_adapdata(adapter);
815 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
816 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
817 I2C_FUNC_SMBUS_BLOCK_DATA | I2C_FUNC_SMBUS_WRITE_I2C_BLOCK |
818 ((priv->features & FEATURE_SMBUS_PEC) ? I2C_FUNC_SMBUS_PEC : 0) |
819 ((priv->features & FEATURE_I2C_BLOCK_READ) ?
820 I2C_FUNC_SMBUS_READ_I2C_BLOCK : 0);
823 static const struct i2c_algorithm smbus_algorithm = {
824 .smbus_xfer = i801_access,
825 .functionality = i801_func,
828 static const struct pci_device_id i801_ids[] = {
829 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AA_3) },
830 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801AB_3) },
831 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801BA_2) },
832 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801CA_3) },
833 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801DB_3) },
834 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82801EB_3) },
835 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB_4) },
836 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH6_16) },
837 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7_17) },
838 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ESB2_17) },
839 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH8_5) },
840 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_6) },
841 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_EP80579_1) },
842 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_4) },
843 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10_5) },
844 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_5_3400_SERIES_SMBUS) },
845 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_SMBUS) },
846 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS) },
847 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0) },
848 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1) },
849 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2) },
850 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_DH89XXCC_SMBUS) },
851 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_SMBUS) },
852 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_SMBUS) },
853 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_LP_SMBUS) },
854 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_AVOTON_SMBUS) },
855 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS) },
856 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0) },
857 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1) },
858 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2) },
859 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COLETOCREEK_SMBUS) },
860 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_SMBUS) },
861 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_WILDCATPOINT_LP_SMBUS) },
862 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BAYTRAIL_SMBUS) },
863 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_BRASWELL_SMBUS) },
864 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS) },
865 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS) },
869 MODULE_DEVICE_TABLE(pci, i801_ids);
871 #if defined CONFIG_X86 && defined CONFIG_DMI
872 static unsigned char apanel_addr;
874 /* Scan the system ROM for the signature "FJKEYINF" */
875 static __init const void __iomem *bios_signature(const void __iomem *bios)
878 const unsigned char signature[] = "FJKEYINF";
880 for (offset = 0; offset < 0x10000; offset += 0x10) {
881 if (check_signature(bios + offset, signature,
882 sizeof(signature)-1))
883 return bios + offset;
888 static void __init input_apanel_init(void)
891 const void __iomem *p;
893 bios = ioremap(0xF0000, 0x10000); /* Can't fail */
894 p = bios_signature(bios);
896 /* just use the first address */
897 apanel_addr = readb(p + 8 + 3) >> 1;
902 struct dmi_onboard_device_info {
905 unsigned short i2c_addr;
906 const char *i2c_type;
909 static const struct dmi_onboard_device_info dmi_devices[] = {
910 { "Syleus", DMI_DEV_TYPE_OTHER, 0x73, "fscsyl" },
911 { "Hermes", DMI_DEV_TYPE_OTHER, 0x73, "fscher" },
912 { "Hades", DMI_DEV_TYPE_OTHER, 0x73, "fschds" },
915 static void dmi_check_onboard_device(u8 type, const char *name,
916 struct i2c_adapter *adap)
919 struct i2c_board_info info;
921 for (i = 0; i < ARRAY_SIZE(dmi_devices); i++) {
922 /* & ~0x80, ignore enabled/disabled bit */
923 if ((type & ~0x80) != dmi_devices[i].type)
925 if (strcasecmp(name, dmi_devices[i].name))
928 memset(&info, 0, sizeof(struct i2c_board_info));
929 info.addr = dmi_devices[i].i2c_addr;
930 strlcpy(info.type, dmi_devices[i].i2c_type, I2C_NAME_SIZE);
931 i2c_new_device(adap, &info);
936 /* We use our own function to check for onboard devices instead of
937 dmi_find_device() as some buggy BIOS's have the devices we are interested
938 in marked as disabled */
939 static void dmi_check_onboard_devices(const struct dmi_header *dm, void *adap)
946 count = (dm->length - sizeof(struct dmi_header)) / 2;
947 for (i = 0; i < count; i++) {
948 const u8 *d = (char *)(dm + 1) + (i * 2);
949 const char *name = ((char *) dm) + dm->length;
956 while (s > 0 && name[0]) {
957 name += strlen(name) + 1;
960 if (name[0] == 0) /* Bogus string reference */
963 dmi_check_onboard_device(type, name, adap);
967 /* Register optional slaves */
968 static void i801_probe_optional_slaves(struct i801_priv *priv)
970 /* Only register slaves on main SMBus channel */
971 if (priv->features & FEATURE_IDF)
975 struct i2c_board_info info;
977 memset(&info, 0, sizeof(struct i2c_board_info));
978 info.addr = apanel_addr;
979 strlcpy(info.type, "fujitsu_apanel", I2C_NAME_SIZE);
980 i2c_new_device(&priv->adapter, &info);
983 if (dmi_name_in_vendors("FUJITSU"))
984 dmi_walk(dmi_check_onboard_devices, &priv->adapter);
987 static void __init input_apanel_init(void) {}
988 static void i801_probe_optional_slaves(struct i801_priv *priv) {}
989 #endif /* CONFIG_X86 && CONFIG_DMI */
991 #if (defined CONFIG_I2C_MUX_GPIO || defined CONFIG_I2C_MUX_GPIO_MODULE) && \
993 static struct i801_mux_config i801_mux_config_asus_z8_d12 = {
994 .gpio_chip = "gpio_ich",
995 .values = { 0x02, 0x03 },
997 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD },
1002 static struct i801_mux_config i801_mux_config_asus_z8_d18 = {
1003 .gpio_chip = "gpio_ich",
1004 .values = { 0x02, 0x03, 0x01 },
1006 .classes = { I2C_CLASS_SPD, I2C_CLASS_SPD, I2C_CLASS_SPD },
1007 .gpios = { 52, 53 },
1011 static const struct dmi_system_id mux_dmi_table[] = {
1014 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1015 DMI_MATCH(DMI_BOARD_NAME, "Z8NA-D6(C)"),
1017 .driver_data = &i801_mux_config_asus_z8_d12,
1021 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1022 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)E-D12(X)"),
1024 .driver_data = &i801_mux_config_asus_z8_d12,
1028 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1029 DMI_MATCH(DMI_BOARD_NAME, "Z8NH-D12"),
1031 .driver_data = &i801_mux_config_asus_z8_d12,
1035 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1036 DMI_MATCH(DMI_BOARD_NAME, "Z8PH-D12/IFB"),
1038 .driver_data = &i801_mux_config_asus_z8_d12,
1042 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1043 DMI_MATCH(DMI_BOARD_NAME, "Z8NR-D12"),
1045 .driver_data = &i801_mux_config_asus_z8_d12,
1049 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1050 DMI_MATCH(DMI_BOARD_NAME, "Z8P(N)H-D12"),
1052 .driver_data = &i801_mux_config_asus_z8_d12,
1056 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1057 DMI_MATCH(DMI_BOARD_NAME, "Z8PG-D18"),
1059 .driver_data = &i801_mux_config_asus_z8_d18,
1063 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1064 DMI_MATCH(DMI_BOARD_NAME, "Z8PE-D18"),
1066 .driver_data = &i801_mux_config_asus_z8_d18,
1070 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
1071 DMI_MATCH(DMI_BOARD_NAME, "Z8PS-D12"),
1073 .driver_data = &i801_mux_config_asus_z8_d12,
1078 /* Setup multiplexing if needed */
1079 static int i801_add_mux(struct i801_priv *priv)
1081 struct device *dev = &priv->adapter.dev;
1082 const struct i801_mux_config *mux_config;
1083 struct i2c_mux_gpio_platform_data gpio_data;
1086 if (!priv->mux_drvdata)
1088 mux_config = priv->mux_drvdata;
1090 /* Prepare the platform data */
1091 memset(&gpio_data, 0, sizeof(struct i2c_mux_gpio_platform_data));
1092 gpio_data.parent = priv->adapter.nr;
1093 gpio_data.values = mux_config->values;
1094 gpio_data.n_values = mux_config->n_values;
1095 gpio_data.classes = mux_config->classes;
1096 gpio_data.gpio_chip = mux_config->gpio_chip;
1097 gpio_data.gpios = mux_config->gpios;
1098 gpio_data.n_gpios = mux_config->n_gpios;
1099 gpio_data.idle = I2C_MUX_GPIO_NO_IDLE;
1101 /* Register the mux device */
1102 priv->mux_pdev = platform_device_register_data(dev, "i2c-mux-gpio",
1103 PLATFORM_DEVID_AUTO, &gpio_data,
1104 sizeof(struct i2c_mux_gpio_platform_data));
1105 if (IS_ERR(priv->mux_pdev)) {
1106 err = PTR_ERR(priv->mux_pdev);
1107 priv->mux_pdev = NULL;
1108 dev_err(dev, "Failed to register i2c-mux-gpio device\n");
1115 static void i801_del_mux(struct i801_priv *priv)
1118 platform_device_unregister(priv->mux_pdev);
1121 static unsigned int i801_get_adapter_class(struct i801_priv *priv)
1123 const struct dmi_system_id *id;
1124 const struct i801_mux_config *mux_config;
1125 unsigned int class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
1128 id = dmi_first_match(mux_dmi_table);
1130 /* Remove branch classes from trunk */
1131 mux_config = id->driver_data;
1132 for (i = 0; i < mux_config->n_values; i++)
1133 class &= ~mux_config->classes[i];
1135 /* Remember for later */
1136 priv->mux_drvdata = mux_config;
1142 static inline int i801_add_mux(struct i801_priv *priv) { return 0; }
1143 static inline void i801_del_mux(struct i801_priv *priv) { }
1145 static inline unsigned int i801_get_adapter_class(struct i801_priv *priv)
1147 return I2C_CLASS_HWMON | I2C_CLASS_SPD;
1151 static const struct itco_wdt_platform_data tco_platform_data = {
1152 .name = "Intel PCH",
1156 static DEFINE_SPINLOCK(p2sb_spinlock);
1158 static void i801_add_tco(struct i801_priv *priv)
1160 struct pci_dev *pci_dev = priv->pci_dev;
1161 struct resource tco_res[3], *res;
1162 struct platform_device *pdev;
1164 u32 tco_base, tco_ctl;
1165 u32 base_addr, ctrl_val;
1168 if (!(priv->features & FEATURE_TCO))
1171 pci_read_config_dword(pci_dev, TCOBASE, &tco_base);
1172 pci_read_config_dword(pci_dev, TCOCTL, &tco_ctl);
1173 if (!(tco_ctl & TCOCTL_EN))
1176 memset(tco_res, 0, sizeof(tco_res));
1178 res = &tco_res[ICH_RES_IO_TCO];
1179 res->start = tco_base & ~1;
1180 res->end = res->start + 32 - 1;
1181 res->flags = IORESOURCE_IO;
1184 * Power Management registers.
1186 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 2);
1187 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPIBASE, &base_addr);
1189 res = &tco_res[ICH_RES_IO_SMI];
1190 res->start = (base_addr & ~1) + ACPIBASE_SMI_OFF;
1191 res->end = res->start + 3;
1192 res->flags = IORESOURCE_IO;
1195 * Enable the ACPI I/O space.
1197 pci_bus_read_config_dword(pci_dev->bus, devfn, ACPICTRL, &ctrl_val);
1198 ctrl_val |= ACPICTRL_EN;
1199 pci_bus_write_config_dword(pci_dev->bus, devfn, ACPICTRL, ctrl_val);
1202 * We must access the NO_REBOOT bit over the Primary to Sideband
1203 * bridge (P2SB). The BIOS prevents the P2SB device from being
1204 * enumerated by the PCI subsystem, so we need to unhide/hide it
1205 * to lookup the P2SB BAR.
1207 spin_lock(&p2sb_spinlock);
1209 devfn = PCI_DEVFN(PCI_SLOT(pci_dev->devfn), 1);
1211 /* Unhide the P2SB device */
1212 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x0);
1214 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR, &base_addr);
1215 base64_addr = base_addr & 0xfffffff0;
1217 pci_bus_read_config_dword(pci_dev->bus, devfn, SBREG_BAR + 0x4, &base_addr);
1218 base64_addr |= (u64)base_addr << 32;
1220 /* Hide the P2SB device */
1221 pci_bus_write_config_byte(pci_dev->bus, devfn, 0xe1, 0x1);
1222 spin_unlock(&p2sb_spinlock);
1224 res = &tco_res[ICH_RES_MEM_OFF];
1225 res->start = (resource_size_t)base64_addr + SBREG_SMBCTRL;
1226 res->end = res->start + 3;
1227 res->flags = IORESOURCE_MEM;
1229 pdev = platform_device_register_resndata(&pci_dev->dev, "iTCO_wdt", -1,
1230 tco_res, 3, &tco_platform_data,
1231 sizeof(tco_platform_data));
1233 dev_warn(&pci_dev->dev, "failed to create iTCO device\n");
1237 priv->tco_pdev = pdev;
1240 static int i801_probe(struct pci_dev *dev, const struct pci_device_id *id)
1244 struct i801_priv *priv;
1246 priv = devm_kzalloc(&dev->dev, sizeof(*priv), GFP_KERNEL);
1250 i2c_set_adapdata(&priv->adapter, priv);
1251 priv->adapter.owner = THIS_MODULE;
1252 priv->adapter.class = i801_get_adapter_class(priv);
1253 priv->adapter.algo = &smbus_algorithm;
1255 priv->pci_dev = dev;
1256 switch (dev->device) {
1257 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_H_SMBUS:
1258 case PCI_DEVICE_ID_INTEL_SUNRISEPOINT_LP_SMBUS:
1259 priv->features |= FEATURE_I2C_BLOCK_READ;
1260 priv->features |= FEATURE_IRQ;
1261 priv->features |= FEATURE_SMBUS_PEC;
1262 priv->features |= FEATURE_BLOCK_BUFFER;
1263 priv->features |= FEATURE_TCO;
1266 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF0:
1267 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF1:
1268 case PCI_DEVICE_ID_INTEL_PATSBURG_SMBUS_IDF2:
1269 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS0:
1270 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS1:
1271 case PCI_DEVICE_ID_INTEL_WELLSBURG_SMBUS_MS2:
1272 priv->features |= FEATURE_IDF;
1275 priv->features |= FEATURE_I2C_BLOCK_READ;
1276 priv->features |= FEATURE_IRQ;
1278 case PCI_DEVICE_ID_INTEL_82801DB_3:
1279 priv->features |= FEATURE_SMBUS_PEC;
1280 priv->features |= FEATURE_BLOCK_BUFFER;
1282 case PCI_DEVICE_ID_INTEL_82801CA_3:
1283 case PCI_DEVICE_ID_INTEL_82801BA_2:
1284 case PCI_DEVICE_ID_INTEL_82801AB_3:
1285 case PCI_DEVICE_ID_INTEL_82801AA_3:
1289 /* Disable features on user request */
1290 for (i = 0; i < ARRAY_SIZE(i801_feature_names); i++) {
1291 if (priv->features & disable_features & (1 << i))
1292 dev_notice(&dev->dev, "%s disabled by user\n",
1293 i801_feature_names[i]);
1295 priv->features &= ~disable_features;
1297 err = pcim_enable_device(dev);
1299 dev_err(&dev->dev, "Failed to enable SMBus PCI device (%d)\n",
1303 pcim_pin_device(dev);
1305 /* Determine the address of the SMBus area */
1306 priv->smba = pci_resource_start(dev, SMBBAR);
1309 "SMBus base address uninitialized, upgrade BIOS\n");
1313 err = acpi_check_resource_conflict(&dev->resource[SMBBAR]);
1318 err = pcim_iomap_regions(dev, 1 << SMBBAR,
1319 dev_driver_string(&dev->dev));
1322 "Failed to request SMBus region 0x%lx-0x%Lx\n",
1324 (unsigned long long)pci_resource_end(dev, SMBBAR));
1328 pci_read_config_byte(priv->pci_dev, SMBHSTCFG, &temp);
1329 priv->original_hstcfg = temp;
1330 temp &= ~SMBHSTCFG_I2C_EN; /* SMBus timing */
1331 if (!(temp & SMBHSTCFG_HST_EN)) {
1332 dev_info(&dev->dev, "Enabling SMBus device\n");
1333 temp |= SMBHSTCFG_HST_EN;
1335 pci_write_config_byte(priv->pci_dev, SMBHSTCFG, temp);
1337 if (temp & SMBHSTCFG_SMB_SMI_EN) {
1338 dev_dbg(&dev->dev, "SMBus using interrupt SMI#\n");
1339 /* Disable SMBus interrupt feature if SMBus using SMI# */
1340 priv->features &= ~FEATURE_IRQ;
1343 /* Clear special mode bits */
1344 if (priv->features & (FEATURE_SMBUS_PEC | FEATURE_BLOCK_BUFFER))
1345 outb_p(inb_p(SMBAUXCTL(priv)) &
1346 ~(SMBAUXCTL_CRC | SMBAUXCTL_E32B), SMBAUXCTL(priv));
1348 /* Default timeout in interrupt mode: 200 ms */
1349 priv->adapter.timeout = HZ / 5;
1351 if (priv->features & FEATURE_IRQ) {
1354 /* Complain if an interrupt is already pending */
1355 pci_read_config_word(priv->pci_dev, SMBPCISTS, &pcists);
1356 if (pcists & SMBPCISTS_INTS)
1357 dev_warn(&dev->dev, "An interrupt is pending!\n");
1359 /* Check if interrupts have been disabled */
1360 pci_read_config_word(priv->pci_dev, SMBPCICTL, &pcictl);
1361 if (pcictl & SMBPCICTL_INTDIS) {
1362 dev_info(&dev->dev, "Interrupts are disabled\n");
1363 priv->features &= ~FEATURE_IRQ;
1367 if (priv->features & FEATURE_IRQ) {
1368 init_waitqueue_head(&priv->waitq);
1370 err = devm_request_irq(&dev->dev, dev->irq, i801_isr,
1372 dev_driver_string(&dev->dev), priv);
1374 dev_err(&dev->dev, "Failed to allocate irq %d: %d\n",
1376 priv->features &= ~FEATURE_IRQ;
1379 dev_info(&dev->dev, "SMBus using %s\n",
1380 priv->features & FEATURE_IRQ ? "PCI interrupt" : "polling");
1384 /* set up the sysfs linkage to our parent device */
1385 priv->adapter.dev.parent = &dev->dev;
1387 /* Retry up to 3 times on lost arbitration */
1388 priv->adapter.retries = 3;
1390 snprintf(priv->adapter.name, sizeof(priv->adapter.name),
1391 "SMBus I801 adapter at %04lx", priv->smba);
1392 err = i2c_add_adapter(&priv->adapter);
1394 dev_err(&dev->dev, "Failed to add SMBus adapter\n");
1398 i801_probe_optional_slaves(priv);
1399 /* We ignore errors - multiplexing is optional */
1402 pci_set_drvdata(dev, priv);
1407 static void i801_remove(struct pci_dev *dev)
1409 struct i801_priv *priv = pci_get_drvdata(dev);
1412 i2c_del_adapter(&priv->adapter);
1413 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1415 platform_device_unregister(priv->tco_pdev);
1418 * do not call pci_disable_device(dev) since it can cause hard hangs on
1419 * some systems during power-off (eg. Fujitsu-Siemens Lifebook E8010)
1424 static int i801_suspend(struct pci_dev *dev, pm_message_t mesg)
1426 struct i801_priv *priv = pci_get_drvdata(dev);
1428 pci_save_state(dev);
1429 pci_write_config_byte(dev, SMBHSTCFG, priv->original_hstcfg);
1430 pci_set_power_state(dev, pci_choose_state(dev, mesg));
1434 static int i801_resume(struct pci_dev *dev)
1436 pci_set_power_state(dev, PCI_D0);
1437 pci_restore_state(dev);
1441 #define i801_suspend NULL
1442 #define i801_resume NULL
1445 static struct pci_driver i801_driver = {
1446 .name = "i801_smbus",
1447 .id_table = i801_ids,
1448 .probe = i801_probe,
1449 .remove = i801_remove,
1450 .suspend = i801_suspend,
1451 .resume = i801_resume,
1454 static int __init i2c_i801_init(void)
1456 if (dmi_name_in_vendors("FUJITSU"))
1457 input_apanel_init();
1458 return pci_register_driver(&i801_driver);
1461 static void __exit i2c_i801_exit(void)
1463 pci_unregister_driver(&i801_driver);
1466 MODULE_AUTHOR("Mark D. Studebaker <mdsxyz123@yahoo.com>, Jean Delvare <jdelvare@suse.de>");
1467 MODULE_DESCRIPTION("I801 SMBus driver");
1468 MODULE_LICENSE("GPL");
1470 module_init(i2c_i801_init);
1471 module_exit(i2c_i801_exit);