2 * Driver for the i2c controller on the Marvell line of host bridges
3 * (e.g, gt642[46]0, mv643[46]0, mv644[46]0, and Orion SoC family).
5 * Author: Mark A. Greer <mgreer@mvista.com>
7 * 2005 (c) MontaVista, Software, Inc. This file is licensed under
8 * the terms of the GNU General Public License version 2. This program
9 * is licensed "as is" without any warranty of any kind, whether express
12 #include <linux/kernel.h>
13 #include <linux/slab.h>
14 #include <linux/module.h>
15 #include <linux/spinlock.h>
16 #include <linux/i2c.h>
17 #include <linux/interrupt.h>
18 #include <linux/mv643xx_i2c.h>
19 #include <linux/platform_device.h>
22 #include <linux/of_irq.h>
23 #include <linux/of_i2c.h>
24 #include <linux/clk.h>
25 #include <linux/err.h>
27 /* Register defines */
28 #define MV64XXX_I2C_REG_SLAVE_ADDR 0x00
29 #define MV64XXX_I2C_REG_DATA 0x04
30 #define MV64XXX_I2C_REG_CONTROL 0x08
31 #define MV64XXX_I2C_REG_STATUS 0x0c
32 #define MV64XXX_I2C_REG_BAUD 0x0c
33 #define MV64XXX_I2C_REG_EXT_SLAVE_ADDR 0x10
34 #define MV64XXX_I2C_REG_SOFT_RESET 0x1c
36 #define MV64XXX_I2C_REG_CONTROL_ACK 0x00000004
37 #define MV64XXX_I2C_REG_CONTROL_IFLG 0x00000008
38 #define MV64XXX_I2C_REG_CONTROL_STOP 0x00000010
39 #define MV64XXX_I2C_REG_CONTROL_START 0x00000020
40 #define MV64XXX_I2C_REG_CONTROL_TWSIEN 0x00000040
41 #define MV64XXX_I2C_REG_CONTROL_INTEN 0x00000080
43 /* Ctlr status values */
44 #define MV64XXX_I2C_STATUS_BUS_ERR 0x00
45 #define MV64XXX_I2C_STATUS_MAST_START 0x08
46 #define MV64XXX_I2C_STATUS_MAST_REPEAT_START 0x10
47 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK 0x18
48 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK 0x20
49 #define MV64XXX_I2C_STATUS_MAST_WR_ACK 0x28
50 #define MV64XXX_I2C_STATUS_MAST_WR_NO_ACK 0x30
51 #define MV64XXX_I2C_STATUS_MAST_LOST_ARB 0x38
52 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK 0x40
53 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK 0x48
54 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK 0x50
55 #define MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK 0x58
56 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK 0xd0
57 #define MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_NO_ACK 0xd8
58 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK 0xe0
59 #define MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_NO_ACK 0xe8
60 #define MV64XXX_I2C_STATUS_NO_STATUS 0xf8
64 MV64XXX_I2C_STATE_INVALID,
65 MV64XXX_I2C_STATE_IDLE,
66 MV64XXX_I2C_STATE_WAITING_FOR_START_COND,
67 MV64XXX_I2C_STATE_WAITING_FOR_RESTART,
68 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK,
69 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK,
70 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK,
71 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA,
76 MV64XXX_I2C_ACTION_INVALID,
77 MV64XXX_I2C_ACTION_CONTINUE,
78 MV64XXX_I2C_ACTION_SEND_START,
79 MV64XXX_I2C_ACTION_SEND_RESTART,
80 MV64XXX_I2C_ACTION_SEND_ADDR_1,
81 MV64XXX_I2C_ACTION_SEND_ADDR_2,
82 MV64XXX_I2C_ACTION_SEND_DATA,
83 MV64XXX_I2C_ACTION_RCV_DATA,
84 MV64XXX_I2C_ACTION_RCV_DATA_STOP,
85 MV64XXX_I2C_ACTION_SEND_STOP,
88 struct mv64xxx_i2c_data {
96 void __iomem *reg_base;
106 #if defined(CONFIG_HAVE_CLK)
109 wait_queue_head_t waitq;
112 struct i2c_adapter adapter;
116 mv64xxx_i2c_prepare_for_io(struct mv64xxx_i2c_data *drv_data,
122 drv_data->byte_posn = 0;
123 drv_data->bytes_left = msg->len;
124 drv_data->aborting = 0;
126 drv_data->cntl_bits = MV64XXX_I2C_REG_CONTROL_ACK |
127 MV64XXX_I2C_REG_CONTROL_INTEN | MV64XXX_I2C_REG_CONTROL_TWSIEN;
129 if (msg->flags & I2C_M_RD)
132 if (msg->flags & I2C_M_TEN) {
133 drv_data->addr1 = 0xf0 | (((u32)msg->addr & 0x300) >> 7) | dir;
134 drv_data->addr2 = (u32)msg->addr & 0xff;
136 drv_data->addr1 = ((u32)msg->addr & 0x7f) << 1 | dir;
142 *****************************************************************************
144 * Finite State Machine & Interrupt Routines
146 *****************************************************************************
149 /* Reset hardware and initialize FSM */
151 mv64xxx_i2c_hw_init(struct mv64xxx_i2c_data *drv_data)
153 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SOFT_RESET);
154 writel((((drv_data->freq_m & 0xf) << 3) | (drv_data->freq_n & 0x7)),
155 drv_data->reg_base + MV64XXX_I2C_REG_BAUD);
156 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_SLAVE_ADDR);
157 writel(0, drv_data->reg_base + MV64XXX_I2C_REG_EXT_SLAVE_ADDR);
158 writel(MV64XXX_I2C_REG_CONTROL_TWSIEN | MV64XXX_I2C_REG_CONTROL_STOP,
159 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
160 drv_data->state = MV64XXX_I2C_STATE_IDLE;
164 mv64xxx_i2c_fsm(struct mv64xxx_i2c_data *drv_data, u32 status)
167 * If state is idle, then this is likely the remnants of an old
168 * operation that driver has given up on or the user has killed.
169 * If so, issue the stop condition and go to idle.
171 if (drv_data->state == MV64XXX_I2C_STATE_IDLE) {
172 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
176 /* The status from the ctlr [mostly] tells us what to do next */
178 /* Start condition interrupt */
179 case MV64XXX_I2C_STATUS_MAST_START: /* 0x08 */
180 case MV64XXX_I2C_STATUS_MAST_REPEAT_START: /* 0x10 */
181 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_1;
182 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_ADDR_1_ACK;
185 /* Performing a write */
186 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_ACK: /* 0x18 */
187 if (drv_data->msg->flags & I2C_M_TEN) {
188 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
190 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
194 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_2_ACK: /* 0xd0 */
195 case MV64XXX_I2C_STATUS_MAST_WR_ACK: /* 0x28 */
196 if ((drv_data->bytes_left == 0)
197 || (drv_data->aborting
198 && (drv_data->byte_posn != 0))) {
199 if (drv_data->send_stop || drv_data->aborting) {
200 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
201 drv_data->state = MV64XXX_I2C_STATE_IDLE;
204 MV64XXX_I2C_ACTION_SEND_RESTART;
206 MV64XXX_I2C_STATE_WAITING_FOR_RESTART;
209 drv_data->action = MV64XXX_I2C_ACTION_SEND_DATA;
211 MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_ACK;
212 drv_data->bytes_left--;
216 /* Performing a read */
217 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_ACK: /* 40 */
218 if (drv_data->msg->flags & I2C_M_TEN) {
219 drv_data->action = MV64XXX_I2C_ACTION_SEND_ADDR_2;
221 MV64XXX_I2C_STATE_WAITING_FOR_ADDR_2_ACK;
225 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_2_ACK: /* 0xe0 */
226 if (drv_data->bytes_left == 0) {
227 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
228 drv_data->state = MV64XXX_I2C_STATE_IDLE;
232 case MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK: /* 0x50 */
233 if (status != MV64XXX_I2C_STATUS_MAST_RD_DATA_ACK)
234 drv_data->action = MV64XXX_I2C_ACTION_CONTINUE;
236 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA;
237 drv_data->bytes_left--;
239 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_SLAVE_DATA;
241 if ((drv_data->bytes_left == 1) || drv_data->aborting)
242 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_ACK;
245 case MV64XXX_I2C_STATUS_MAST_RD_DATA_NO_ACK: /* 0x58 */
246 drv_data->action = MV64XXX_I2C_ACTION_RCV_DATA_STOP;
247 drv_data->state = MV64XXX_I2C_STATE_IDLE;
250 case MV64XXX_I2C_STATUS_MAST_WR_ADDR_NO_ACK: /* 0x20 */
251 case MV64XXX_I2C_STATUS_MAST_WR_NO_ACK: /* 30 */
252 case MV64XXX_I2C_STATUS_MAST_RD_ADDR_NO_ACK: /* 48 */
253 /* Doesn't seem to be a device at other end */
254 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
255 drv_data->state = MV64XXX_I2C_STATE_IDLE;
256 drv_data->rc = -ENODEV;
260 dev_err(&drv_data->adapter.dev,
261 "mv64xxx_i2c_fsm: Ctlr Error -- state: 0x%x, "
262 "status: 0x%x, addr: 0x%x, flags: 0x%x\n",
263 drv_data->state, status, drv_data->msg->addr,
264 drv_data->msg->flags);
265 drv_data->action = MV64XXX_I2C_ACTION_SEND_STOP;
266 mv64xxx_i2c_hw_init(drv_data);
272 mv64xxx_i2c_do_action(struct mv64xxx_i2c_data *drv_data)
274 switch(drv_data->action) {
275 case MV64XXX_I2C_ACTION_SEND_RESTART:
276 /* We should only get here if we have further messages */
277 BUG_ON(drv_data->num_msgs == 0);
279 drv_data->cntl_bits |= MV64XXX_I2C_REG_CONTROL_START;
280 writel(drv_data->cntl_bits,
281 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
284 drv_data->num_msgs--;
286 /* Setup for the next message */
287 mv64xxx_i2c_prepare_for_io(drv_data, drv_data->msgs);
290 * We're never at the start of the message here, and by this
291 * time it's already too late to do any protocol mangling.
292 * Thankfully, do not advertise support for that feature.
294 drv_data->send_stop = drv_data->num_msgs == 1;
297 case MV64XXX_I2C_ACTION_CONTINUE:
298 writel(drv_data->cntl_bits,
299 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
302 case MV64XXX_I2C_ACTION_SEND_START:
303 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_START,
304 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
307 case MV64XXX_I2C_ACTION_SEND_ADDR_1:
308 writel(drv_data->addr1,
309 drv_data->reg_base + MV64XXX_I2C_REG_DATA);
310 writel(drv_data->cntl_bits,
311 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
314 case MV64XXX_I2C_ACTION_SEND_ADDR_2:
315 writel(drv_data->addr2,
316 drv_data->reg_base + MV64XXX_I2C_REG_DATA);
317 writel(drv_data->cntl_bits,
318 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
321 case MV64XXX_I2C_ACTION_SEND_DATA:
322 writel(drv_data->msg->buf[drv_data->byte_posn++],
323 drv_data->reg_base + MV64XXX_I2C_REG_DATA);
324 writel(drv_data->cntl_bits,
325 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
328 case MV64XXX_I2C_ACTION_RCV_DATA:
329 drv_data->msg->buf[drv_data->byte_posn++] =
330 readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA);
331 writel(drv_data->cntl_bits,
332 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
335 case MV64XXX_I2C_ACTION_RCV_DATA_STOP:
336 drv_data->msg->buf[drv_data->byte_posn++] =
337 readl(drv_data->reg_base + MV64XXX_I2C_REG_DATA);
338 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
339 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
340 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
342 wake_up(&drv_data->waitq);
345 case MV64XXX_I2C_ACTION_INVALID:
347 dev_err(&drv_data->adapter.dev,
348 "mv64xxx_i2c_do_action: Invalid action: %d\n",
352 case MV64XXX_I2C_ACTION_SEND_STOP:
353 drv_data->cntl_bits &= ~MV64XXX_I2C_REG_CONTROL_INTEN;
354 writel(drv_data->cntl_bits | MV64XXX_I2C_REG_CONTROL_STOP,
355 drv_data->reg_base + MV64XXX_I2C_REG_CONTROL);
357 wake_up(&drv_data->waitq);
363 mv64xxx_i2c_intr(int irq, void *dev_id)
365 struct mv64xxx_i2c_data *drv_data = dev_id;
368 irqreturn_t rc = IRQ_NONE;
370 spin_lock_irqsave(&drv_data->lock, flags);
371 while (readl(drv_data->reg_base + MV64XXX_I2C_REG_CONTROL) &
372 MV64XXX_I2C_REG_CONTROL_IFLG) {
373 status = readl(drv_data->reg_base + MV64XXX_I2C_REG_STATUS);
374 mv64xxx_i2c_fsm(drv_data, status);
375 mv64xxx_i2c_do_action(drv_data);
378 spin_unlock_irqrestore(&drv_data->lock, flags);
384 *****************************************************************************
386 * I2C Msg Execution Routines
388 *****************************************************************************
391 mv64xxx_i2c_wait_for_completion(struct mv64xxx_i2c_data *drv_data)
397 time_left = wait_event_timeout(drv_data->waitq,
398 !drv_data->block, drv_data->adapter.timeout);
400 spin_lock_irqsave(&drv_data->lock, flags);
401 if (!time_left) { /* Timed out */
402 drv_data->rc = -ETIMEDOUT;
404 } else if (time_left < 0) { /* Interrupted/Error */
405 drv_data->rc = time_left; /* errno value */
409 if (abort && drv_data->block) {
410 drv_data->aborting = 1;
411 spin_unlock_irqrestore(&drv_data->lock, flags);
413 time_left = wait_event_timeout(drv_data->waitq,
414 !drv_data->block, drv_data->adapter.timeout);
416 if ((time_left <= 0) && drv_data->block) {
417 drv_data->state = MV64XXX_I2C_STATE_IDLE;
418 dev_err(&drv_data->adapter.dev,
419 "mv64xxx: I2C bus locked, block: %d, "
420 "time_left: %d\n", drv_data->block,
422 mv64xxx_i2c_hw_init(drv_data);
425 spin_unlock_irqrestore(&drv_data->lock, flags);
429 mv64xxx_i2c_execute_msg(struct mv64xxx_i2c_data *drv_data, struct i2c_msg *msg,
434 spin_lock_irqsave(&drv_data->lock, flags);
435 mv64xxx_i2c_prepare_for_io(drv_data, msg);
437 drv_data->action = MV64XXX_I2C_ACTION_SEND_START;
438 drv_data->state = MV64XXX_I2C_STATE_WAITING_FOR_START_COND;
440 drv_data->send_stop = is_last;
442 mv64xxx_i2c_do_action(drv_data);
443 spin_unlock_irqrestore(&drv_data->lock, flags);
445 mv64xxx_i2c_wait_for_completion(drv_data);
450 *****************************************************************************
452 * I2C Core Support Routines (Interface to higher level I2C code)
454 *****************************************************************************
457 mv64xxx_i2c_functionality(struct i2c_adapter *adap)
459 return I2C_FUNC_I2C | I2C_FUNC_10BIT_ADDR | I2C_FUNC_SMBUS_EMUL;
463 mv64xxx_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
465 struct mv64xxx_i2c_data *drv_data = i2c_get_adapdata(adap);
468 BUG_ON(drv_data->msgs != NULL);
469 drv_data->msgs = msgs;
470 drv_data->num_msgs = num;
472 rc = mv64xxx_i2c_execute_msg(drv_data, &msgs[0], num == 1);
476 drv_data->num_msgs = 0;
477 drv_data->msgs = NULL;
482 static const struct i2c_algorithm mv64xxx_i2c_algo = {
483 .master_xfer = mv64xxx_i2c_xfer,
484 .functionality = mv64xxx_i2c_functionality,
488 *****************************************************************************
490 * Driver Interface & Early Init Routines
492 *****************************************************************************
496 mv64xxx_calc_freq(const int tclk, const int n, const int m)
498 return tclk / (10 * (m + 1) * (2 << n));
502 mv64xxx_find_baud_factors(const u32 req_freq, const u32 tclk, u32 *best_n,
505 int freq, delta, best_delta = INT_MAX;
508 for (n = 0; n <= 7; n++)
509 for (m = 0; m <= 15; m++) {
510 freq = mv64xxx_calc_freq(tclk, n, m);
511 delta = req_freq - freq;
512 if (delta >= 0 && delta < best_delta) {
520 if (best_delta == INT_MAX)
526 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
527 struct device_node *np)
532 /* CLK is mandatory when using DT to describe the i2c bus. We
533 * need to know tclk in order to calculate bus clock
536 #if !defined(CONFIG_HAVE_CLK)
537 /* Have OF but no CLK */
540 if (IS_ERR(drv_data->clk)) {
544 tclk = clk_get_rate(drv_data->clk);
545 of_property_read_u32(np, "clock-frequency", &bus_freq);
546 if (!mv64xxx_find_baud_factors(bus_freq, tclk,
547 &drv_data->freq_n, &drv_data->freq_m)) {
551 drv_data->irq = irq_of_parse_and_map(np, 0);
553 /* Its not yet defined how timeouts will be specified in device tree.
554 * So hard code the value to 1 second.
556 drv_data->adapter.timeout = HZ;
561 #else /* CONFIG_OF */
563 mv64xxx_of_config(struct mv64xxx_i2c_data *drv_data,
564 struct device_node *np)
568 #endif /* CONFIG_OF */
571 mv64xxx_i2c_probe(struct platform_device *pd)
573 struct mv64xxx_i2c_data *drv_data;
574 struct mv64xxx_i2c_pdata *pdata = pd->dev.platform_data;
578 if ((!pdata && !pd->dev.of_node))
581 drv_data = devm_kzalloc(&pd->dev, sizeof(struct mv64xxx_i2c_data),
586 r = platform_get_resource(pd, IORESOURCE_MEM, 0);
587 drv_data->reg_base = devm_ioremap_resource(&pd->dev, r);
588 if (IS_ERR(drv_data->reg_base))
589 return PTR_ERR(drv_data->reg_base);
591 strlcpy(drv_data->adapter.name, MV64XXX_I2C_CTLR_NAME " adapter",
592 sizeof(drv_data->adapter.name));
594 init_waitqueue_head(&drv_data->waitq);
595 spin_lock_init(&drv_data->lock);
597 #if defined(CONFIG_HAVE_CLK)
598 /* Not all platforms have a clk */
599 drv_data->clk = devm_clk_get(&pd->dev, NULL);
600 if (!IS_ERR(drv_data->clk)) {
601 clk_prepare(drv_data->clk);
602 clk_enable(drv_data->clk);
606 drv_data->freq_m = pdata->freq_m;
607 drv_data->freq_n = pdata->freq_n;
608 drv_data->irq = platform_get_irq(pd, 0);
609 drv_data->adapter.timeout = msecs_to_jiffies(pdata->timeout);
610 } else if (pd->dev.of_node) {
611 rc = mv64xxx_of_config(drv_data, pd->dev.of_node);
615 if (drv_data->irq < 0) {
620 drv_data->adapter.dev.parent = &pd->dev;
621 drv_data->adapter.algo = &mv64xxx_i2c_algo;
622 drv_data->adapter.owner = THIS_MODULE;
623 drv_data->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
624 drv_data->adapter.nr = pd->id;
625 drv_data->adapter.dev.of_node = pd->dev.of_node;
626 platform_set_drvdata(pd, drv_data);
627 i2c_set_adapdata(&drv_data->adapter, drv_data);
629 mv64xxx_i2c_hw_init(drv_data);
631 rc = request_irq(drv_data->irq, mv64xxx_i2c_intr, 0,
632 MV64XXX_I2C_CTLR_NAME, drv_data);
634 dev_err(&drv_data->adapter.dev,
635 "mv64xxx: Can't register intr handler irq%d: %d\n",
638 } else if ((rc = i2c_add_numbered_adapter(&drv_data->adapter)) != 0) {
639 dev_err(&drv_data->adapter.dev,
640 "mv64xxx: Can't add i2c adapter, rc: %d\n", -rc);
644 of_i2c_register_devices(&drv_data->adapter);
649 free_irq(drv_data->irq, drv_data);
651 #if defined(CONFIG_HAVE_CLK)
652 /* Not all platforms have a clk */
653 if (!IS_ERR(drv_data->clk)) {
654 clk_disable(drv_data->clk);
655 clk_unprepare(drv_data->clk);
662 mv64xxx_i2c_remove(struct platform_device *dev)
664 struct mv64xxx_i2c_data *drv_data = platform_get_drvdata(dev);
666 i2c_del_adapter(&drv_data->adapter);
667 free_irq(drv_data->irq, drv_data);
668 #if defined(CONFIG_HAVE_CLK)
669 /* Not all platforms have a clk */
670 if (!IS_ERR(drv_data->clk)) {
671 clk_disable(drv_data->clk);
672 clk_unprepare(drv_data->clk);
679 static const struct of_device_id mv64xxx_i2c_of_match_table[] = {
680 { .compatible = "marvell,mv64xxx-i2c", },
683 MODULE_DEVICE_TABLE(of, mv64xxx_i2c_of_match_table);
685 static struct platform_driver mv64xxx_i2c_driver = {
686 .probe = mv64xxx_i2c_probe,
687 .remove = mv64xxx_i2c_remove,
689 .owner = THIS_MODULE,
690 .name = MV64XXX_I2C_CTLR_NAME,
691 .of_match_table = of_match_ptr(mv64xxx_i2c_of_match_table),
695 module_platform_driver(mv64xxx_i2c_driver);
697 MODULE_AUTHOR("Mark A. Greer <mgreer@mvista.com>");
698 MODULE_DESCRIPTION("Marvell mv64xxx host bridge i2c ctlr driver");
699 MODULE_LICENSE("GPL");