2 * Freescale MXS I2C bus driver
4 * Copyright (C) 2011 Wolfram Sang, Pengutronix e.K.
6 * based on a (non-working) driver which was:
8 * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. All Rights Reserved.
10 * TODO: add dma-support if platform-support for it is available
12 * This program is free software; you can redistribute it and/or modify
13 * it under the terms of the GNU General Public License as published by
14 * the Free Software Foundation; either version 2 of the License, or
15 * (at your option) any later version.
19 #include <linux/slab.h>
20 #include <linux/device.h>
21 #include <linux/module.h>
22 #include <linux/i2c.h>
23 #include <linux/err.h>
24 #include <linux/interrupt.h>
25 #include <linux/completion.h>
26 #include <linux/platform_device.h>
27 #include <linux/jiffies.h>
29 #include <linux/pinctrl/consumer.h>
30 #include <linux/stmp_device.h>
32 #include <linux/of_device.h>
33 #include <linux/of_i2c.h>
35 #define DRIVER_NAME "mxs-i2c"
37 #define MXS_I2C_CTRL0 (0x00)
38 #define MXS_I2C_CTRL0_SET (0x04)
40 #define MXS_I2C_CTRL0_SFTRST 0x80000000
41 #define MXS_I2C_CTRL0_SEND_NAK_ON_LAST 0x02000000
42 #define MXS_I2C_CTRL0_RETAIN_CLOCK 0x00200000
43 #define MXS_I2C_CTRL0_POST_SEND_STOP 0x00100000
44 #define MXS_I2C_CTRL0_PRE_SEND_START 0x00080000
45 #define MXS_I2C_CTRL0_MASTER_MODE 0x00020000
46 #define MXS_I2C_CTRL0_DIRECTION 0x00010000
47 #define MXS_I2C_CTRL0_XFER_COUNT(v) ((v) & 0x0000FFFF)
49 #define MXS_I2C_TIMING0 (0x10)
50 #define MXS_I2C_TIMING1 (0x20)
51 #define MXS_I2C_TIMING2 (0x30)
53 #define MXS_I2C_CTRL1 (0x40)
54 #define MXS_I2C_CTRL1_SET (0x44)
55 #define MXS_I2C_CTRL1_CLR (0x48)
57 #define MXS_I2C_CTRL1_BUS_FREE_IRQ 0x80
58 #define MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ 0x40
59 #define MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ 0x20
60 #define MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ 0x10
61 #define MXS_I2C_CTRL1_EARLY_TERM_IRQ 0x08
62 #define MXS_I2C_CTRL1_MASTER_LOSS_IRQ 0x04
63 #define MXS_I2C_CTRL1_SLAVE_STOP_IRQ 0x02
64 #define MXS_I2C_CTRL1_SLAVE_IRQ 0x01
66 #define MXS_I2C_IRQ_MASK (MXS_I2C_CTRL1_DATA_ENGINE_CMPLT_IRQ | \
67 MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ | \
68 MXS_I2C_CTRL1_EARLY_TERM_IRQ | \
69 MXS_I2C_CTRL1_MASTER_LOSS_IRQ | \
70 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | \
71 MXS_I2C_CTRL1_SLAVE_IRQ)
73 #define MXS_I2C_QUEUECTRL (0x60)
74 #define MXS_I2C_QUEUECTRL_SET (0x64)
75 #define MXS_I2C_QUEUECTRL_CLR (0x68)
77 #define MXS_I2C_QUEUECTRL_QUEUE_RUN 0x20
78 #define MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE 0x04
80 #define MXS_I2C_QUEUESTAT (0x70)
81 #define MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY 0x00002000
82 #define MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK 0x0000001F
84 #define MXS_I2C_QUEUECMD (0x80)
86 #define MXS_I2C_QUEUEDATA (0x90)
88 #define MXS_I2C_DATA (0xa0)
91 #define MXS_CMD_I2C_SELECT (MXS_I2C_CTRL0_RETAIN_CLOCK | \
92 MXS_I2C_CTRL0_PRE_SEND_START | \
93 MXS_I2C_CTRL0_MASTER_MODE | \
94 MXS_I2C_CTRL0_DIRECTION | \
95 MXS_I2C_CTRL0_XFER_COUNT(1))
97 #define MXS_CMD_I2C_WRITE (MXS_I2C_CTRL0_PRE_SEND_START | \
98 MXS_I2C_CTRL0_MASTER_MODE | \
99 MXS_I2C_CTRL0_DIRECTION)
101 #define MXS_CMD_I2C_READ (MXS_I2C_CTRL0_SEND_NAK_ON_LAST | \
102 MXS_I2C_CTRL0_MASTER_MODE)
104 struct mxs_i2c_speed_config {
111 * Timing values for the default 24MHz clock supplied into the i2c block.
113 * The bus can operate at 95kHz or at 400kHz with the following timing
114 * register configurations. The 100kHz mode isn't present because it's
115 * values are not stated in the i.MX233/i.MX28 datasheet. The 95kHz mode
116 * shall be close enough replacement. Therefore when the bus is configured
117 * for 100kHz operation, 95kHz timing settings are actually loaded.
119 * For details, see i.MX233 [25.4.2 - 25.4.4] and i.MX28 [27.5.2 - 27.5.4].
121 static const struct mxs_i2c_speed_config mxs_i2c_95kHz_config = {
122 .timing0 = 0x00780030,
123 .timing1 = 0x00800030,
124 .timing2 = 0x00300030,
127 static const struct mxs_i2c_speed_config mxs_i2c_400kHz_config = {
128 .timing0 = 0x000f0007,
129 .timing1 = 0x001f000f,
130 .timing2 = 0x00300030,
134 * struct mxs_i2c_dev - per device, private MXS-I2C data
136 * @dev: driver model device node
137 * @regs: IO registers pointer
138 * @cmd_complete: completion object for transaction wait
139 * @cmd_err: error code for last transaction
140 * @adapter: i2c subsystem adapter node
145 struct completion cmd_complete;
147 struct i2c_adapter adapter;
148 const struct mxs_i2c_speed_config *speed;
151 static void mxs_i2c_reset(struct mxs_i2c_dev *i2c)
153 stmp_reset_block(i2c->regs);
155 writel(i2c->speed->timing0, i2c->regs + MXS_I2C_TIMING0);
156 writel(i2c->speed->timing1, i2c->regs + MXS_I2C_TIMING1);
157 writel(i2c->speed->timing2, i2c->regs + MXS_I2C_TIMING2);
159 writel(MXS_I2C_IRQ_MASK << 8, i2c->regs + MXS_I2C_CTRL1_SET);
160 writel(MXS_I2C_QUEUECTRL_PIO_QUEUE_MODE,
161 i2c->regs + MXS_I2C_QUEUECTRL_SET);
164 static void mxs_i2c_pioq_setup_read(struct mxs_i2c_dev *i2c, u8 addr, int len,
169 writel(MXS_CMD_I2C_SELECT, i2c->regs + MXS_I2C_QUEUECMD);
171 data = (addr << 1) | I2C_SMBUS_READ;
172 writel(data, i2c->regs + MXS_I2C_DATA);
174 data = MXS_CMD_I2C_READ | MXS_I2C_CTRL0_XFER_COUNT(len) | flags;
175 writel(data, i2c->regs + MXS_I2C_QUEUECMD);
178 static void mxs_i2c_pioq_setup_write(struct mxs_i2c_dev *i2c,
179 u8 addr, u8 *buf, int len, int flags)
184 data = MXS_CMD_I2C_WRITE | MXS_I2C_CTRL0_XFER_COUNT(len + 1) | flags;
185 writel(data, i2c->regs + MXS_I2C_QUEUECMD);
188 * We have to copy the slave address (u8) and buffer (arbitrary number
189 * of u8) into the data register (u32). To achieve that, the u8 are put
190 * into the MSBs of 'data' which is then shifted for the next u8. When
191 * appropriate, 'data' is written to MXS_I2C_DATA. So, the first u32
195 * 10987654|32109876|54321098|76543210
196 * --------+--------+--------+--------
197 * buffer+2|buffer+1|buffer+0|slave_addr
200 data = ((addr << 1) | I2C_SMBUS_WRITE) << 24;
202 for (i = 0; i < len; i++) {
204 data |= buf[i] << 24;
206 writel(data, i2c->regs + MXS_I2C_DATA);
209 /* Write out the remaining bytes if any */
210 shifts_left = 24 - (i & 3) * 8;
212 writel(data >> shifts_left, i2c->regs + MXS_I2C_DATA);
216 * TODO: should be replaceable with a waitqueue and RD_QUEUE_IRQ (setting the
217 * rd_threshold to 1). Couldn't get this to work, though.
219 static int mxs_i2c_wait_for_data(struct mxs_i2c_dev *i2c)
221 unsigned long timeout = jiffies + msecs_to_jiffies(1000);
223 while (readl(i2c->regs + MXS_I2C_QUEUESTAT)
224 & MXS_I2C_QUEUESTAT_RD_QUEUE_EMPTY) {
225 if (time_after(jiffies, timeout))
233 static int mxs_i2c_finish_read(struct mxs_i2c_dev *i2c, u8 *buf, int len)
235 u32 uninitialized_var(data);
238 for (i = 0; i < len; i++) {
240 if (mxs_i2c_wait_for_data(i2c))
242 data = readl(i2c->regs + MXS_I2C_QUEUEDATA);
244 buf[i] = data & 0xff;
252 * Low level master read/write transaction.
254 static int mxs_i2c_xfer_msg(struct i2c_adapter *adap, struct i2c_msg *msg,
257 struct mxs_i2c_dev *i2c = i2c_get_adapdata(adap);
261 dev_dbg(i2c->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
262 msg->addr, msg->len, msg->flags, stop);
267 init_completion(&i2c->cmd_complete);
270 flags = stop ? MXS_I2C_CTRL0_POST_SEND_STOP : 0;
272 if (msg->flags & I2C_M_RD)
273 mxs_i2c_pioq_setup_read(i2c, msg->addr, msg->len, flags);
275 mxs_i2c_pioq_setup_write(i2c, msg->addr, msg->buf, msg->len,
278 writel(MXS_I2C_QUEUECTRL_QUEUE_RUN,
279 i2c->regs + MXS_I2C_QUEUECTRL_SET);
281 ret = wait_for_completion_timeout(&i2c->cmd_complete,
282 msecs_to_jiffies(1000));
286 if ((!i2c->cmd_err) && (msg->flags & I2C_M_RD)) {
287 ret = mxs_i2c_finish_read(i2c, msg->buf, msg->len);
292 if (i2c->cmd_err == -ENXIO)
295 writel(MXS_I2C_QUEUECTRL_QUEUE_RUN,
296 i2c->regs + MXS_I2C_QUEUECTRL_CLR);
298 dev_dbg(i2c->dev, "Done with err=%d\n", i2c->cmd_err);
303 dev_dbg(i2c->dev, "Timeout!\n");
308 static int mxs_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[],
314 for (i = 0; i < num; i++) {
315 err = mxs_i2c_xfer_msg(adap, &msgs[i], i == (num - 1));
323 static u32 mxs_i2c_func(struct i2c_adapter *adap)
325 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
328 static irqreturn_t mxs_i2c_isr(int this_irq, void *dev_id)
330 struct mxs_i2c_dev *i2c = dev_id;
331 u32 stat = readl(i2c->regs + MXS_I2C_CTRL1) & MXS_I2C_IRQ_MASK;
337 if (stat & MXS_I2C_CTRL1_NO_SLAVE_ACK_IRQ)
338 i2c->cmd_err = -ENXIO;
339 else if (stat & (MXS_I2C_CTRL1_EARLY_TERM_IRQ |
340 MXS_I2C_CTRL1_MASTER_LOSS_IRQ |
341 MXS_I2C_CTRL1_SLAVE_STOP_IRQ | MXS_I2C_CTRL1_SLAVE_IRQ))
342 /* MXS_I2C_CTRL1_OVERSIZE_XFER_TERM_IRQ is only for slaves */
345 is_last_cmd = (readl(i2c->regs + MXS_I2C_QUEUESTAT) &
346 MXS_I2C_QUEUESTAT_WRITE_QUEUE_CNT_MASK) == 0;
348 if (is_last_cmd || i2c->cmd_err)
349 complete(&i2c->cmd_complete);
351 writel(stat, i2c->regs + MXS_I2C_CTRL1_CLR);
356 static const struct i2c_algorithm mxs_i2c_algo = {
357 .master_xfer = mxs_i2c_xfer,
358 .functionality = mxs_i2c_func,
361 static int mxs_i2c_get_ofdata(struct mxs_i2c_dev *i2c)
364 struct device *dev = i2c->dev;
365 struct device_node *node = dev->of_node;
371 i2c->speed = &mxs_i2c_95kHz_config;
372 ret = of_property_read_u32(node, "clock-frequency", &speed);
374 dev_warn(dev, "No I2C speed selected, using 100kHz\n");
375 else if (speed == 400000)
376 i2c->speed = &mxs_i2c_400kHz_config;
377 else if (speed != 100000)
378 dev_warn(dev, "Unsupported I2C speed selected, using 100kHz\n");
383 static int __devinit mxs_i2c_probe(struct platform_device *pdev)
385 struct device *dev = &pdev->dev;
386 struct mxs_i2c_dev *i2c;
387 struct i2c_adapter *adap;
388 struct pinctrl *pinctrl;
389 struct resource *res;
390 resource_size_t res_size;
393 pinctrl = devm_pinctrl_get_select_default(dev);
395 return PTR_ERR(pinctrl);
397 i2c = devm_kzalloc(dev, sizeof(struct mxs_i2c_dev), GFP_KERNEL);
401 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
405 res_size = resource_size(res);
406 if (!devm_request_mem_region(dev, res->start, res_size, res->name))
409 i2c->regs = devm_ioremap_nocache(dev, res->start, res_size);
413 irq = platform_get_irq(pdev, 0);
417 err = devm_request_irq(dev, irq, mxs_i2c_isr, 0, dev_name(dev), i2c);
423 err = mxs_i2c_get_ofdata(i2c);
427 platform_set_drvdata(pdev, i2c);
429 /* Do reset to enforce correct startup after pinmuxing */
432 adap = &i2c->adapter;
433 strlcpy(adap->name, "MXS I2C adapter", sizeof(adap->name));
434 adap->owner = THIS_MODULE;
435 adap->algo = &mxs_i2c_algo;
436 adap->dev.parent = dev;
438 adap->dev.of_node = pdev->dev.of_node;
439 i2c_set_adapdata(adap, i2c);
440 err = i2c_add_numbered_adapter(adap);
442 dev_err(dev, "Failed to add adapter (%d)\n", err);
443 writel(MXS_I2C_CTRL0_SFTRST,
444 i2c->regs + MXS_I2C_CTRL0_SET);
448 of_i2c_register_devices(adap);
453 static int __devexit mxs_i2c_remove(struct platform_device *pdev)
455 struct mxs_i2c_dev *i2c = platform_get_drvdata(pdev);
458 ret = i2c_del_adapter(&i2c->adapter);
462 writel(MXS_I2C_CTRL0_SFTRST, i2c->regs + MXS_I2C_CTRL0_SET);
464 platform_set_drvdata(pdev, NULL);
469 static const struct of_device_id mxs_i2c_dt_ids[] = {
470 { .compatible = "fsl,imx28-i2c", },
473 MODULE_DEVICE_TABLE(of, mxs_i2c_dt_ids);
475 static struct platform_driver mxs_i2c_driver = {
478 .owner = THIS_MODULE,
479 .of_match_table = mxs_i2c_dt_ids,
481 .remove = __devexit_p(mxs_i2c_remove),
484 static int __init mxs_i2c_init(void)
486 return platform_driver_probe(&mxs_i2c_driver, mxs_i2c_probe);
488 subsys_initcall(mxs_i2c_init);
490 static void __exit mxs_i2c_exit(void)
492 platform_driver_unregister(&mxs_i2c_driver);
494 module_exit(mxs_i2c_exit);
496 MODULE_AUTHOR("Wolfram Sang <w.sang@pengutronix.de>");
497 MODULE_DESCRIPTION("MXS I2C Bus Driver");
498 MODULE_LICENSE("GPL");
499 MODULE_ALIAS("platform:" DRIVER_NAME);