drivers/i2c/busses/i2c-ocores.c

   1 /*
   2  * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
   3  * (http://www.opencores.org/projects.cgi/web/i2c/overview).
   4  *
   5  * Peter Korsgaard <jacmet@sunsite.dk>
   6  *
   7  * Support for the GRLIB port of the controller by
   8  * Andreas Larsson <andreas@gaisler.com>
   9  *
  10  * This file is licensed under the terms of the GNU General Public License
  11  * version 2.  This program is licensed "as is" without any warranty of any
  12  * kind, whether express or implied.
  13  */
  14
  15 /*
  16  * This driver can be used from the device tree, see
  17  *     Documentation/devicetree/bindings/i2c/ocore-i2c.txt
  18  */
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/i2c.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/wait.h>
  27 #include <linux/i2c-ocores.h>
  28 #include <linux/slab.h>
  29 #include <linux/io.h>
  30 #include <linux/of_i2c.h>
  31 #include <linux/log2.h>
  32
  33 struct ocores_i2c {
  34         void __iomem *base;
  35         u32 reg_shift;
  36         u32 reg_io_width;
  37         wait_queue_head_t wait;
  38         struct i2c_adapter adap;
  39         struct i2c_msg *msg;
  40         int pos;
  41         int nmsgs;
  42         int state; /* see STATE_ */
  43         int clock_khz;
  44         void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value);
  45         u8 (*getreg)(struct ocores_i2c *i2c, int reg);
  46 };
  47
  48 /* registers */
  49 #define OCI2C_PRELOW            0
  50 #define OCI2C_PREHIGH           1
  51 #define OCI2C_CONTROL           2
  52 #define OCI2C_DATA              3
  53 #define OCI2C_CMD               4 /* write only */
  54 #define OCI2C_STATUS            4 /* read only, same address as OCI2C_CMD */
  55
  56 #define OCI2C_CTRL_IEN          0x40
  57 #define OCI2C_CTRL_EN           0x80
  58
  59 #define OCI2C_CMD_START         0x91
  60 #define OCI2C_CMD_STOP          0x41
  61 #define OCI2C_CMD_READ          0x21
  62 #define OCI2C_CMD_WRITE         0x11
  63 #define OCI2C_CMD_READ_ACK      0x21
  64 #define OCI2C_CMD_READ_NACK     0x29
  65 #define OCI2C_CMD_IACK          0x01
  66
  67 #define OCI2C_STAT_IF           0x01
  68 #define OCI2C_STAT_TIP          0x02
  69 #define OCI2C_STAT_ARBLOST      0x20
  70 #define OCI2C_STAT_BUSY         0x40
  71 #define OCI2C_STAT_NACK         0x80
  72
  73 #define STATE_DONE              0
  74 #define STATE_START             1
  75 #define STATE_WRITE             2
  76 #define STATE_READ              3
  77 #define STATE_ERROR             4
  78
  79 #define TYPE_OCORES             0
  80 #define TYPE_GRLIB              1
  81
  82 static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value)
  83 {
  84         iowrite8(value, i2c->base + (reg << i2c->reg_shift));
  85 }
  86
  87 static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value)
  88 {
  89         iowrite16(value, i2c->base + (reg << i2c->reg_shift));
  90 }
  91
  92 static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value)
  93 {
  94         iowrite32(value, i2c->base + (reg << i2c->reg_shift));
  95 }
  96
  97 static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg)
  98 {
  99         return ioread8(i2c->base + (reg << i2c->reg_shift));
 100 }
 101
 102 static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg)
 103 {
 104         return ioread16(i2c->base + (reg << i2c->reg_shift));
 105 }
 106
 107 static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg)
 108 {
 109         return ioread32(i2c->base + (reg << i2c->reg_shift));
 110 }
 111
 112 /* Read and write functions for the GRLIB port of the controller. Registers are
 113  * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
 114  * register. The subsequent registers has their offset decreased accordingly. */
 115 static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
 116 {
 117         u32 rd;
 118         int rreg = reg;
 119         if (reg != OCI2C_PRELOW)
 120                 rreg--;
 121         rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
 122         if (reg == OCI2C_PREHIGH)
 123                 return (u8)(rd >> 8);
 124         else
 125                 return (u8)rd;
 126 }
 127
 128 static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
 129 {
 130         u32 curr, wr;
 131         int rreg = reg;
 132         if (reg != OCI2C_PRELOW)
 133                 rreg--;
 134         if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
 135                 curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
 136                 if (reg == OCI2C_PRELOW)
 137                         wr = (curr & 0xff00) | value;
 138                 else
 139                         wr = (((u32)value) << 8) | (curr & 0xff);
 140         } else {
 141                 wr = value;
 142         }
 143         iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
 144 }
 145
 146 static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
 147 {
 148         i2c->setreg(i2c, reg, value);
 149 }
 150
 151 static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
 152 {
 153         return i2c->getreg(i2c, reg);
 154 }
 155
 156 static void ocores_process(struct ocores_i2c *i2c)
 157 {
 158         struct i2c_msg *msg = i2c->msg;
 159         u8 stat = oc_getreg(i2c, OCI2C_STATUS);
 160
 161         if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
 162                 /* stop has been sent */
 163                 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
 164                 wake_up(&i2c->wait);
 165                 return;
 166         }
 167
 168         /* error? */
 169         if (stat & OCI2C_STAT_ARBLOST) {
 170                 i2c->state = STATE_ERROR;
 171                 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
 172                 return;
 173         }
 174
 175         if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
 176                 i2c->state =
 177                         (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
 178
 179                 if (stat & OCI2C_STAT_NACK) {
 180                         i2c->state = STATE_ERROR;
 181                         oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
 182                         return;
 183                 }
 184         } else
 185                 msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
 186
 187         /* end of msg? */
 188         if (i2c->pos == msg->len) {
 189                 i2c->nmsgs--;
 190                 i2c->msg++;
 191                 i2c->pos = 0;
 192                 msg = i2c->msg;
 193
 194                 if (i2c->nmsgs) {       /* end? */
 195                         /* send start? */
 196                         if (!(msg->flags & I2C_M_NOSTART)) {
 197                                 u8 addr = (msg->addr << 1);
 198
 199                                 if (msg->flags & I2C_M_RD)
 200                                         addr |= 1;
 201
 202                                 i2c->state = STATE_START;
 203
 204                                 oc_setreg(i2c, OCI2C_DATA, addr);
 205                                 oc_setreg(i2c, OCI2C_CMD,  OCI2C_CMD_START);
 206                                 return;
 207                         } else
 208                                 i2c->state = (msg->flags & I2C_M_RD)
 209                                         ? STATE_READ : STATE_WRITE;
 210                 } else {
 211                         i2c->state = STATE_DONE;
 212                         oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
 213                         return;
 214                 }
 215         }
 216
 217         if (i2c->state == STATE_READ) {
 218                 oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
 219                           OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
 220         } else {
 221                 oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
 222                 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
 223         }
 224 }
 225
 226 static irqreturn_t ocores_isr(int irq, void *dev_id)
 227 {
 228         struct ocores_i2c *i2c = dev_id;
 229
 230         ocores_process(i2c);
 231
 232         return IRQ_HANDLED;
 233 }
 234
 235 static int ocores_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 236 {
 237         struct ocores_i2c *i2c = i2c_get_adapdata(adap);
 238
 239         i2c->msg = msgs;
 240         i2c->pos = 0;
 241         i2c->nmsgs = num;
 242         i2c->state = STATE_START;
 243
 244         oc_setreg(i2c, OCI2C_DATA,
 245                         (i2c->msg->addr << 1) |
 246                         ((i2c->msg->flags & I2C_M_RD) ? 1:0));
 247
 248         oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
 249
 250         if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
 251                                (i2c->state == STATE_DONE), HZ))
 252                 return (i2c->state == STATE_DONE) ? num : -EIO;
 253         else
 254                 return -ETIMEDOUT;
 255 }
 256
 257 static void ocores_init(struct ocores_i2c *i2c)
 258 {
 259         int prescale;
 260         u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
 261
 262         /* make sure the device is disabled */
 263         oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
 264
 265         prescale = (i2c->clock_khz / (5*100)) - 1;
 266         oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
 267         oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
 268
 269         /* Init the device */
 270         oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
 271         oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN | OCI2C_CTRL_EN);
 272 }
 273
 274
 275 static u32 ocores_func(struct i2c_adapter *adap)
 276 {
 277         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 278 }
 279
 280 static const struct i2c_algorithm ocores_algorithm = {
 281         .master_xfer    = ocores_xfer,
 282         .functionality  = ocores_func,
 283 };
 284
 285 static struct i2c_adapter ocores_adapter = {
 286         .owner          = THIS_MODULE,
 287         .name           = "i2c-ocores",
 288         .class          = I2C_CLASS_HWMON | I2C_CLASS_SPD,
 289         .algo           = &ocores_algorithm,
 290 };
 291
 292 static struct of_device_id ocores_i2c_match[] = {
 293         {
 294                 .compatible = "opencores,i2c-ocores",
 295                 .data = (void *)TYPE_OCORES,
 296         },
 297         {
 298                 .compatible = "aeroflexgaisler,i2cmst",
 299                 .data = (void *)TYPE_GRLIB,
 300         },
 301         {},
 302 };
 303 MODULE_DEVICE_TABLE(of, ocores_i2c_match);
 304
 305 #ifdef CONFIG_OF
 306 static int ocores_i2c_of_probe(struct platform_device *pdev,
 307                                 struct ocores_i2c *i2c)
 308 {
 309         struct device_node *np = pdev->dev.of_node;
 310         const struct of_device_id *match;
 311         u32 val;
 312
 313         if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) {
 314                 /* no 'reg-shift', check for deprecated 'regstep' */
 315                 if (!of_property_read_u32(np, "regstep", &val)) {
 316                         if (!is_power_of_2(val)) {
 317                                 dev_err(&pdev->dev, "invalid regstep %d\n",
 318                                         val);
 319                                 return -EINVAL;
 320                         }
 321                         i2c->reg_shift = ilog2(val);
 322                         dev_warn(&pdev->dev,
 323                                 "regstep property deprecated, use reg-shift\n");
 324                 }
 325         }
 326
 327         if (of_property_read_u32(np, "clock-frequency", &val)) {
 328                 dev_err(&pdev->dev,
 329                         "Missing required parameter 'clock-frequency'\n");
 330                 return -ENODEV;
 331         }
 332         i2c->clock_khz = val / 1000;
 333
 334         of_property_read_u32(pdev->dev.of_node, "reg-io-width",
 335                                 &i2c->reg_io_width);
 336
 337         match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
 338         if (match && (int)match->data == TYPE_GRLIB) {
 339                 dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n");
 340                 i2c->setreg = oc_setreg_grlib;
 341                 i2c->getreg = oc_getreg_grlib;
 342         }
 343
 344         return 0;
 345 }
 346 #else
 347 #define ocores_i2c_of_probe(pdev,i2c) -ENODEV
 348 #endif
 349
 350 static int __devinit ocores_i2c_probe(struct platform_device *pdev)
 351 {
 352         struct ocores_i2c *i2c;
 353         struct ocores_i2c_platform_data *pdata;
 354         struct resource *res;
 355         int irq;
 356         int ret;
 357         int i;
 358
 359         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 360         if (!res)
 361                 return -ENODEV;
 362
 363         irq = platform_get_irq(pdev, 0);
 364         if (irq < 0)
 365                 return irq;
 366
 367         i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
 368         if (!i2c)
 369                 return -ENOMEM;
 370
 371         i2c->base = devm_request_and_ioremap(&pdev->dev, res);
 372         if (!i2c->base)
 373                 return -EADDRNOTAVAIL;
 374
 375         pdata = pdev->dev.platform_data;
 376         if (pdata) {
 377                 i2c->reg_shift = pdata->reg_shift;
 378                 i2c->reg_io_width = pdata->reg_io_width;
 379                 i2c->clock_khz = pdata->clock_khz;
 380         } else {
 381                 ret = ocores_i2c_of_probe(pdev, i2c);
 382                 if (ret)
 383                         return ret;
 384         }
 385
 386         if (i2c->reg_io_width == 0)
 387                 i2c->reg_io_width = 1; /* Set to default value */
 388
 389         if (!i2c->setreg || !i2c->getreg) {
 390                 switch (i2c->reg_io_width) {
 391                 case 1:
 392                         i2c->setreg = oc_setreg_8;
 393                         i2c->getreg = oc_getreg_8;
 394                         break;
 395
 396                 case 2:
 397                         i2c->setreg = oc_setreg_16;
 398                         i2c->getreg = oc_getreg_16;
 399                         break;
 400
 401                 case 4:
 402                         i2c->setreg = oc_setreg_32;
 403                         i2c->getreg = oc_getreg_32;
 404                         break;
 405
 406                 default:
 407                         dev_err(&pdev->dev, "Unsupported I/O width (%d)\n",
 408                                 i2c->reg_io_width);
 409                         return -EINVAL;
 410                 }
 411         }
 412
 413         ocores_init(i2c);
 414
 415         init_waitqueue_head(&i2c->wait);
 416         ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0,
 417                                pdev->name, i2c);
 418         if (ret) {
 419                 dev_err(&pdev->dev, "Cannot claim IRQ\n");
 420                 return ret;
 421         }
 422
 423         /* hook up driver to tree */
 424         platform_set_drvdata(pdev, i2c);
 425         i2c->adap = ocores_adapter;
 426         i2c_set_adapdata(&i2c->adap, i2c);
 427         i2c->adap.dev.parent = &pdev->dev;
 428         i2c->adap.dev.of_node = pdev->dev.of_node;
 429
 430         /* add i2c adapter to i2c tree */
 431         ret = i2c_add_adapter(&i2c->adap);
 432         if (ret) {
 433                 dev_err(&pdev->dev, "Failed to add adapter\n");
 434                 return ret;
 435         }
 436
 437         /* add in known devices to the bus */
 438         if (pdata) {
 439                 for (i = 0; i < pdata->num_devices; i++)
 440                         i2c_new_device(&i2c->adap, pdata->devices + i);
 441         } else {
 442                 of_i2c_register_devices(&i2c->adap);
 443         }
 444
 445         return 0;
 446 }
 447
 448 static int __devexit ocores_i2c_remove(struct platform_device *pdev)
 449 {
 450         struct ocores_i2c *i2c = platform_get_drvdata(pdev);
 451
 452         /* disable i2c logic */
 453         oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL)
 454                   & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
 455
 456         /* remove adapter & data */
 457         i2c_del_adapter(&i2c->adap);
 458         platform_set_drvdata(pdev, NULL);
 459
 460         return 0;
 461 }
 462
 463 #ifdef CONFIG_PM
 464 static int ocores_i2c_suspend(struct device *dev)
 465 {
 466         struct ocores_i2c *i2c = dev_get_drvdata(dev);
 467         u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
 468
 469         /* make sure the device is disabled */
 470         oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
 471
 472         return 0;
 473 }
 474
 475 static int ocores_i2c_resume(struct device *dev)
 476 {
 477         struct ocores_i2c *i2c = dev_get_drvdata(dev);
 478
 479         ocores_init(i2c);
 480
 481         return 0;
 482 }
 483
 484 static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume);
 485 #define OCORES_I2C_PM   (&ocores_i2c_pm)
 486 #else
 487 #define OCORES_I2C_PM   NULL
 488 #endif
 489
 490 static struct platform_driver ocores_i2c_driver = {
 491         .probe   = ocores_i2c_probe,
 492         .remove  = __devexit_p(ocores_i2c_remove),
 493         .driver  = {
 494                 .owner = THIS_MODULE,
 495                 .name = "ocores-i2c",
 496                 .of_match_table = ocores_i2c_match,
 497                 .pm = OCORES_I2C_PM,
 498         },
 499 };
 500
 501 module_platform_driver(ocores_i2c_driver);
 502
 503 MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
 504 MODULE_DESCRIPTION("OpenCores I2C bus driver");
 505 MODULE_LICENSE("GPL");
 506 MODULE_ALIAS("platform:ocores-i2c");