drivers/i2c/busses/i2c-ocores.c

   1 /*
   2  * i2c-ocores.c: I2C bus driver for OpenCores I2C controller
   3  * (http://www.opencores.org/projects.cgi/web/i2c/overview).
   4  *
   5  * Peter Korsgaard <jacmet@sunsite.dk>
   6  *
   7  * Support for the GRLIB port of the controller by
   8  * Andreas Larsson <andreas@gaisler.com>
   9  *
  10  * This file is licensed under the terms of the GNU General Public License
  11  * version 2.  This program is licensed "as is" without any warranty of any
  12  * kind, whether express or implied.
  13  */
  14
  15 /*
  16  * This driver can be used from the device tree, see
  17  *     Documentation/devicetree/bindings/i2c/ocore-i2c.txt
  18  */
  19 #include <linux/kernel.h>
  20 #include <linux/module.h>
  21 #include <linux/init.h>
  22 #include <linux/errno.h>
  23 #include <linux/platform_device.h>
  24 #include <linux/i2c.h>
  25 #include <linux/interrupt.h>
  26 #include <linux/wait.h>
  27 #include <linux/i2c-ocores.h>
  28 #include <linux/slab.h>
  29 #include <linux/io.h>
  30 #include <linux/of_i2c.h>
  31 #include <linux/log2.h>
  32
  33 struct ocores_i2c {
  34         void __iomem *base;
  35         u32 reg_shift;
  36         u32 reg_io_width;
  37         wait_queue_head_t wait;
  38         struct i2c_adapter adap;
  39         struct i2c_msg *msg;
  40         int pos;
  41         int nmsgs;
  42         int state; /* see STATE_ */
  43         int clock_khz;
  44         void (*setreg)(struct ocores_i2c *i2c, int reg, u8 value);
  45         u8 (*getreg)(struct ocores_i2c *i2c, int reg);
  46 };
  47
  48 /* registers */
  49 #define OCI2C_PRELOW            0
  50 #define OCI2C_PREHIGH           1
  51 #define OCI2C_CONTROL           2
  52 #define OCI2C_DATA              3
  53 #define OCI2C_CMD               4 /* write only */
  54 #define OCI2C_STATUS            4 /* read only, same address as OCI2C_CMD */
  55
  56 #define OCI2C_CTRL_IEN          0x40
  57 #define OCI2C_CTRL_EN           0x80
  58
  59 #define OCI2C_CMD_START         0x91
  60 #define OCI2C_CMD_STOP          0x41
  61 #define OCI2C_CMD_READ          0x21
  62 #define OCI2C_CMD_WRITE         0x11
  63 #define OCI2C_CMD_READ_ACK      0x21
  64 #define OCI2C_CMD_READ_NACK     0x29
  65 #define OCI2C_CMD_IACK          0x01
  66
  67 #define OCI2C_STAT_IF           0x01
  68 #define OCI2C_STAT_TIP          0x02
  69 #define OCI2C_STAT_ARBLOST      0x20
  70 #define OCI2C_STAT_BUSY         0x40
  71 #define OCI2C_STAT_NACK         0x80
  72
  73 #define STATE_DONE              0
  74 #define STATE_START             1
  75 #define STATE_WRITE             2
  76 #define STATE_READ              3
  77 #define STATE_ERROR             4
  78
  79 #define TYPE_OCORES             0
  80 #define TYPE_GRLIB              1
  81
  82 static void oc_setreg_8(struct ocores_i2c *i2c, int reg, u8 value)
  83 {
  84         iowrite8(value, i2c->base + (reg << i2c->reg_shift));
  85 }
  86
  87 static void oc_setreg_16(struct ocores_i2c *i2c, int reg, u8 value)
  88 {
  89         iowrite16(value, i2c->base + (reg << i2c->reg_shift));
  90 }
  91
  92 static void oc_setreg_32(struct ocores_i2c *i2c, int reg, u8 value)
  93 {
  94         iowrite32(value, i2c->base + (reg << i2c->reg_shift));
  95 }
  96
  97 static inline u8 oc_getreg_8(struct ocores_i2c *i2c, int reg)
  98 {
  99         return ioread8(i2c->base + (reg << i2c->reg_shift));
 100 }
 101
 102 static inline u8 oc_getreg_16(struct ocores_i2c *i2c, int reg)
 103 {
 104         return ioread16(i2c->base + (reg << i2c->reg_shift));
 105 }
 106
 107 static inline u8 oc_getreg_32(struct ocores_i2c *i2c, int reg)
 108 {
 109         return ioread32(i2c->base + (reg << i2c->reg_shift));
 110 }
 111
 112 static inline void oc_setreg(struct ocores_i2c *i2c, int reg, u8 value)
 113 {
 114         i2c->setreg(i2c, reg, value);
 115 }
 116
 117 static inline u8 oc_getreg(struct ocores_i2c *i2c, int reg)
 118 {
 119         return i2c->getreg(i2c, reg);
 120 }
 121
 122 static void ocores_process(struct ocores_i2c *i2c)
 123 {
 124         struct i2c_msg *msg = i2c->msg;
 125         u8 stat = oc_getreg(i2c, OCI2C_STATUS);
 126
 127         if ((i2c->state == STATE_DONE) || (i2c->state == STATE_ERROR)) {
 128                 /* stop has been sent */
 129                 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
 130                 wake_up(&i2c->wait);
 131                 return;
 132         }
 133
 134         /* error? */
 135         if (stat & OCI2C_STAT_ARBLOST) {
 136                 i2c->state = STATE_ERROR;
 137                 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
 138                 return;
 139         }
 140
 141         if ((i2c->state == STATE_START) || (i2c->state == STATE_WRITE)) {
 142                 i2c->state =
 143                         (msg->flags & I2C_M_RD) ? STATE_READ : STATE_WRITE;
 144
 145                 if (stat & OCI2C_STAT_NACK) {
 146                         i2c->state = STATE_ERROR;
 147                         oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
 148                         return;
 149                 }
 150         } else
 151                 msg->buf[i2c->pos++] = oc_getreg(i2c, OCI2C_DATA);
 152
 153         /* end of msg? */
 154         if (i2c->pos == msg->len) {
 155                 i2c->nmsgs--;
 156                 i2c->msg++;
 157                 i2c->pos = 0;
 158                 msg = i2c->msg;
 159
 160                 if (i2c->nmsgs) {       /* end? */
 161                         /* send start? */
 162                         if (!(msg->flags & I2C_M_NOSTART)) {
 163                                 u8 addr = (msg->addr << 1);
 164
 165                                 if (msg->flags & I2C_M_RD)
 166                                         addr |= 1;
 167
 168                                 i2c->state = STATE_START;
 169
 170                                 oc_setreg(i2c, OCI2C_DATA, addr);
 171                                 oc_setreg(i2c, OCI2C_CMD,  OCI2C_CMD_START);
 172                                 return;
 173                         } else
 174                                 i2c->state = (msg->flags & I2C_M_RD)
 175                                         ? STATE_READ : STATE_WRITE;
 176                 } else {
 177                         i2c->state = STATE_DONE;
 178                         oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_STOP);
 179                         return;
 180                 }
 181         }
 182
 183         if (i2c->state == STATE_READ) {
 184                 oc_setreg(i2c, OCI2C_CMD, i2c->pos == (msg->len-1) ?
 185                           OCI2C_CMD_READ_NACK : OCI2C_CMD_READ_ACK);
 186         } else {
 187                 oc_setreg(i2c, OCI2C_DATA, msg->buf[i2c->pos++]);
 188                 oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_WRITE);
 189         }
 190 }
 191
 192 static irqreturn_t ocores_isr(int irq, void *dev_id)
 193 {
 194         struct ocores_i2c *i2c = dev_id;
 195
 196         ocores_process(i2c);
 197
 198         return IRQ_HANDLED;
 199 }
 200
 201 static int ocores_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num)
 202 {
 203         struct ocores_i2c *i2c = i2c_get_adapdata(adap);
 204
 205         i2c->msg = msgs;
 206         i2c->pos = 0;
 207         i2c->nmsgs = num;
 208         i2c->state = STATE_START;
 209
 210         oc_setreg(i2c, OCI2C_DATA,
 211                         (i2c->msg->addr << 1) |
 212                         ((i2c->msg->flags & I2C_M_RD) ? 1:0));
 213
 214         oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_START);
 215
 216         if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) ||
 217                                (i2c->state == STATE_DONE), HZ))
 218                 return (i2c->state == STATE_DONE) ? num : -EIO;
 219         else
 220                 return -ETIMEDOUT;
 221 }
 222
 223 static void ocores_init(struct ocores_i2c *i2c)
 224 {
 225         int prescale;
 226         u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
 227
 228         /* make sure the device is disabled */
 229         oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
 230
 231         prescale = (i2c->clock_khz / (5*100)) - 1;
 232         oc_setreg(i2c, OCI2C_PRELOW, prescale & 0xff);
 233         oc_setreg(i2c, OCI2C_PREHIGH, prescale >> 8);
 234
 235         /* Init the device */
 236         oc_setreg(i2c, OCI2C_CMD, OCI2C_CMD_IACK);
 237         oc_setreg(i2c, OCI2C_CONTROL, ctrl | OCI2C_CTRL_IEN | OCI2C_CTRL_EN);
 238 }
 239
 240
 241 static u32 ocores_func(struct i2c_adapter *adap)
 242 {
 243         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
 244 }
 245
 246 static const struct i2c_algorithm ocores_algorithm = {
 247         .master_xfer    = ocores_xfer,
 248         .functionality  = ocores_func,
 249 };
 250
 251 static struct i2c_adapter ocores_adapter = {
 252         .owner          = THIS_MODULE,
 253         .name           = "i2c-ocores",
 254         .class          = I2C_CLASS_HWMON | I2C_CLASS_SPD,
 255         .algo           = &ocores_algorithm,
 256 };
 257
 258 static struct of_device_id ocores_i2c_match[] = {
 259         {
 260                 .compatible = "opencores,i2c-ocores",
 261                 .data = (void *)TYPE_OCORES,
 262         },
 263         {
 264                 .compatible = "aeroflexgaisler,i2cmst",
 265                 .data = (void *)TYPE_GRLIB,
 266         },
 267         {},
 268 };
 269 MODULE_DEVICE_TABLE(of, ocores_i2c_match);
 270
 271 #ifdef CONFIG_OF
 272 /* Read and write functions for the GRLIB port of the controller. Registers are
 273  * 32-bit big endian and the PRELOW and PREHIGH registers are merged into one
 274  * register. The subsequent registers has their offset decreased accordingly. */
 275 static u8 oc_getreg_grlib(struct ocores_i2c *i2c, int reg)
 276 {
 277         u32 rd;
 278         int rreg = reg;
 279         if (reg != OCI2C_PRELOW)
 280                 rreg--;
 281         rd = ioread32be(i2c->base + (rreg << i2c->reg_shift));
 282         if (reg == OCI2C_PREHIGH)
 283                 return (u8)(rd >> 8);
 284         else
 285                 return (u8)rd;
 286 }
 287
 288 static void oc_setreg_grlib(struct ocores_i2c *i2c, int reg, u8 value)
 289 {
 290         u32 curr, wr;
 291         int rreg = reg;
 292         if (reg != OCI2C_PRELOW)
 293                 rreg--;
 294         if (reg == OCI2C_PRELOW || reg == OCI2C_PREHIGH) {
 295                 curr = ioread32be(i2c->base + (rreg << i2c->reg_shift));
 296                 if (reg == OCI2C_PRELOW)
 297                         wr = (curr & 0xff00) | value;
 298                 else
 299                         wr = (((u32)value) << 8) | (curr & 0xff);
 300         } else {
 301                 wr = value;
 302         }
 303         iowrite32be(wr, i2c->base + (rreg << i2c->reg_shift));
 304 }
 305
 306 static int ocores_i2c_of_probe(struct platform_device *pdev,
 307                                 struct ocores_i2c *i2c)
 308 {
 309         struct device_node *np = pdev->dev.of_node;
 310         const struct of_device_id *match;
 311         u32 val;
 312
 313         if (of_property_read_u32(np, "reg-shift", &i2c->reg_shift)) {
 314                 /* no 'reg-shift', check for deprecated 'regstep' */
 315                 if (!of_property_read_u32(np, "regstep", &val)) {
 316                         if (!is_power_of_2(val)) {
 317                                 dev_err(&pdev->dev, "invalid regstep %d\n",
 318                                         val);
 319                                 return -EINVAL;
 320                         }
 321                         i2c->reg_shift = ilog2(val);
 322                         dev_warn(&pdev->dev,
 323                                 "regstep property deprecated, use reg-shift\n");
 324                 }
 325         }
 326
 327         if (of_property_read_u32(np, "clock-frequency", &val)) {
 328                 dev_err(&pdev->dev,
 329                         "Missing required parameter 'clock-frequency'\n");
 330                 return -ENODEV;
 331         }
 332         i2c->clock_khz = val / 1000;
 333
 334         of_property_read_u32(pdev->dev.of_node, "reg-io-width",
 335                                 &i2c->reg_io_width);
 336
 337         match = of_match_node(ocores_i2c_match, pdev->dev.of_node);
 338         if (match && (int)match->data == TYPE_GRLIB) {
 339                 dev_dbg(&pdev->dev, "GRLIB variant of i2c-ocores\n");
 340                 i2c->setreg = oc_setreg_grlib;
 341                 i2c->getreg = oc_getreg_grlib;
 342         }
 343
 344         return 0;
 345 }
 346 #else
 347 #define ocores_i2c_of_probe(pdev,i2c) -ENODEV
 348 #endif
 349
 350 static int __devinit ocores_i2c_probe(struct platform_device *pdev)
 351 {
 352         struct ocores_i2c *i2c;
 353         struct ocores_i2c_platform_data *pdata;
 354         struct resource *res;
 355         int irq;
 356         int ret;
 357         int i;
 358
 359         res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 360         if (!res)
 361                 return -ENODEV;
 362
 363         irq = platform_get_irq(pdev, 0);
 364         if (irq < 0)
 365                 return irq;
 366
 367         i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL);
 368         if (!i2c)
 369                 return -ENOMEM;
 370
 371         i2c->base = devm_request_and_ioremap(&pdev->dev, res);
 372         if (!i2c->base)
 373                 return -EADDRNOTAVAIL;
 374
 375         pdata = pdev->dev.platform_data;
 376         if (pdata) {
 377                 i2c->reg_shift = pdata->reg_shift;
 378                 i2c->reg_io_width = pdata->reg_io_width;
 379                 i2c->clock_khz = pdata->clock_khz;
 380         } else {
 381                 ret = ocores_i2c_of_probe(pdev, i2c);
 382                 if (ret)
 383                         return ret;
 384         }
 385
 386         if (i2c->reg_io_width == 0)
 387                 i2c->reg_io_width = 1; /* Set to default value */
 388
 389         if (!i2c->setreg || !i2c->getreg) {
 390                 switch (i2c->reg_io_width) {
 391                 case 1:
 392                         i2c->setreg = oc_setreg_8;
 393                         i2c->getreg = oc_getreg_8;
 394                         break;
 395
 396                 case 2:
 397                         i2c->setreg = oc_setreg_16;
 398                         i2c->getreg = oc_getreg_16;
 399                         break;
 400
 401                 case 4:
 402                         i2c->setreg = oc_setreg_32;
 403                         i2c->getreg = oc_getreg_32;
 404                         break;
 405
 406                 default:
 407                         dev_err(&pdev->dev, "Unsupported I/O width (%d)\n",
 408                                 i2c->reg_io_width);
 409                         return -EINVAL;
 410                 }
 411         }
 412
 413         ocores_init(i2c);
 414
 415         init_waitqueue_head(&i2c->wait);
 416         ret = devm_request_irq(&pdev->dev, irq, ocores_isr, 0,
 417                                pdev->name, i2c);
 418         if (ret) {
 419                 dev_err(&pdev->dev, "Cannot claim IRQ\n");
 420                 return ret;
 421         }
 422
 423         /* hook up driver to tree */
 424         platform_set_drvdata(pdev, i2c);
 425         i2c->adap = ocores_adapter;
 426         i2c_set_adapdata(&i2c->adap, i2c);
 427         i2c->adap.dev.parent = &pdev->dev;
 428         i2c->adap.dev.of_node = pdev->dev.of_node;
 429
 430         /* add i2c adapter to i2c tree */
 431         ret = i2c_add_adapter(&i2c->adap);
 432         if (ret) {
 433                 dev_err(&pdev->dev, "Failed to add adapter\n");
 434                 return ret;
 435         }
 436
 437         /* add in known devices to the bus */
 438         if (pdata) {
 439                 for (i = 0; i < pdata->num_devices; i++)
 440                         i2c_new_device(&i2c->adap, pdata->devices + i);
 441         } else {
 442                 of_i2c_register_devices(&i2c->adap);
 443         }
 444
 445         return 0;
 446 }
 447
 448 static int __devexit ocores_i2c_remove(struct platform_device *pdev)
 449 {
 450         struct ocores_i2c *i2c = platform_get_drvdata(pdev);
 451
 452         /* disable i2c logic */
 453         oc_setreg(i2c, OCI2C_CONTROL, oc_getreg(i2c, OCI2C_CONTROL)
 454                   & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
 455
 456         /* remove adapter & data */
 457         i2c_del_adapter(&i2c->adap);
 458         platform_set_drvdata(pdev, NULL);
 459
 460         return 0;
 461 }
 462
 463 #ifdef CONFIG_PM
 464 static int ocores_i2c_suspend(struct device *dev)
 465 {
 466         struct ocores_i2c *i2c = dev_get_drvdata(dev);
 467         u8 ctrl = oc_getreg(i2c, OCI2C_CONTROL);
 468
 469         /* make sure the device is disabled */
 470         oc_setreg(i2c, OCI2C_CONTROL, ctrl & ~(OCI2C_CTRL_EN|OCI2C_CTRL_IEN));
 471
 472         return 0;
 473 }
 474
 475 static int ocores_i2c_resume(struct device *dev)
 476 {
 477         struct ocores_i2c *i2c = dev_get_drvdata(dev);
 478
 479         ocores_init(i2c);
 480
 481         return 0;
 482 }
 483
 484 static SIMPLE_DEV_PM_OPS(ocores_i2c_pm, ocores_i2c_suspend, ocores_i2c_resume);
 485 #define OCORES_I2C_PM   (&ocores_i2c_pm)
 486 #else
 487 #define OCORES_I2C_PM   NULL
 488 #endif
 489
 490 static struct platform_driver ocores_i2c_driver = {
 491         .probe   = ocores_i2c_probe,
 492         .remove  = __devexit_p(ocores_i2c_remove),
 493         .driver  = {
 494                 .owner = THIS_MODULE,
 495                 .name = "ocores-i2c",
 496                 .of_match_table = ocores_i2c_match,
 497                 .pm = OCORES_I2C_PM,
 498         },
 499 };
 500
 501 module_platform_driver(ocores_i2c_driver);
 502
 503 MODULE_AUTHOR("Peter Korsgaard <jacmet@sunsite.dk>");
 504 MODULE_DESCRIPTION("OpenCores I2C bus driver");
 505 MODULE_LICENSE("GPL");
 506 MODULE_ALIAS("platform:ocores-i2c");