2 * TI OMAP I2C master mode driver
4 * Copyright (C) 2003 MontaVista Software, Inc.
5 * Copyright (C) 2005 Nokia Corporation
6 * Copyright (C) 2004 - 2007 Texas Instruments.
8 * Originally written by MontaVista Software, Inc.
9 * Additional contributions by:
10 * Tony Lindgren <tony@atomide.com>
11 * Imre Deak <imre.deak@nokia.com>
12 * Juha Yrjölä <juha.yrjola@solidboot.com>
13 * Syed Khasim <x0khasim@ti.com>
14 * Nishant Menon <nm@ti.com>
16 * This program is free software; you can redistribute it and/or modify
17 * it under the terms of the GNU General Public License as published by
18 * the Free Software Foundation; either version 2 of the License, or
19 * (at your option) any later version.
21 * This program is distributed in the hope that it will be useful,
22 * but WITHOUT ANY WARRANTY; without even the implied warranty of
23 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
24 * GNU General Public License for more details.
26 * You should have received a copy of the GNU General Public License
27 * along with this program; if not, write to the Free Software
28 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
31 #include <linux/module.h>
32 #include <linux/delay.h>
33 #include <linux/i2c.h>
34 #include <linux/err.h>
35 #include <linux/interrupt.h>
36 #include <linux/completion.h>
37 #include <linux/platform_device.h>
38 #include <linux/clk.h>
40 #include <linux/slab.h>
41 #include <linux/i2c-omap.h>
42 #include <linux/pm_runtime.h>
44 /* I2C controller revisions */
45 #define OMAP_I2C_REV_2 0x20
47 /* I2C controller revisions present on specific hardware */
48 #define OMAP_I2C_REV_ON_2430 0x36
49 #define OMAP_I2C_REV_ON_3430 0x3C
50 #define OMAP_I2C_REV_ON_4430 0x40
52 /* timeout waiting for the controller to respond */
53 #define OMAP_I2C_TIMEOUT (msecs_to_jiffies(1000))
55 /* For OMAP3 I2C_IV has changed to I2C_WE (wakeup enable) */
77 OMAP_I2C_IRQSTATUS_RAW,
78 OMAP_I2C_IRQENABLE_SET,
79 OMAP_I2C_IRQENABLE_CLR,
82 /* I2C Interrupt Enable Register (OMAP_I2C_IE): */
83 #define OMAP_I2C_IE_XDR (1 << 14) /* TX Buffer drain int enable */
84 #define OMAP_I2C_IE_RDR (1 << 13) /* RX Buffer drain int enable */
85 #define OMAP_I2C_IE_XRDY (1 << 4) /* TX data ready int enable */
86 #define OMAP_I2C_IE_RRDY (1 << 3) /* RX data ready int enable */
87 #define OMAP_I2C_IE_ARDY (1 << 2) /* Access ready int enable */
88 #define OMAP_I2C_IE_NACK (1 << 1) /* No ack interrupt enable */
89 #define OMAP_I2C_IE_AL (1 << 0) /* Arbitration lost int ena */
91 /* I2C Status Register (OMAP_I2C_STAT): */
92 #define OMAP_I2C_STAT_XDR (1 << 14) /* TX Buffer draining */
93 #define OMAP_I2C_STAT_RDR (1 << 13) /* RX Buffer draining */
94 #define OMAP_I2C_STAT_BB (1 << 12) /* Bus busy */
95 #define OMAP_I2C_STAT_ROVR (1 << 11) /* Receive overrun */
96 #define OMAP_I2C_STAT_XUDF (1 << 10) /* Transmit underflow */
97 #define OMAP_I2C_STAT_AAS (1 << 9) /* Address as slave */
98 #define OMAP_I2C_STAT_AD0 (1 << 8) /* Address zero */
99 #define OMAP_I2C_STAT_XRDY (1 << 4) /* Transmit data ready */
100 #define OMAP_I2C_STAT_RRDY (1 << 3) /* Receive data ready */
101 #define OMAP_I2C_STAT_ARDY (1 << 2) /* Register access ready */
102 #define OMAP_I2C_STAT_NACK (1 << 1) /* No ack interrupt enable */
103 #define OMAP_I2C_STAT_AL (1 << 0) /* Arbitration lost int ena */
105 /* I2C WE wakeup enable register */
106 #define OMAP_I2C_WE_XDR_WE (1 << 14) /* TX drain wakup */
107 #define OMAP_I2C_WE_RDR_WE (1 << 13) /* RX drain wakeup */
108 #define OMAP_I2C_WE_AAS_WE (1 << 9) /* Address as slave wakeup*/
109 #define OMAP_I2C_WE_BF_WE (1 << 8) /* Bus free wakeup */
110 #define OMAP_I2C_WE_STC_WE (1 << 6) /* Start condition wakeup */
111 #define OMAP_I2C_WE_GC_WE (1 << 5) /* General call wakeup */
112 #define OMAP_I2C_WE_DRDY_WE (1 << 3) /* TX/RX data ready wakeup */
113 #define OMAP_I2C_WE_ARDY_WE (1 << 2) /* Reg access ready wakeup */
114 #define OMAP_I2C_WE_NACK_WE (1 << 1) /* No acknowledgment wakeup */
115 #define OMAP_I2C_WE_AL_WE (1 << 0) /* Arbitration lost wakeup */
117 #define OMAP_I2C_WE_ALL (OMAP_I2C_WE_XDR_WE | OMAP_I2C_WE_RDR_WE | \
118 OMAP_I2C_WE_AAS_WE | OMAP_I2C_WE_BF_WE | \
119 OMAP_I2C_WE_STC_WE | OMAP_I2C_WE_GC_WE | \
120 OMAP_I2C_WE_DRDY_WE | OMAP_I2C_WE_ARDY_WE | \
121 OMAP_I2C_WE_NACK_WE | OMAP_I2C_WE_AL_WE)
123 /* I2C Buffer Configuration Register (OMAP_I2C_BUF): */
124 #define OMAP_I2C_BUF_RDMA_EN (1 << 15) /* RX DMA channel enable */
125 #define OMAP_I2C_BUF_RXFIF_CLR (1 << 14) /* RX FIFO Clear */
126 #define OMAP_I2C_BUF_XDMA_EN (1 << 7) /* TX DMA channel enable */
127 #define OMAP_I2C_BUF_TXFIF_CLR (1 << 6) /* TX FIFO Clear */
129 /* I2C Configuration Register (OMAP_I2C_CON): */
130 #define OMAP_I2C_CON_EN (1 << 15) /* I2C module enable */
131 #define OMAP_I2C_CON_BE (1 << 14) /* Big endian mode */
132 #define OMAP_I2C_CON_OPMODE_HS (1 << 12) /* High Speed support */
133 #define OMAP_I2C_CON_STB (1 << 11) /* Start byte mode (master) */
134 #define OMAP_I2C_CON_MST (1 << 10) /* Master/slave mode */
135 #define OMAP_I2C_CON_TRX (1 << 9) /* TX/RX mode (master only) */
136 #define OMAP_I2C_CON_XA (1 << 8) /* Expand address */
137 #define OMAP_I2C_CON_RM (1 << 2) /* Repeat mode (master only) */
138 #define OMAP_I2C_CON_STP (1 << 1) /* Stop cond (master only) */
139 #define OMAP_I2C_CON_STT (1 << 0) /* Start condition (master) */
141 /* I2C SCL time value when Master */
142 #define OMAP_I2C_SCLL_HSSCLL 8
143 #define OMAP_I2C_SCLH_HSSCLH 8
145 /* I2C System Test Register (OMAP_I2C_SYSTEST): */
147 #define OMAP_I2C_SYSTEST_ST_EN (1 << 15) /* System test enable */
148 #define OMAP_I2C_SYSTEST_FREE (1 << 14) /* Free running mode */
149 #define OMAP_I2C_SYSTEST_TMODE_MASK (3 << 12) /* Test mode select */
150 #define OMAP_I2C_SYSTEST_TMODE_SHIFT (12) /* Test mode select */
151 #define OMAP_I2C_SYSTEST_SCL_I (1 << 3) /* SCL line sense in */
152 #define OMAP_I2C_SYSTEST_SCL_O (1 << 2) /* SCL line drive out */
153 #define OMAP_I2C_SYSTEST_SDA_I (1 << 1) /* SDA line sense in */
154 #define OMAP_I2C_SYSTEST_SDA_O (1 << 0) /* SDA line drive out */
157 /* OCP_SYSSTATUS bit definitions */
158 #define SYSS_RESETDONE_MASK (1 << 0)
160 /* OCP_SYSCONFIG bit definitions */
161 #define SYSC_CLOCKACTIVITY_MASK (0x3 << 8)
162 #define SYSC_SIDLEMODE_MASK (0x3 << 3)
163 #define SYSC_ENAWAKEUP_MASK (1 << 2)
164 #define SYSC_SOFTRESET_MASK (1 << 1)
165 #define SYSC_AUTOIDLE_MASK (1 << 0)
167 #define SYSC_IDLEMODE_SMART 0x2
168 #define SYSC_CLOCKACTIVITY_FCLK 0x2
170 /* Errata definitions */
171 #define I2C_OMAP_ERRATA_I207 (1 << 0)
172 #define I2C_OMAP3_1P153 (1 << 1)
174 struct omap_i2c_dev {
176 void __iomem *base; /* virtual */
178 int reg_shift; /* bit shift for I2C register addresses */
179 struct completion cmd_complete;
180 struct resource *ioarea;
181 u32 latency; /* maximum mpu wkup latency */
182 void (*set_mpu_wkup_lat)(struct device *dev,
184 u32 speed; /* Speed of bus in Khz */
189 struct i2c_adapter adapter;
190 u8 fifo_size; /* use as flag and value
191 * fifo_size==0 implies no fifo
192 * if set, should be trsh+1
195 unsigned b_hw:1; /* bad h/w fixes */
197 u16 iestate; /* Saved interrupt register */
207 const static u8 reg_map[] = {
208 [OMAP_I2C_REV_REG] = 0x00,
209 [OMAP_I2C_IE_REG] = 0x01,
210 [OMAP_I2C_STAT_REG] = 0x02,
211 [OMAP_I2C_IV_REG] = 0x03,
212 [OMAP_I2C_WE_REG] = 0x03,
213 [OMAP_I2C_SYSS_REG] = 0x04,
214 [OMAP_I2C_BUF_REG] = 0x05,
215 [OMAP_I2C_CNT_REG] = 0x06,
216 [OMAP_I2C_DATA_REG] = 0x07,
217 [OMAP_I2C_SYSC_REG] = 0x08,
218 [OMAP_I2C_CON_REG] = 0x09,
219 [OMAP_I2C_OA_REG] = 0x0a,
220 [OMAP_I2C_SA_REG] = 0x0b,
221 [OMAP_I2C_PSC_REG] = 0x0c,
222 [OMAP_I2C_SCLL_REG] = 0x0d,
223 [OMAP_I2C_SCLH_REG] = 0x0e,
224 [OMAP_I2C_SYSTEST_REG] = 0x0f,
225 [OMAP_I2C_BUFSTAT_REG] = 0x10,
228 const static u8 omap4_reg_map[] = {
229 [OMAP_I2C_REV_REG] = 0x04,
230 [OMAP_I2C_IE_REG] = 0x2c,
231 [OMAP_I2C_STAT_REG] = 0x28,
232 [OMAP_I2C_IV_REG] = 0x34,
233 [OMAP_I2C_WE_REG] = 0x34,
234 [OMAP_I2C_SYSS_REG] = 0x90,
235 [OMAP_I2C_BUF_REG] = 0x94,
236 [OMAP_I2C_CNT_REG] = 0x98,
237 [OMAP_I2C_DATA_REG] = 0x9c,
238 [OMAP_I2C_SYSC_REG] = 0x20,
239 [OMAP_I2C_CON_REG] = 0xa4,
240 [OMAP_I2C_OA_REG] = 0xa8,
241 [OMAP_I2C_SA_REG] = 0xac,
242 [OMAP_I2C_PSC_REG] = 0xb0,
243 [OMAP_I2C_SCLL_REG] = 0xb4,
244 [OMAP_I2C_SCLH_REG] = 0xb8,
245 [OMAP_I2C_SYSTEST_REG] = 0xbC,
246 [OMAP_I2C_BUFSTAT_REG] = 0xc0,
247 [OMAP_I2C_REVNB_LO] = 0x00,
248 [OMAP_I2C_REVNB_HI] = 0x04,
249 [OMAP_I2C_IRQSTATUS_RAW] = 0x24,
250 [OMAP_I2C_IRQENABLE_SET] = 0x2c,
251 [OMAP_I2C_IRQENABLE_CLR] = 0x30,
254 static inline void omap_i2c_write_reg(struct omap_i2c_dev *i2c_dev,
257 __raw_writew(val, i2c_dev->base +
258 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
261 static inline u16 omap_i2c_read_reg(struct omap_i2c_dev *i2c_dev, int reg)
263 return __raw_readw(i2c_dev->base +
264 (i2c_dev->regs[reg] << i2c_dev->reg_shift));
267 static void omap_i2c_unidle(struct omap_i2c_dev *dev)
269 struct platform_device *pdev;
270 struct omap_i2c_bus_platform_data *pdata;
274 pdev = to_platform_device(dev->dev);
275 pdata = pdev->dev.platform_data;
277 pm_runtime_get_sync(&pdev->dev);
279 if (cpu_is_omap34xx()) {
280 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
281 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, dev->pscstate);
282 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, dev->scllstate);
283 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, dev->sclhstate);
284 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, dev->bufstate);
285 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, dev->syscstate);
286 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG, dev->westate);
287 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
292 * Don't write to this register if the IE state is 0 as it can
296 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
299 static void omap_i2c_idle(struct omap_i2c_dev *dev)
301 struct platform_device *pdev;
302 struct omap_i2c_bus_platform_data *pdata;
307 pdev = to_platform_device(dev->dev);
308 pdata = pdev->dev.platform_data;
310 dev->iestate = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
311 if (dev->rev >= OMAP_I2C_REV_ON_4430)
312 omap_i2c_write_reg(dev, OMAP_I2C_IRQENABLE_CLR, 1);
314 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, 0);
316 if (dev->rev < OMAP_I2C_REV_2) {
317 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG); /* Read clears */
319 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, dev->iestate);
321 /* Flush posted write before the dev->idle store occurs */
322 omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
326 pm_runtime_put_sync(&pdev->dev);
329 static int omap_i2c_init(struct omap_i2c_dev *dev)
331 u16 psc = 0, scll = 0, sclh = 0, buf = 0;
332 u16 fsscll = 0, fssclh = 0, hsscll = 0, hssclh = 0;
333 unsigned long fclk_rate = 12000000;
334 unsigned long timeout;
335 unsigned long internal_clk = 0;
338 if (dev->rev >= OMAP_I2C_REV_2) {
339 /* Disable I2C controller before soft reset */
340 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
341 omap_i2c_read_reg(dev, OMAP_I2C_CON_REG) &
344 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG, SYSC_SOFTRESET_MASK);
345 /* For some reason we need to set the EN bit before the
346 * reset done bit gets set. */
347 timeout = jiffies + OMAP_I2C_TIMEOUT;
348 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
349 while (!(omap_i2c_read_reg(dev, OMAP_I2C_SYSS_REG) &
350 SYSS_RESETDONE_MASK)) {
351 if (time_after(jiffies, timeout)) {
352 dev_warn(dev->dev, "timeout waiting "
353 "for controller reset\n");
359 /* SYSC register is cleared by the reset; rewrite it */
360 if (dev->rev == OMAP_I2C_REV_ON_2430) {
362 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
365 } else if (dev->rev >= OMAP_I2C_REV_ON_3430) {
366 dev->syscstate = SYSC_AUTOIDLE_MASK;
367 dev->syscstate |= SYSC_ENAWAKEUP_MASK;
368 dev->syscstate |= (SYSC_IDLEMODE_SMART <<
369 __ffs(SYSC_SIDLEMODE_MASK));
370 dev->syscstate |= (SYSC_CLOCKACTIVITY_FCLK <<
371 __ffs(SYSC_CLOCKACTIVITY_MASK));
373 omap_i2c_write_reg(dev, OMAP_I2C_SYSC_REG,
376 * Enabling all wakup sources to stop I2C freezing on
378 * REVISIT: Some wkup sources might not be needed.
380 dev->westate = OMAP_I2C_WE_ALL;
381 if (dev->rev < OMAP_I2C_REV_ON_4430)
382 omap_i2c_write_reg(dev, OMAP_I2C_WE_REG,
386 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
388 if (cpu_class_is_omap1()) {
390 * The I2C functional clock is the armxor_ck, so there's
391 * no need to get "armxor_ck" separately. Now, if OMAP2420
392 * always returns 12MHz for the functional clock, we can
393 * do this bit unconditionally.
395 fclk = clk_get(dev->dev, "fck");
396 fclk_rate = clk_get_rate(fclk);
399 /* TRM for 5912 says the I2C clock must be prescaled to be
400 * between 7 - 12 MHz. The XOR input clock is typically
401 * 12, 13 or 19.2 MHz. So we should have code that produces:
403 * XOR MHz Divider Prescaler
408 if (fclk_rate > 12000000)
409 psc = fclk_rate / 12000000;
412 if (!(cpu_class_is_omap1() || cpu_is_omap2420())) {
415 * HSI2C controller internal clk rate should be 19.2 Mhz for
416 * HS and for all modes on 2430. On 34xx we can use lower rate
417 * to get longer filter period for better noise suppression.
418 * The filter is iclk (fclk for HS) period.
420 if (dev->speed > 400 || cpu_is_omap2430())
421 internal_clk = 19200;
422 else if (dev->speed > 100)
426 fclk = clk_get(dev->dev, "fck");
427 fclk_rate = clk_get_rate(fclk) / 1000;
430 /* Compute prescaler divisor */
431 psc = fclk_rate / internal_clk;
434 /* If configured for High Speed */
435 if (dev->speed > 400) {
438 /* For first phase of HS mode */
439 scl = internal_clk / 400;
440 fsscll = scl - (scl / 3) - 7;
441 fssclh = (scl / 3) - 5;
443 /* For second phase of HS mode */
444 scl = fclk_rate / dev->speed;
445 hsscll = scl - (scl / 3) - 7;
446 hssclh = (scl / 3) - 5;
447 } else if (dev->speed > 100) {
451 scl = internal_clk / dev->speed;
452 fsscll = scl - (scl / 3) - 7;
453 fssclh = (scl / 3) - 5;
456 fsscll = internal_clk / (dev->speed * 2) - 7;
457 fssclh = internal_clk / (dev->speed * 2) - 5;
459 scll = (hsscll << OMAP_I2C_SCLL_HSSCLL) | fsscll;
460 sclh = (hssclh << OMAP_I2C_SCLH_HSSCLH) | fssclh;
462 /* Program desired operating rate */
463 fclk_rate /= (psc + 1) * 1000;
466 scll = fclk_rate / (dev->speed * 2) - 7 + psc;
467 sclh = fclk_rate / (dev->speed * 2) - 7 + psc;
470 /* Setup clock prescaler to obtain approx 12MHz I2C module clock: */
471 omap_i2c_write_reg(dev, OMAP_I2C_PSC_REG, psc);
473 /* SCL low and high time values */
474 omap_i2c_write_reg(dev, OMAP_I2C_SCLL_REG, scll);
475 omap_i2c_write_reg(dev, OMAP_I2C_SCLH_REG, sclh);
477 if (dev->fifo_size) {
478 /* Note: setup required fifo size - 1. RTRSH and XTRSH */
479 buf = (dev->fifo_size - 1) << 8 | OMAP_I2C_BUF_RXFIF_CLR |
480 (dev->fifo_size - 1) | OMAP_I2C_BUF_TXFIF_CLR;
481 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, buf);
484 /* Take the I2C module out of reset: */
485 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_EN);
489 if (cpu_is_omap2430() || cpu_is_omap34xx())
490 dev->errata |= I2C_OMAP_ERRATA_I207;
492 /* Enable interrupts */
493 dev->iestate = (OMAP_I2C_IE_XRDY | OMAP_I2C_IE_RRDY |
494 OMAP_I2C_IE_ARDY | OMAP_I2C_IE_NACK |
495 OMAP_I2C_IE_AL) | ((dev->fifo_size) ?
496 (OMAP_I2C_IE_RDR | OMAP_I2C_IE_XDR) : 0);
497 omap_i2c_write_reg(dev, OMAP_I2C_IE_REG, dev->iestate);
498 if (cpu_is_omap34xx()) {
500 dev->scllstate = scll;
501 dev->sclhstate = sclh;
508 * Waiting on Bus Busy
510 static int omap_i2c_wait_for_bb(struct omap_i2c_dev *dev)
512 unsigned long timeout;
514 timeout = jiffies + OMAP_I2C_TIMEOUT;
515 while (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG) & OMAP_I2C_STAT_BB) {
516 if (time_after(jiffies, timeout)) {
517 dev_warn(dev->dev, "timeout waiting for bus ready\n");
527 * Low level master read/write transaction.
529 static int omap_i2c_xfer_msg(struct i2c_adapter *adap,
530 struct i2c_msg *msg, int stop)
532 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
536 dev_dbg(dev->dev, "addr: 0x%04x, len: %d, flags: 0x%x, stop: %d\n",
537 msg->addr, msg->len, msg->flags, stop);
542 omap_i2c_write_reg(dev, OMAP_I2C_SA_REG, msg->addr);
544 /* REVISIT: Could the STB bit of I2C_CON be used with probing? */
546 dev->buf_len = msg->len;
548 omap_i2c_write_reg(dev, OMAP_I2C_CNT_REG, dev->buf_len);
550 /* Clear the FIFO Buffers */
551 w = omap_i2c_read_reg(dev, OMAP_I2C_BUF_REG);
552 w |= OMAP_I2C_BUF_RXFIF_CLR | OMAP_I2C_BUF_TXFIF_CLR;
553 omap_i2c_write_reg(dev, OMAP_I2C_BUF_REG, w);
555 init_completion(&dev->cmd_complete);
558 w = OMAP_I2C_CON_EN | OMAP_I2C_CON_MST | OMAP_I2C_CON_STT;
560 /* High speed configuration */
561 if (dev->speed > 400)
562 w |= OMAP_I2C_CON_OPMODE_HS;
564 if (msg->flags & I2C_M_TEN)
565 w |= OMAP_I2C_CON_XA;
566 if (!(msg->flags & I2C_M_RD))
567 w |= OMAP_I2C_CON_TRX;
569 if (!dev->b_hw && stop)
570 w |= OMAP_I2C_CON_STP;
572 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
575 * Don't write stt and stp together on some hardware.
577 if (dev->b_hw && stop) {
578 unsigned long delay = jiffies + OMAP_I2C_TIMEOUT;
579 u16 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
580 while (con & OMAP_I2C_CON_STT) {
581 con = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
583 /* Let the user know if i2c is in a bad state */
584 if (time_after(jiffies, delay)) {
585 dev_err(dev->dev, "controller timed out "
586 "waiting for start condition to finish\n");
592 w |= OMAP_I2C_CON_STP;
593 w &= ~OMAP_I2C_CON_STT;
594 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
598 * REVISIT: We should abort the transfer on signals, but the bus goes
599 * into arbitration and we're currently unable to recover from it.
601 r = wait_for_completion_timeout(&dev->cmd_complete,
607 dev_err(dev->dev, "controller timed out\n");
612 if (likely(!dev->cmd_err))
615 /* We have an error */
616 if (dev->cmd_err & (OMAP_I2C_STAT_AL | OMAP_I2C_STAT_ROVR |
617 OMAP_I2C_STAT_XUDF)) {
622 if (dev->cmd_err & OMAP_I2C_STAT_NACK) {
623 if (msg->flags & I2C_M_IGNORE_NAK)
626 w = omap_i2c_read_reg(dev, OMAP_I2C_CON_REG);
627 w |= OMAP_I2C_CON_STP;
628 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, w);
637 * Prepare controller for a transaction and call omap_i2c_xfer_msg
638 * to do the work during IRQ processing.
641 omap_i2c_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
643 struct omap_i2c_dev *dev = i2c_get_adapdata(adap);
647 omap_i2c_unidle(dev);
649 r = omap_i2c_wait_for_bb(dev);
653 if (dev->set_mpu_wkup_lat != NULL)
654 dev->set_mpu_wkup_lat(dev->dev, dev->latency);
656 for (i = 0; i < num; i++) {
657 r = omap_i2c_xfer_msg(adap, &msgs[i], (i == (num - 1)));
662 if (dev->set_mpu_wkup_lat != NULL)
663 dev->set_mpu_wkup_lat(dev->dev, -1);
668 omap_i2c_wait_for_bb(dev);
675 omap_i2c_func(struct i2c_adapter *adap)
677 return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
681 omap_i2c_complete_cmd(struct omap_i2c_dev *dev, u16 err)
684 complete(&dev->cmd_complete);
688 omap_i2c_ack_stat(struct omap_i2c_dev *dev, u16 stat)
690 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat);
693 static inline void i2c_omap_errata_i207(struct omap_i2c_dev *dev, u16 stat)
696 * I2C Errata(Errata Nos. OMAP2: 1.67, OMAP3: 1.8)
697 * Not applicable for OMAP4.
698 * Under certain rare conditions, RDR could be set again
699 * when the bus is busy, then ignore the interrupt and
700 * clear the interrupt.
702 if (stat & OMAP_I2C_STAT_RDR) {
703 /* Step 1: If RDR is set, clear it */
704 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
707 if (!(omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
708 & OMAP_I2C_STAT_BB)) {
711 if (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG)
712 & OMAP_I2C_STAT_RDR) {
713 omap_i2c_ack_stat(dev, OMAP_I2C_STAT_RDR);
714 dev_dbg(dev->dev, "RDR when bus is busy.\n");
721 /* rev1 devices are apparently only on some 15xx */
722 #ifdef CONFIG_ARCH_OMAP15XX
725 omap_i2c_rev1_isr(int this_irq, void *dev_id)
727 struct omap_i2c_dev *dev = dev_id;
733 iv = omap_i2c_read_reg(dev, OMAP_I2C_IV_REG);
735 case 0x00: /* None */
737 case 0x01: /* Arbitration lost */
738 dev_err(dev->dev, "Arbitration lost\n");
739 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_AL);
741 case 0x02: /* No acknowledgement */
742 omap_i2c_complete_cmd(dev, OMAP_I2C_STAT_NACK);
743 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, OMAP_I2C_CON_STP);
745 case 0x03: /* Register access ready */
746 omap_i2c_complete_cmd(dev, 0);
748 case 0x04: /* Receive data ready */
750 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
754 *dev->buf++ = w >> 8;
758 dev_err(dev->dev, "RRDY IRQ while no data requested\n");
760 case 0x05: /* Transmit data ready */
765 w |= *dev->buf++ << 8;
768 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
770 dev_err(dev->dev, "XRDY IRQ while no data to send\n");
779 #define omap_i2c_rev1_isr NULL
783 * OMAP3430 Errata 1.153: When an XRDY/XDR is hit, wait for XUDF before writing
784 * data to DATA_REG. Otherwise some data bytes can be lost while transferring
785 * them from the memory to the I2C interface.
787 static int errata_omap3_1p153(struct omap_i2c_dev *dev, u16 *stat, int *err)
789 unsigned long timeout = 10000;
791 while (--timeout && !(*stat & OMAP_I2C_STAT_XUDF)) {
792 if (*stat & (OMAP_I2C_STAT_NACK | OMAP_I2C_STAT_AL)) {
793 omap_i2c_ack_stat(dev, *stat & (OMAP_I2C_STAT_XRDY |
795 *err |= OMAP_I2C_STAT_XUDF;
800 *stat = omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG);
804 dev_err(dev->dev, "timeout waiting on XUDF bit\n");
812 omap_i2c_isr(int this_irq, void *dev_id)
814 struct omap_i2c_dev *dev = dev_id;
822 bits = omap_i2c_read_reg(dev, OMAP_I2C_IE_REG);
823 while ((stat = (omap_i2c_read_reg(dev, OMAP_I2C_STAT_REG))) & bits) {
824 dev_dbg(dev->dev, "IRQ (ISR = 0x%04x)\n", stat);
825 if (count++ == 100) {
826 dev_warn(dev->dev, "Too much work in one IRQ\n");
833 * Ack the stat in one go, but [R/X]DR and [R/X]RDY should be
834 * acked after the data operation is complete.
835 * Ref: TRM SWPU114Q Figure 18-31
837 omap_i2c_write_reg(dev, OMAP_I2C_STAT_REG, stat &
838 ~(OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
839 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
841 if (stat & OMAP_I2C_STAT_NACK) {
842 err |= OMAP_I2C_STAT_NACK;
843 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG,
846 if (stat & OMAP_I2C_STAT_AL) {
847 dev_err(dev->dev, "Arbitration lost\n");
848 err |= OMAP_I2C_STAT_AL;
851 * ProDB0017052: Clear ARDY bit twice
853 if (stat & (OMAP_I2C_STAT_ARDY | OMAP_I2C_STAT_NACK |
855 omap_i2c_ack_stat(dev, stat &
856 (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR |
857 OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR |
858 OMAP_I2C_STAT_ARDY));
859 omap_i2c_complete_cmd(dev, err);
862 if (stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR)) {
865 if (dev->errata & I2C_OMAP_ERRATA_I207)
866 i2c_omap_errata_i207(dev, stat);
868 if (dev->fifo_size) {
869 if (stat & OMAP_I2C_STAT_RRDY)
870 num_bytes = dev->fifo_size;
871 else /* read RXSTAT on RDR interrupt */
872 num_bytes = (omap_i2c_read_reg(dev,
873 OMAP_I2C_BUFSTAT_REG)
878 w = omap_i2c_read_reg(dev, OMAP_I2C_DATA_REG);
883 * Data reg in 2430, omap3 and
884 * omap4 is 8 bit wide
886 if (cpu_class_is_omap1() ||
889 *dev->buf++ = w >> 8;
894 if (stat & OMAP_I2C_STAT_RRDY)
896 "RRDY IRQ while no data"
898 if (stat & OMAP_I2C_STAT_RDR)
900 "RDR IRQ while no data"
905 omap_i2c_ack_stat(dev,
906 stat & (OMAP_I2C_STAT_RRDY | OMAP_I2C_STAT_RDR));
909 if (stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR)) {
911 if (dev->fifo_size) {
912 if (stat & OMAP_I2C_STAT_XRDY)
913 num_bytes = dev->fifo_size;
914 else /* read TXSTAT on XDR interrupt */
915 num_bytes = omap_i2c_read_reg(dev,
916 OMAP_I2C_BUFSTAT_REG)
926 * Data reg in 2430, omap3 and
927 * omap4 is 8 bit wide
929 if (cpu_class_is_omap1() ||
932 w |= *dev->buf++ << 8;
937 if (stat & OMAP_I2C_STAT_XRDY)
941 if (stat & OMAP_I2C_STAT_XDR)
948 if ((dev->errata & I2C_OMAP3_1P153) &&
949 errata_omap3_1p153(dev, &stat, &err))
952 omap_i2c_write_reg(dev, OMAP_I2C_DATA_REG, w);
954 omap_i2c_ack_stat(dev,
955 stat & (OMAP_I2C_STAT_XRDY | OMAP_I2C_STAT_XDR));
958 if (stat & OMAP_I2C_STAT_ROVR) {
959 dev_err(dev->dev, "Receive overrun\n");
960 dev->cmd_err |= OMAP_I2C_STAT_ROVR;
962 if (stat & OMAP_I2C_STAT_XUDF) {
963 dev_err(dev->dev, "Transmit underflow\n");
964 dev->cmd_err |= OMAP_I2C_STAT_XUDF;
968 return count ? IRQ_HANDLED : IRQ_NONE;
971 static const struct i2c_algorithm omap_i2c_algo = {
972 .master_xfer = omap_i2c_xfer,
973 .functionality = omap_i2c_func,
977 omap_i2c_probe(struct platform_device *pdev)
979 struct omap_i2c_dev *dev;
980 struct i2c_adapter *adap;
981 struct resource *mem, *irq, *ioarea;
982 struct omap_i2c_bus_platform_data *pdata = pdev->dev.platform_data;
987 /* NOTE: driver uses the static register mapping */
988 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
990 dev_err(&pdev->dev, "no mem resource?\n");
993 irq = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
995 dev_err(&pdev->dev, "no irq resource?\n");
999 ioarea = request_mem_region(mem->start, resource_size(mem),
1002 dev_err(&pdev->dev, "I2C region already claimed\n");
1006 dev = kzalloc(sizeof(struct omap_i2c_dev), GFP_KERNEL);
1009 goto err_release_region;
1012 if (pdata != NULL) {
1013 speed = pdata->clkrate;
1014 dev->set_mpu_wkup_lat = pdata->set_mpu_wkup_lat;
1016 speed = 100; /* Default speed */
1017 dev->set_mpu_wkup_lat = NULL;
1022 dev->dev = &pdev->dev;
1023 dev->irq = irq->start;
1024 dev->base = ioremap(mem->start, resource_size(mem));
1030 platform_set_drvdata(pdev, dev);
1032 if (cpu_is_omap7xx())
1034 else if (cpu_is_omap44xx())
1039 if (cpu_is_omap44xx())
1040 dev->regs = (u8 *) omap4_reg_map;
1042 dev->regs = (u8 *) reg_map;
1044 pm_runtime_enable(&pdev->dev);
1045 omap_i2c_unidle(dev);
1047 dev->rev = omap_i2c_read_reg(dev, OMAP_I2C_REV_REG) & 0xff;
1049 if (dev->rev <= OMAP_I2C_REV_ON_3430)
1050 dev->errata |= I2C_OMAP3_1P153;
1052 if (!(cpu_class_is_omap1() || cpu_is_omap2420())) {
1055 /* Set up the fifo size - Get total size */
1056 s = (omap_i2c_read_reg(dev, OMAP_I2C_BUFSTAT_REG) >> 14) & 0x3;
1057 dev->fifo_size = 0x8 << s;
1060 * Set up notification threshold as half the total available
1061 * size. This is to ensure that we can handle the status on int
1062 * call back latencies.
1064 if (dev->rev >= OMAP_I2C_REV_ON_4430) {
1066 dev->b_hw = 0; /* Disable hardware fixes */
1068 dev->fifo_size = (dev->fifo_size / 2);
1069 dev->b_hw = 1; /* Enable hardware fixes */
1071 /* calculate wakeup latency constraint for MPU */
1072 if (dev->set_mpu_wkup_lat != NULL)
1073 dev->latency = (1000000 * dev->fifo_size) /
1077 /* reset ASAP, clearing any IRQs */
1080 isr = (dev->rev < OMAP_I2C_REV_2) ? omap_i2c_rev1_isr : omap_i2c_isr;
1081 r = request_irq(dev->irq, isr, 0, pdev->name, dev);
1084 dev_err(dev->dev, "failure requesting irq %i\n", dev->irq);
1085 goto err_unuse_clocks;
1088 dev_info(dev->dev, "bus %d rev%d.%d at %d kHz\n",
1089 pdev->id, dev->rev >> 4, dev->rev & 0xf, dev->speed);
1093 adap = &dev->adapter;
1094 i2c_set_adapdata(adap, dev);
1095 adap->owner = THIS_MODULE;
1096 adap->class = I2C_CLASS_HWMON;
1097 strlcpy(adap->name, "OMAP I2C adapter", sizeof(adap->name));
1098 adap->algo = &omap_i2c_algo;
1099 adap->dev.parent = &pdev->dev;
1101 /* i2c device drivers may be active on return from add_adapter() */
1102 adap->nr = pdev->id;
1103 r = i2c_add_numbered_adapter(adap);
1105 dev_err(dev->dev, "failure adding adapter\n");
1112 free_irq(dev->irq, dev);
1114 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1118 platform_set_drvdata(pdev, NULL);
1121 release_mem_region(mem->start, resource_size(mem));
1127 omap_i2c_remove(struct platform_device *pdev)
1129 struct omap_i2c_dev *dev = platform_get_drvdata(pdev);
1130 struct resource *mem;
1132 platform_set_drvdata(pdev, NULL);
1134 free_irq(dev->irq, dev);
1135 i2c_del_adapter(&dev->adapter);
1136 omap_i2c_write_reg(dev, OMAP_I2C_CON_REG, 0);
1139 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
1140 release_mem_region(mem->start, resource_size(mem));
1144 #ifdef CONFIG_SUSPEND
1145 static int omap_i2c_suspend(struct device *dev)
1147 if (!pm_runtime_suspended(dev))
1148 if (dev->bus && dev->bus->pm && dev->bus->pm->runtime_suspend)
1149 dev->bus->pm->runtime_suspend(dev);
1154 static int omap_i2c_resume(struct device *dev)
1156 if (!pm_runtime_suspended(dev))
1157 if (dev->bus && dev->bus->pm && dev->bus->pm->runtime_resume)
1158 dev->bus->pm->runtime_resume(dev);
1163 static struct dev_pm_ops omap_i2c_pm_ops = {
1164 .suspend = omap_i2c_suspend,
1165 .resume = omap_i2c_resume,
1167 #define OMAP_I2C_PM_OPS (&omap_i2c_pm_ops)
1169 #define OMAP_I2C_PM_OPS NULL
1172 static struct platform_driver omap_i2c_driver = {
1173 .probe = omap_i2c_probe,
1174 .remove = omap_i2c_remove,
1177 .owner = THIS_MODULE,
1178 .pm = OMAP_I2C_PM_OPS,
1182 /* I2C may be needed to bring up other drivers */
1184 omap_i2c_init_driver(void)
1186 return platform_driver_register(&omap_i2c_driver);
1188 subsys_initcall(omap_i2c_init_driver);
1190 static void __exit omap_i2c_exit_driver(void)
1192 platform_driver_unregister(&omap_i2c_driver);
1194 module_exit(omap_i2c_exit_driver);
1196 MODULE_AUTHOR("MontaVista Software, Inc. (and others)");
1197 MODULE_DESCRIPTION("TI OMAP I2C bus adapter");
1198 MODULE_LICENSE("GPL");
1199 MODULE_ALIAS("platform:omap_i2c");