2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and
3 Philip Edelbrock <phil@netroedge.com>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
23 Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100
24 ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800
28 Note: we assume there can only be one device, with one or more
32 #include <linux/module.h>
33 #include <linux/moduleparam.h>
34 #include <linux/pci.h>
35 #include <linux/kernel.h>
36 #include <linux/delay.h>
37 #include <linux/stddef.h>
38 #include <linux/ioport.h>
39 #include <linux/i2c.h>
40 #include <linux/slab.h>
41 #include <linux/init.h>
42 #include <linux/dmi.h>
43 #include <linux/acpi.h>
47 /* PIIX4 SMBus address offsets */
48 #define SMBHSTSTS (0 + piix4_smba)
49 #define SMBHSLVSTS (1 + piix4_smba)
50 #define SMBHSTCNT (2 + piix4_smba)
51 #define SMBHSTCMD (3 + piix4_smba)
52 #define SMBHSTADD (4 + piix4_smba)
53 #define SMBHSTDAT0 (5 + piix4_smba)
54 #define SMBHSTDAT1 (6 + piix4_smba)
55 #define SMBBLKDAT (7 + piix4_smba)
56 #define SMBSLVCNT (8 + piix4_smba)
57 #define SMBSHDWCMD (9 + piix4_smba)
58 #define SMBSLVEVT (0xA + piix4_smba)
59 #define SMBSLVDAT (0xC + piix4_smba)
61 /* count for request_region */
64 /* PCI Address Constants */
66 #define SMBHSTCFG 0x0D2
68 #define SMBSHDW1 0x0D4
69 #define SMBSHDW2 0x0D5
73 #define MAX_TIMEOUT 500
77 #define PIIX4_QUICK 0x00
78 #define PIIX4_BYTE 0x04
79 #define PIIX4_BYTE_DATA 0x08
80 #define PIIX4_WORD_DATA 0x0C
81 #define PIIX4_BLOCK_DATA 0x14
83 /* insmod parameters */
85 /* If force is set to anything different from 0, we forcibly enable the
88 module_param (force, int, 0);
89 MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!");
91 /* If force_addr is set to anything different from 0, we forcibly enable
92 the PIIX4 at the given address. VERY DANGEROUS! */
93 static int force_addr;
94 module_param (force_addr, int, 0);
95 MODULE_PARM_DESC(force_addr,
96 "Forcibly enable the PIIX4 at the given address. "
97 "EXTREMELY DANGEROUS!");
99 static int srvrworks_csb5_delay;
100 static struct pci_driver piix4_driver;
102 static struct dmi_system_id __devinitdata piix4_dmi_blacklist[] = {
104 .ident = "Sapphire AM2RD790",
106 DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."),
107 DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"),
111 .ident = "DFI Lanparty UT 790FX",
113 DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."),
114 DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"),
120 /* The IBM entry is in a separate table because we only check it
121 on Intel-based systems */
122 static struct dmi_system_id __devinitdata piix4_dmi_ibm[] = {
125 .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), },
130 struct i2c_piix4_adapdata {
134 static int __devinit piix4_setup(struct pci_dev *PIIX4_dev,
135 const struct pci_device_id *id)
138 unsigned short piix4_smba;
140 if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) &&
141 (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5))
142 srvrworks_csb5_delay = 1;
144 /* On some motherboards, it was reported that accessing the SMBus
145 caused severe hardware problems */
146 if (dmi_check_system(piix4_dmi_blacklist)) {
147 dev_err(&PIIX4_dev->dev,
148 "Accessing the SMBus on this system is unsafe!\n");
152 /* Don't access SMBus on IBM systems which get corrupted eeproms */
153 if (dmi_check_system(piix4_dmi_ibm) &&
154 PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) {
155 dev_err(&PIIX4_dev->dev, "IBM system detected; this module "
156 "may corrupt your serial eeprom! Refusing to load "
161 /* Determine the address of the SMBus areas */
163 piix4_smba = force_addr & 0xfff0;
166 pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba);
167 piix4_smba &= 0xfff0;
168 if(piix4_smba == 0) {
169 dev_err(&PIIX4_dev->dev, "SMBus base address "
170 "uninitialized - upgrade BIOS or use "
171 "force_addr=0xaddr\n");
176 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
179 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
180 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
185 pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp);
187 /* If force_addr is set, we program the new address here. Just to make
188 sure, we disable the PIIX4 first. */
190 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe);
191 pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba);
192 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01);
193 dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to "
194 "new address %04x!\n", piix4_smba);
195 } else if ((temp & 1) == 0) {
197 /* This should never need to be done, but has been
198 * noted that many Dell machines have the SMBus
199 * interface on the PIIX4 disabled!? NOTE: This assumes
200 * I/O space and other allocations WERE done by the
201 * Bios! Don't complain if your hardware does weird
202 * things after enabling this. :') Check for Bios
203 * updates before resorting to this.
205 pci_write_config_byte(PIIX4_dev, SMBHSTCFG,
207 dev_printk(KERN_NOTICE, &PIIX4_dev->dev,
208 "WARNING: SMBus interface has been "
209 "FORCEFULLY ENABLED!\n");
211 dev_err(&PIIX4_dev->dev,
212 "Host SMBus controller not enabled!\n");
213 release_region(piix4_smba, SMBIOSIZE);
218 if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2))
219 dev_dbg(&PIIX4_dev->dev, "Using Interrupt 9 for SMBus.\n");
220 else if ((temp & 0x0E) == 0)
221 dev_dbg(&PIIX4_dev->dev, "Using Interrupt SMI# for SMBus.\n");
223 dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration "
224 "(or code out of date)!\n");
226 pci_read_config_byte(PIIX4_dev, SMBREV, &temp);
227 dev_info(&PIIX4_dev->dev,
228 "SMBus Host Controller at 0x%x, revision %d\n",
234 static int __devinit piix4_setup_sb800(struct pci_dev *PIIX4_dev,
235 const struct pci_device_id *id)
237 unsigned short piix4_smba;
238 unsigned short smba_idx = 0xcd6;
239 u8 smba_en_lo, smba_en_hi, i2ccfg, i2ccfg_offset = 0x10, smb_en = 0x2c;
241 /* SB800 and later SMBus does not support forcing address */
242 if (force || force_addr) {
243 dev_err(&PIIX4_dev->dev, "SMBus does not support "
244 "forcing address!\n");
248 /* Determine the address of the SMBus areas */
249 if (!request_region(smba_idx, 2, "smba_idx")) {
250 dev_err(&PIIX4_dev->dev, "SMBus base address index region "
251 "0x%x already in use!\n", smba_idx);
254 outb_p(smb_en, smba_idx);
255 smba_en_lo = inb_p(smba_idx + 1);
256 outb_p(smb_en + 1, smba_idx);
257 smba_en_hi = inb_p(smba_idx + 1);
258 release_region(smba_idx, 2);
260 if ((smba_en_lo & 1) == 0) {
261 dev_err(&PIIX4_dev->dev,
262 "Host SMBus controller not enabled!\n");
266 piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0;
267 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
270 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
271 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n",
276 /* Request the SMBus I2C bus config region */
277 if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) {
278 dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region "
279 "0x%x already in use!\n", piix4_smba + i2ccfg_offset);
280 release_region(piix4_smba, SMBIOSIZE);
283 i2ccfg = inb_p(piix4_smba + i2ccfg_offset);
284 release_region(piix4_smba + i2ccfg_offset, 1);
287 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus.\n");
289 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus.\n");
291 dev_info(&PIIX4_dev->dev,
292 "SMBus Host Controller at 0x%x, revision %d\n",
293 piix4_smba, i2ccfg >> 4);
298 static int __devinit piix4_setup_aux(struct pci_dev *PIIX4_dev,
299 const struct pci_device_id *id,
300 unsigned short base_reg_addr)
302 /* Set up auxiliary SMBus controllers found on some
303 * AMD chipsets e.g. SP5100 (SB700 derivative) */
305 unsigned short piix4_smba;
307 /* Read address of auxiliary SMBus controller */
308 pci_read_config_word(PIIX4_dev, base_reg_addr, &piix4_smba);
309 if ((piix4_smba & 1) == 0) {
310 dev_dbg(&PIIX4_dev->dev,
311 "Auxiliary SMBus controller not enabled\n");
315 piix4_smba &= 0xfff0;
316 if (piix4_smba == 0) {
317 dev_dbg(&PIIX4_dev->dev,
318 "Auxiliary SMBus base address uninitialized\n");
322 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name))
325 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) {
326 dev_err(&PIIX4_dev->dev, "Auxiliary SMBus region 0x%x "
327 "already in use!\n", piix4_smba);
331 dev_info(&PIIX4_dev->dev,
332 "Auxiliary SMBus Host Controller at 0x%x\n",
338 static int piix4_transaction(struct i2c_adapter *piix4_adapter)
340 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(piix4_adapter);
341 unsigned short piix4_smba = adapdata->smba;
346 dev_dbg(&piix4_adapter->dev, "Transaction (pre): CNT=%02x, CMD=%02x, "
347 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
348 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
351 /* Make sure the SMBus host is ready to start transmitting */
352 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
353 dev_dbg(&piix4_adapter->dev, "SMBus busy (%02x). "
354 "Resetting...\n", temp);
355 outb_p(temp, SMBHSTSTS);
356 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
357 dev_err(&piix4_adapter->dev, "Failed! (%02x)\n", temp);
360 dev_dbg(&piix4_adapter->dev, "Successful!\n");
364 /* start the transaction by setting bit 6 */
365 outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT);
367 /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */
368 if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */
373 while ((++timeout < MAX_TIMEOUT) &&
374 ((temp = inb_p(SMBHSTSTS)) & 0x01))
377 /* If the SMBus is still busy, we give up */
378 if (timeout == MAX_TIMEOUT) {
379 dev_err(&piix4_adapter->dev, "SMBus Timeout!\n");
385 dev_err(&piix4_adapter->dev, "Error: Failed bus transaction\n");
390 dev_dbg(&piix4_adapter->dev, "Bus collision! SMBus may be "
391 "locked until next hard reset. (sorry!)\n");
392 /* Clock stops and slave is stuck in mid-transmission */
397 dev_dbg(&piix4_adapter->dev, "Error: no response!\n");
400 if (inb_p(SMBHSTSTS) != 0x00)
401 outb_p(inb(SMBHSTSTS), SMBHSTSTS);
403 if ((temp = inb_p(SMBHSTSTS)) != 0x00) {
404 dev_err(&piix4_adapter->dev, "Failed reset at end of "
405 "transaction (%02x)\n", temp);
407 dev_dbg(&piix4_adapter->dev, "Transaction (post): CNT=%02x, CMD=%02x, "
408 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT),
409 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0),
414 /* Return negative errno on error. */
415 static s32 piix4_access(struct i2c_adapter * adap, u16 addr,
416 unsigned short flags, char read_write,
417 u8 command, int size, union i2c_smbus_data * data)
419 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
420 unsigned short piix4_smba = adapdata->smba;
425 case I2C_SMBUS_QUICK:
426 outb_p((addr << 1) | read_write,
431 outb_p((addr << 1) | read_write,
433 if (read_write == I2C_SMBUS_WRITE)
434 outb_p(command, SMBHSTCMD);
437 case I2C_SMBUS_BYTE_DATA:
438 outb_p((addr << 1) | read_write,
440 outb_p(command, SMBHSTCMD);
441 if (read_write == I2C_SMBUS_WRITE)
442 outb_p(data->byte, SMBHSTDAT0);
443 size = PIIX4_BYTE_DATA;
445 case I2C_SMBUS_WORD_DATA:
446 outb_p((addr << 1) | read_write,
448 outb_p(command, SMBHSTCMD);
449 if (read_write == I2C_SMBUS_WRITE) {
450 outb_p(data->word & 0xff, SMBHSTDAT0);
451 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1);
453 size = PIIX4_WORD_DATA;
455 case I2C_SMBUS_BLOCK_DATA:
456 outb_p((addr << 1) | read_write,
458 outb_p(command, SMBHSTCMD);
459 if (read_write == I2C_SMBUS_WRITE) {
460 len = data->block[0];
461 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX)
463 outb_p(len, SMBHSTDAT0);
464 i = inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
465 for (i = 1; i <= len; i++)
466 outb_p(data->block[i], SMBBLKDAT);
468 size = PIIX4_BLOCK_DATA;
471 dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
475 outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT);
477 status = piix4_transaction(adap);
481 if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK))
487 case PIIX4_BYTE_DATA:
488 data->byte = inb_p(SMBHSTDAT0);
490 case PIIX4_WORD_DATA:
491 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8);
493 case PIIX4_BLOCK_DATA:
494 data->block[0] = inb_p(SMBHSTDAT0);
495 if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX)
497 i = inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */
498 for (i = 1; i <= data->block[0]; i++)
499 data->block[i] = inb_p(SMBBLKDAT);
505 static u32 piix4_func(struct i2c_adapter *adapter)
507 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
508 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
509 I2C_FUNC_SMBUS_BLOCK_DATA;
512 static const struct i2c_algorithm smbus_algorithm = {
513 .smbus_xfer = piix4_access,
514 .functionality = piix4_func,
517 static DEFINE_PCI_DEVICE_TABLE(piix4_ids) = {
518 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) },
519 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) },
520 { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) },
521 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) },
522 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) },
523 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) },
524 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) },
525 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) },
526 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
527 PCI_DEVICE_ID_SERVERWORKS_OSB4) },
528 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
529 PCI_DEVICE_ID_SERVERWORKS_CSB5) },
530 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
531 PCI_DEVICE_ID_SERVERWORKS_CSB6) },
532 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
533 PCI_DEVICE_ID_SERVERWORKS_HT1000SB) },
534 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS,
535 PCI_DEVICE_ID_SERVERWORKS_HT1100LD) },
539 MODULE_DEVICE_TABLE (pci, piix4_ids);
541 static struct i2c_adapter *piix4_main_adapter;
542 static struct i2c_adapter *piix4_aux_adapter;
544 static int __devinit piix4_add_adapter(struct pci_dev *dev,
546 struct i2c_adapter **padap)
548 struct i2c_adapter *adap;
549 struct i2c_piix4_adapdata *adapdata;
552 adap = kzalloc(sizeof(*adap), GFP_KERNEL);
554 release_region(smba, SMBIOSIZE);
558 adap->owner = THIS_MODULE;
559 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
560 adap->algo = &smbus_algorithm;
562 adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL);
563 if (adapdata == NULL) {
565 release_region(smba, SMBIOSIZE);
569 adapdata->smba = smba;
571 /* set up the sysfs linkage to our parent device */
572 adap->dev.parent = &dev->dev;
574 snprintf(adap->name, sizeof(adap->name),
575 "SMBus PIIX4 adapter at %04x", smba);
577 i2c_set_adapdata(adap, adapdata);
579 retval = i2c_add_adapter(adap);
581 dev_err(&dev->dev, "Couldn't register adapter!\n");
584 release_region(smba, SMBIOSIZE);
592 static int __devinit piix4_probe(struct pci_dev *dev,
593 const struct pci_device_id *id)
597 if ((dev->vendor == PCI_VENDOR_ID_ATI &&
598 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
599 dev->revision >= 0x40) ||
600 dev->vendor == PCI_VENDOR_ID_AMD)
601 /* base address location etc changed in SB800 */
602 retval = piix4_setup_sb800(dev, id);
604 retval = piix4_setup(dev, id);
606 /* If no main SMBus found, give up */
610 /* Try to register main SMBus adapter, give up if we can't */
611 retval = piix4_add_adapter(dev, retval, &piix4_main_adapter);
615 /* Check for auxiliary SMBus on some AMD chipsets */
616 if (dev->vendor == PCI_VENDOR_ID_ATI &&
617 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS &&
618 dev->revision < 0x40) {
619 retval = piix4_setup_aux(dev, id, 0x58);
621 /* Try to add the aux adapter if it exists,
622 * piix4_add_adapter will clean up if this fails */
623 piix4_add_adapter(dev, retval, &piix4_aux_adapter);
630 static void __devexit piix4_adap_remove(struct i2c_adapter *adap)
632 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap);
634 if (adapdata->smba) {
635 i2c_del_adapter(adap);
636 release_region(adapdata->smba, SMBIOSIZE);
642 static void __devexit piix4_remove(struct pci_dev *dev)
644 if (piix4_main_adapter) {
645 piix4_adap_remove(piix4_main_adapter);
646 piix4_main_adapter = NULL;
649 if (piix4_aux_adapter) {
650 piix4_adap_remove(piix4_aux_adapter);
651 piix4_aux_adapter = NULL;
655 static struct pci_driver piix4_driver = {
656 .name = "piix4_smbus",
657 .id_table = piix4_ids,
658 .probe = piix4_probe,
659 .remove = __devexit_p(piix4_remove),
662 module_pci_driver(piix4_driver);
664 MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and "
665 "Philip Edelbrock <phil@netroedge.com>");
666 MODULE_DESCRIPTION("PIIX4 SMBus driver");
667 MODULE_LICENSE("GPL");