4 * I2C adapter for the PXA I2C bus access.
6 * Copyright (C) 2002 Intrinsyc Software Inc.
7 * Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License version 2 as
11 * published by the Free Software Foundation.
14 * Apr 2002: Initial version [CS]
15 * Jun 2002: Properly separated algo/adap [FB]
16 * Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
17 * Jan 2003: added limited signal handling [Kai-Uwe Bloem]
18 * Sep 2004: Major rework to ensure efficient bus handling [RMK]
19 * Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
20 * Feb 2005: Rework slave mode handling [RMK]
22 #include <linux/kernel.h>
23 #include <linux/module.h>
24 #include <linux/i2c.h>
25 #include <linux/init.h>
26 #include <linux/time.h>
27 #include <linux/sched.h>
28 #include <linux/delay.h>
29 #include <linux/errno.h>
30 #include <linux/interrupt.h>
31 #include <linux/i2c-pxa.h>
33 #include <linux/of_device.h>
34 #include <linux/platform_device.h>
35 #include <linux/err.h>
36 #include <linux/clk.h>
37 #include <linux/slab.h>
39 #include <linux/i2c/pxa-i2c.h>
43 struct pxa_reg_layout {
58 * I2C registers definitions
60 static struct pxa_reg_layout pxa_reg_layout[] = {
80 /* no isar register */
84 static const struct platform_device_id i2c_pxa_id_table[] = {
85 { "pxa2xx-i2c", REGS_PXA2XX },
86 { "pxa3xx-pwri2c", REGS_PXA3XX },
87 { "ce4100-i2c", REGS_CE4100 },
90 MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
96 #define ICR_START (1 << 0) /* start bit */
97 #define ICR_STOP (1 << 1) /* stop bit */
98 #define ICR_ACKNAK (1 << 2) /* send ACK(0) or NAK(1) */
99 #define ICR_TB (1 << 3) /* transfer byte bit */
100 #define ICR_MA (1 << 4) /* master abort */
101 #define ICR_SCLE (1 << 5) /* master clock enable */
102 #define ICR_IUE (1 << 6) /* unit enable */
103 #define ICR_GCD (1 << 7) /* general call disable */
104 #define ICR_ITEIE (1 << 8) /* enable tx interrupts */
105 #define ICR_IRFIE (1 << 9) /* enable rx interrupts */
106 #define ICR_BEIE (1 << 10) /* enable bus error ints */
107 #define ICR_SSDIE (1 << 11) /* slave STOP detected int enable */
108 #define ICR_ALDIE (1 << 12) /* enable arbitration interrupt */
109 #define ICR_SADIE (1 << 13) /* slave address detected int enable */
110 #define ICR_UR (1 << 14) /* unit reset */
111 #define ICR_FM (1 << 15) /* fast mode */
112 #define ICR_HS (1 << 16) /* High Speed mode */
113 #define ICR_GPIOEN (1 << 19) /* enable GPIO mode for SCL in HS */
115 #define ISR_RWM (1 << 0) /* read/write mode */
116 #define ISR_ACKNAK (1 << 1) /* ack/nak status */
117 #define ISR_UB (1 << 2) /* unit busy */
118 #define ISR_IBB (1 << 3) /* bus busy */
119 #define ISR_SSD (1 << 4) /* slave stop detected */
120 #define ISR_ALD (1 << 5) /* arbitration loss detected */
121 #define ISR_ITE (1 << 6) /* tx buffer empty */
122 #define ISR_IRF (1 << 7) /* rx buffer full */
123 #define ISR_GCAD (1 << 8) /* general call address detected */
124 #define ISR_SAD (1 << 9) /* slave address detected */
125 #define ISR_BED (1 << 10) /* bus error no ACK/NAK */
129 wait_queue_head_t wait;
131 unsigned int msg_num;
132 unsigned int msg_idx;
133 unsigned int msg_ptr;
134 unsigned int slave_addr;
135 unsigned int req_slave_addr;
137 struct i2c_adapter adap;
139 #ifdef CONFIG_I2C_PXA_SLAVE
140 struct i2c_slave_client *slave;
143 unsigned int irqlogidx;
147 void __iomem *reg_base;
148 void __iomem *reg_ibmr;
149 void __iomem *reg_idbr;
150 void __iomem *reg_icr;
151 void __iomem *reg_isr;
152 void __iomem *reg_isar;
154 unsigned long iobase;
155 unsigned long iosize;
158 unsigned int use_pio :1;
159 unsigned int fast_mode :1;
160 unsigned int high_mode:1;
161 unsigned char master_code;
166 #define _IBMR(i2c) ((i2c)->reg_ibmr)
167 #define _IDBR(i2c) ((i2c)->reg_idbr)
168 #define _ICR(i2c) ((i2c)->reg_icr)
169 #define _ISR(i2c) ((i2c)->reg_isr)
170 #define _ISAR(i2c) ((i2c)->reg_isar)
173 * I2C Slave mode address
175 #define I2C_PXA_SLAVE_ADDR 0x1
184 #define PXA_BIT(m, s, u) { .mask = m, .set = s, .unset = u }
187 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
189 printk("%s %08x: ", prefix, val);
191 const char *str = val & bits->mask ? bits->set : bits->unset;
198 static const struct bits isr_bits[] = {
199 PXA_BIT(ISR_RWM, "RX", "TX"),
200 PXA_BIT(ISR_ACKNAK, "NAK", "ACK"),
201 PXA_BIT(ISR_UB, "Bsy", "Rdy"),
202 PXA_BIT(ISR_IBB, "BusBsy", "BusRdy"),
203 PXA_BIT(ISR_SSD, "SlaveStop", NULL),
204 PXA_BIT(ISR_ALD, "ALD", NULL),
205 PXA_BIT(ISR_ITE, "TxEmpty", NULL),
206 PXA_BIT(ISR_IRF, "RxFull", NULL),
207 PXA_BIT(ISR_GCAD, "GenCall", NULL),
208 PXA_BIT(ISR_SAD, "SlaveAddr", NULL),
209 PXA_BIT(ISR_BED, "BusErr", NULL),
212 static void decode_ISR(unsigned int val)
214 decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
218 static const struct bits icr_bits[] = {
219 PXA_BIT(ICR_START, "START", NULL),
220 PXA_BIT(ICR_STOP, "STOP", NULL),
221 PXA_BIT(ICR_ACKNAK, "ACKNAK", NULL),
222 PXA_BIT(ICR_TB, "TB", NULL),
223 PXA_BIT(ICR_MA, "MA", NULL),
224 PXA_BIT(ICR_SCLE, "SCLE", "scle"),
225 PXA_BIT(ICR_IUE, "IUE", "iue"),
226 PXA_BIT(ICR_GCD, "GCD", NULL),
227 PXA_BIT(ICR_ITEIE, "ITEIE", NULL),
228 PXA_BIT(ICR_IRFIE, "IRFIE", NULL),
229 PXA_BIT(ICR_BEIE, "BEIE", NULL),
230 PXA_BIT(ICR_SSDIE, "SSDIE", NULL),
231 PXA_BIT(ICR_ALDIE, "ALDIE", NULL),
232 PXA_BIT(ICR_SADIE, "SADIE", NULL),
233 PXA_BIT(ICR_UR, "UR", "ur"),
236 #ifdef CONFIG_I2C_PXA_SLAVE
237 static void decode_ICR(unsigned int val)
239 decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
244 static unsigned int i2c_debug = DEBUG;
246 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
248 dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
249 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
252 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
254 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
257 struct device *dev = &i2c->adap.dev;
259 dev_err(dev, "slave_0x%x error: %s\n",
260 i2c->req_slave_addr >> 1, why);
261 dev_err(dev, "msg_num: %d msg_idx: %d msg_ptr: %d\n",
262 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
263 dev_err(dev, "IBMR: %08x IDBR: %08x ICR: %08x ISR: %08x\n",
264 readl(_IBMR(i2c)), readl(_IDBR(i2c)), readl(_ICR(i2c)),
266 dev_dbg(dev, "log: ");
267 for (i = 0; i < i2c->irqlogidx; i++)
268 pr_debug("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
273 #else /* ifdef DEBUG */
277 #define show_state(i2c) do { } while (0)
278 #define decode_ISR(val) do { } while (0)
279 #define decode_ICR(val) do { } while (0)
280 #define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0)
282 #endif /* ifdef DEBUG / else */
284 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
285 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id);
287 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
289 return !(readl(_ICR(i2c)) & ICR_SCLE);
292 static void i2c_pxa_abort(struct pxa_i2c *i2c)
296 if (i2c_pxa_is_slavemode(i2c)) {
297 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
301 while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) {
302 unsigned long icr = readl(_ICR(i2c));
305 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
307 writel(icr, _ICR(i2c));
315 writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
319 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
321 int timeout = DEF_TIMEOUT;
323 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
324 if ((readl(_ISR(i2c)) & ISR_SAD) != 0)
334 return timeout < 0 ? I2C_RETRY : 0;
337 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
339 unsigned long timeout = jiffies + HZ*4;
341 while (time_before(jiffies, timeout)) {
343 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
344 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
346 if (readl(_ISR(i2c)) & ISR_SAD) {
348 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
352 /* wait for unit and bus being not busy, and we also do a
353 * quick check of the i2c lines themselves to ensure they've
356 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) {
358 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
366 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
371 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
374 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
376 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
377 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
378 if (!i2c_pxa_wait_master(i2c)) {
379 dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
384 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
388 #ifdef CONFIG_I2C_PXA_SLAVE
389 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
391 unsigned long timeout = jiffies + HZ*1;
397 while (time_before(jiffies, timeout)) {
399 dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
400 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
402 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
403 (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
404 (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
406 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
414 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
419 * clear the hold on the bus, and take of anything else
420 * that has been configured
422 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
427 udelay(100); /* simple delay */
429 /* we need to wait for the stop condition to end */
431 /* if we where in stop, then clear... */
432 if (readl(_ICR(i2c)) & ICR_STOP) {
434 writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
437 if (!i2c_pxa_wait_slave(i2c)) {
438 dev_err(&i2c->adap.dev, "%s: wait timedout\n",
444 writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
445 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
448 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
449 decode_ICR(readl(_ICR(i2c)));
453 #define i2c_pxa_set_slave(i2c, err) do { } while (0)
456 static void i2c_pxa_reset(struct pxa_i2c *i2c)
458 pr_debug("Resetting I2C Controller Unit\n");
460 /* abort any transfer currently under way */
463 /* reset according to 9.8 */
464 writel(ICR_UR, _ICR(i2c));
465 writel(I2C_ISR_INIT, _ISR(i2c));
466 writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
468 if (i2c->reg_isar && IS_ENABLED(CONFIG_I2C_PXA_SLAVE))
469 writel(i2c->slave_addr, _ISAR(i2c));
471 /* set control register values */
472 writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c));
473 writel(readl(_ICR(i2c)) | (i2c->high_mode ? ICR_HS : 0), _ICR(i2c));
475 #ifdef CONFIG_I2C_PXA_SLAVE
476 dev_info(&i2c->adap.dev, "Enabling slave mode\n");
477 writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
480 i2c_pxa_set_slave(i2c, 0);
483 writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
488 #ifdef CONFIG_I2C_PXA_SLAVE
493 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
496 /* what should we do here? */
500 if (i2c->slave != NULL)
501 ret = i2c->slave->read(i2c->slave->data);
503 writel(ret, _IDBR(i2c));
504 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c)); /* allow next byte */
508 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
510 unsigned int byte = readl(_IDBR(i2c));
512 if (i2c->slave != NULL)
513 i2c->slave->write(i2c->slave->data, byte);
515 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
518 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
523 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
524 (isr & ISR_RWM) ? 'r' : 't');
526 if (i2c->slave != NULL)
527 i2c->slave->event(i2c->slave->data,
528 (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
531 * slave could interrupt in the middle of us generating a
532 * start condition... if this happens, we'd better back off
533 * and stop holding the poor thing up
535 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
536 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
541 if ((readl(_IBMR(i2c)) & 2) == 2)
547 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
552 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
555 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
558 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
560 if (i2c->slave != NULL)
561 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
564 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
567 * If we have a master-mode message waiting,
568 * kick it off now that the slave has completed.
571 i2c_pxa_master_complete(i2c, I2C_RETRY);
574 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
577 /* what should we do here? */
579 writel(0, _IDBR(i2c));
580 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
584 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
586 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
589 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
594 * slave could interrupt in the middle of us generating a
595 * start condition... if this happens, we'd better back off
596 * and stop holding the poor thing up
598 writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
599 writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
604 if ((readl(_IBMR(i2c)) & 2) == 2)
610 dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
615 writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
618 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
621 i2c_pxa_master_complete(i2c, I2C_RETRY);
626 * PXA I2C Master mode
629 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
631 unsigned int addr = (msg->addr & 0x7f) << 1;
633 if (msg->flags & I2C_M_RD)
639 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
644 * Step 1: target slave address into IDBR
646 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
647 i2c->req_slave_addr = i2c_pxa_addr_byte(i2c->msg);
650 * Step 2: initiate the write.
652 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
653 writel(icr | ICR_START | ICR_TB, _ICR(i2c));
656 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
661 * Clear the STOP and ACK flags
663 icr = readl(_ICR(i2c));
664 icr &= ~(ICR_STOP | ICR_ACKNAK);
665 writel(icr, _ICR(i2c));
668 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
670 /* make timeout the same as for interrupt based functions */
671 long timeout = 2 * DEF_TIMEOUT;
674 * Wait for the bus to become free.
676 while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
683 dev_err(&i2c->adap.dev,
684 "i2c_pxa: timeout waiting for bus free\n");
691 writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
697 * PXA I2C send master code
698 * 1. Load master code to IDBR and send it.
699 * Note for HS mode, set ICR [GPIOEN].
700 * 2. Wait until win arbitration.
702 static int i2c_pxa_send_mastercode(struct pxa_i2c *i2c)
707 spin_lock_irq(&i2c->lock);
708 i2c->highmode_enter = true;
709 writel(i2c->master_code, _IDBR(i2c));
711 icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
712 icr |= ICR_GPIOEN | ICR_START | ICR_TB | ICR_ITEIE;
713 writel(icr, _ICR(i2c));
715 spin_unlock_irq(&i2c->lock);
716 timeout = wait_event_timeout(i2c->wait,
717 i2c->highmode_enter == false, HZ * 1);
719 i2c->highmode_enter = false;
721 return (timeout == 0) ? I2C_RETRY : 0;
724 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
725 struct i2c_msg *msg, int num)
727 unsigned long timeout = 500000; /* 5 seconds */
730 ret = i2c_pxa_pio_set_master(i2c);
740 i2c_pxa_start_message(i2c);
742 while (i2c->msg_num > 0 && --timeout) {
743 i2c_pxa_handler(0, i2c);
747 i2c_pxa_stop_message(i2c);
750 * We place the return code in i2c->msg_idx.
756 i2c_pxa_scream_blue_murder(i2c, "timeout");
764 * We are protected by the adapter bus mutex.
766 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
772 * Wait for the bus to become free.
774 ret = i2c_pxa_wait_bus_not_busy(i2c);
776 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
783 ret = i2c_pxa_set_master(i2c);
785 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
789 if (i2c->high_mode) {
790 ret = i2c_pxa_send_mastercode(i2c);
792 dev_err(&i2c->adap.dev, "i2c_pxa_send_mastercode timeout\n");
797 spin_lock_irq(&i2c->lock);
805 i2c_pxa_start_message(i2c);
807 spin_unlock_irq(&i2c->lock);
810 * The rest of the processing occurs in the interrupt handler.
812 timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
813 i2c_pxa_stop_message(i2c);
816 * We place the return code in i2c->msg_idx.
820 if (!timeout && i2c->msg_num) {
821 i2c_pxa_scream_blue_murder(i2c, "timeout");
829 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
830 struct i2c_msg msgs[], int num)
832 struct pxa_i2c *i2c = adap->algo_data;
835 /* If the I2C controller is disabled we need to reset it
836 (probably due to a suspend/resume destroying state). We do
837 this here as we can then avoid worrying about resuming the
838 controller before its users. */
839 if (!(readl(_ICR(i2c)) & ICR_IUE))
842 for (i = adap->retries; i >= 0; i--) {
843 ret = i2c_pxa_do_pio_xfer(i2c, msgs, num);
844 if (ret != I2C_RETRY)
848 dev_dbg(&adap->dev, "Retrying transmission\n");
851 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
854 i2c_pxa_set_slave(i2c, ret);
859 * i2c_pxa_master_complete - complete the message and wake up.
861 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
873 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
875 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
879 * If ISR_ALD is set, we lost arbitration.
883 * Do we need to do anything here? The PXA docs
884 * are vague about what happens.
886 i2c_pxa_scream_blue_murder(i2c, "ALD set");
889 * We ignore this error. We seem to see spurious ALDs
890 * for seemingly no reason. If we handle them as I think
891 * they should, we end up causing an I2C error, which
892 * is painful for some systems.
897 if ((isr & ISR_BED) &&
898 (!((i2c->msg->flags & I2C_M_IGNORE_NAK) &&
899 (isr & ISR_ACKNAK)))) {
903 * I2C bus error - either the device NAK'd us, or
904 * something more serious happened. If we were NAK'd
905 * on the initial address phase, we can retry.
907 if (isr & ISR_ACKNAK) {
908 if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
913 i2c_pxa_master_complete(i2c, ret);
914 } else if (isr & ISR_RWM) {
916 * Read mode. We have just sent the address byte, and
917 * now we must initiate the transfer.
919 if (i2c->msg_ptr == i2c->msg->len - 1 &&
920 i2c->msg_idx == i2c->msg_num - 1)
921 icr |= ICR_STOP | ICR_ACKNAK;
923 icr |= ICR_ALDIE | ICR_TB;
924 } else if (i2c->msg_ptr < i2c->msg->len) {
926 * Write mode. Write the next data byte.
928 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
930 icr |= ICR_ALDIE | ICR_TB;
933 * If this is the last byte of the last message or last byte
934 * of any message with I2C_M_STOP (e.g. SCCB), send a STOP.
936 if ((i2c->msg_ptr == i2c->msg->len) &&
937 ((i2c->msg->flags & I2C_M_STOP) ||
938 (i2c->msg_idx == i2c->msg_num - 1)))
941 } else if (i2c->msg_idx < i2c->msg_num - 1) {
943 * Next segment of the message.
950 * If we aren't doing a repeated start and address,
951 * go back and try to send the next byte. Note that
952 * we do not support switching the R/W direction here.
954 if (i2c->msg->flags & I2C_M_NOSTART)
958 * Write the next address.
960 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
961 i2c->req_slave_addr = i2c_pxa_addr_byte(i2c->msg);
964 * And trigger a repeated start, and send the byte.
967 icr |= ICR_START | ICR_TB;
969 if (i2c->msg->len == 0) {
971 * Device probes have a message length of zero
972 * and need the bus to be reset before it can
977 i2c_pxa_master_complete(i2c, 0);
980 i2c->icrlog[i2c->irqlogidx-1] = icr;
982 writel(icr, _ICR(i2c));
986 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
988 u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
993 i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
995 if (i2c->msg_ptr < i2c->msg->len) {
997 * If this is the last byte of the last
998 * message, send a STOP.
1000 if (i2c->msg_ptr == i2c->msg->len - 1)
1001 icr |= ICR_STOP | ICR_ACKNAK;
1003 icr |= ICR_ALDIE | ICR_TB;
1005 i2c_pxa_master_complete(i2c, 0);
1008 i2c->icrlog[i2c->irqlogidx-1] = icr;
1010 writel(icr, _ICR(i2c));
1013 #define VALID_INT_SOURCE (ISR_SSD | ISR_ALD | ISR_ITE | ISR_IRF | \
1015 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
1017 struct pxa_i2c *i2c = dev_id;
1018 u32 isr = readl(_ISR(i2c));
1020 if (!(isr & VALID_INT_SOURCE))
1023 if (i2c_debug > 2 && 0) {
1024 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
1025 __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
1029 if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
1030 i2c->isrlog[i2c->irqlogidx++] = isr;
1035 * Always clear all pending IRQs.
1037 writel(isr & VALID_INT_SOURCE, _ISR(i2c));
1040 i2c_pxa_slave_start(i2c, isr);
1042 i2c_pxa_slave_stop(i2c);
1044 if (i2c_pxa_is_slavemode(i2c)) {
1046 i2c_pxa_slave_txempty(i2c, isr);
1048 i2c_pxa_slave_rxfull(i2c, isr);
1049 } else if (i2c->msg && (!i2c->highmode_enter)) {
1051 i2c_pxa_irq_txempty(i2c, isr);
1053 i2c_pxa_irq_rxfull(i2c, isr);
1054 } else if ((isr & ISR_ITE) && i2c->highmode_enter) {
1055 i2c->highmode_enter = false;
1056 wake_up(&i2c->wait);
1058 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
1065 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
1067 struct pxa_i2c *i2c = adap->algo_data;
1070 for (i = adap->retries; i >= 0; i--) {
1071 ret = i2c_pxa_do_xfer(i2c, msgs, num);
1072 if (ret != I2C_RETRY)
1076 dev_dbg(&adap->dev, "Retrying transmission\n");
1079 i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
1082 i2c_pxa_set_slave(i2c, ret);
1086 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
1088 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
1089 I2C_FUNC_PROTOCOL_MANGLING | I2C_FUNC_NOSTART;
1092 static const struct i2c_algorithm i2c_pxa_algorithm = {
1093 .master_xfer = i2c_pxa_xfer,
1094 .functionality = i2c_pxa_functionality,
1097 static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
1098 .master_xfer = i2c_pxa_pio_xfer,
1099 .functionality = i2c_pxa_functionality,
1102 static const struct of_device_id i2c_pxa_dt_ids[] = {
1103 { .compatible = "mrvl,pxa-i2c", .data = (void *)REGS_PXA2XX },
1104 { .compatible = "mrvl,pwri2c", .data = (void *)REGS_PXA3XX },
1105 { .compatible = "mrvl,mmp-twsi", .data = (void *)REGS_PXA2XX },
1108 MODULE_DEVICE_TABLE(of, i2c_pxa_dt_ids);
1110 static int i2c_pxa_probe_dt(struct platform_device *pdev, struct pxa_i2c *i2c,
1111 enum pxa_i2c_types *i2c_types)
1113 struct device_node *np = pdev->dev.of_node;
1114 const struct of_device_id *of_id =
1115 of_match_device(i2c_pxa_dt_ids, &pdev->dev);
1120 /* For device tree we always use the dynamic or alias-assigned ID */
1123 if (of_get_property(np, "mrvl,i2c-polling", NULL))
1125 if (of_get_property(np, "mrvl,i2c-fast-mode", NULL))
1128 *i2c_types = (enum pxa_i2c_types)(of_id->data);
1133 static int i2c_pxa_probe_pdata(struct platform_device *pdev,
1134 struct pxa_i2c *i2c,
1135 enum pxa_i2c_types *i2c_types)
1137 struct i2c_pxa_platform_data *plat = dev_get_platdata(&pdev->dev);
1138 const struct platform_device_id *id = platform_get_device_id(pdev);
1140 *i2c_types = id->driver_data;
1142 i2c->use_pio = plat->use_pio;
1143 i2c->fast_mode = plat->fast_mode;
1144 i2c->high_mode = plat->high_mode;
1145 i2c->master_code = plat->master_code;
1146 if (!i2c->master_code)
1147 i2c->master_code = 0xe;
1148 i2c->rate = plat->rate;
1153 static int i2c_pxa_probe(struct platform_device *dev)
1155 struct i2c_pxa_platform_data *plat = dev_get_platdata(&dev->dev);
1156 enum pxa_i2c_types i2c_type;
1157 struct pxa_i2c *i2c;
1158 struct resource *res = NULL;
1161 i2c = devm_kzalloc(&dev->dev, sizeof(struct pxa_i2c), GFP_KERNEL);
1165 res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1166 i2c->reg_base = devm_ioremap_resource(&dev->dev, res);
1167 if (IS_ERR(i2c->reg_base))
1168 return PTR_ERR(i2c->reg_base);
1170 irq = platform_get_irq(dev, 0);
1172 dev_err(&dev->dev, "no irq resource: %d\n", irq);
1176 /* Default adapter num to device id; i2c_pxa_probe_dt can override. */
1177 i2c->adap.nr = dev->id;
1179 ret = i2c_pxa_probe_dt(dev, i2c, &i2c_type);
1181 ret = i2c_pxa_probe_pdata(dev, i2c, &i2c_type);
1185 i2c->adap.owner = THIS_MODULE;
1186 i2c->adap.retries = 5;
1188 spin_lock_init(&i2c->lock);
1189 init_waitqueue_head(&i2c->wait);
1191 strlcpy(i2c->adap.name, "pxa_i2c-i2c", sizeof(i2c->adap.name));
1193 i2c->clk = devm_clk_get(&dev->dev, NULL);
1194 if (IS_ERR(i2c->clk)) {
1195 dev_err(&dev->dev, "failed to get the clk: %ld\n", PTR_ERR(i2c->clk));
1196 return PTR_ERR(i2c->clk);
1199 i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr;
1200 i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr;
1201 i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr;
1202 i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr;
1203 if (i2c_type != REGS_CE4100)
1204 i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar;
1206 i2c->iobase = res->start;
1207 i2c->iosize = resource_size(res);
1211 i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1212 i2c->highmode_enter = false;
1215 #ifdef CONFIG_I2C_PXA_SLAVE
1216 i2c->slave_addr = plat->slave_addr;
1217 i2c->slave = plat->slave;
1219 i2c->adap.class = plat->class;
1222 if (i2c->high_mode) {
1224 clk_set_rate(i2c->clk, i2c->rate);
1225 pr_info("i2c: <%s> set rate to %ld\n",
1226 i2c->adap.name, clk_get_rate(i2c->clk));
1228 pr_warn("i2c: <%s> clock rate not set\n",
1232 clk_prepare_enable(i2c->clk);
1235 i2c->adap.algo = &i2c_pxa_pio_algorithm;
1237 i2c->adap.algo = &i2c_pxa_algorithm;
1238 ret = devm_request_irq(&dev->dev, irq, i2c_pxa_handler,
1239 IRQF_SHARED | IRQF_NO_SUSPEND,
1240 dev_name(&dev->dev), i2c);
1242 dev_err(&dev->dev, "failed to request irq: %d\n", ret);
1249 i2c->adap.algo_data = i2c;
1250 i2c->adap.dev.parent = &dev->dev;
1252 i2c->adap.dev.of_node = dev->dev.of_node;
1255 ret = i2c_add_numbered_adapter(&i2c->adap);
1257 dev_err(&dev->dev, "failed to add bus: %d\n", ret);
1261 platform_set_drvdata(dev, i2c);
1263 #ifdef CONFIG_I2C_PXA_SLAVE
1264 dev_info(&i2c->adap.dev, " PXA I2C adapter, slave address %d\n",
1267 dev_info(&i2c->adap.dev, " PXA I2C adapter\n");
1272 clk_disable_unprepare(i2c->clk);
1276 static int i2c_pxa_remove(struct platform_device *dev)
1278 struct pxa_i2c *i2c = platform_get_drvdata(dev);
1280 i2c_del_adapter(&i2c->adap);
1282 clk_disable_unprepare(i2c->clk);
1288 static int i2c_pxa_suspend_noirq(struct device *dev)
1290 struct platform_device *pdev = to_platform_device(dev);
1291 struct pxa_i2c *i2c = platform_get_drvdata(pdev);
1293 clk_disable(i2c->clk);
1298 static int i2c_pxa_resume_noirq(struct device *dev)
1300 struct platform_device *pdev = to_platform_device(dev);
1301 struct pxa_i2c *i2c = platform_get_drvdata(pdev);
1303 clk_enable(i2c->clk);
1309 static const struct dev_pm_ops i2c_pxa_dev_pm_ops = {
1310 .suspend_noirq = i2c_pxa_suspend_noirq,
1311 .resume_noirq = i2c_pxa_resume_noirq,
1314 #define I2C_PXA_DEV_PM_OPS (&i2c_pxa_dev_pm_ops)
1316 #define I2C_PXA_DEV_PM_OPS NULL
1319 static struct platform_driver i2c_pxa_driver = {
1320 .probe = i2c_pxa_probe,
1321 .remove = i2c_pxa_remove,
1323 .name = "pxa2xx-i2c",
1324 .pm = I2C_PXA_DEV_PM_OPS,
1325 .of_match_table = i2c_pxa_dt_ids,
1327 .id_table = i2c_pxa_id_table,
1330 static int __init i2c_adap_pxa_init(void)
1332 return platform_driver_register(&i2c_pxa_driver);
1335 static void __exit i2c_adap_pxa_exit(void)
1337 platform_driver_unregister(&i2c_pxa_driver);
1340 MODULE_LICENSE("GPL");
1341 MODULE_ALIAS("platform:pxa2xx-i2c");
1343 subsys_initcall(i2c_adap_pxa_init);
1344 module_exit(i2c_adap_pxa_exit);