drivers/i2c/busses/i2c-pxa.c

   1 /*
   2  *  i2c_adap_pxa.c
   3  *
   4  *  I2C adapter for the PXA I2C bus access.
   5  *
   6  *  Copyright (C) 2002 Intrinsyc Software Inc.
   7  *  Copyright (C) 2004-2005 Deep Blue Solutions Ltd.
   8  *
   9  *  This program is free software; you can redistribute it and/or modify
  10  *  it under the terms of the GNU General Public License version 2 as
  11  *  published by the Free Software Foundation.
  12  *
  13  *  History:
  14  *    Apr 2002: Initial version [CS]
  15  *    Jun 2002: Properly separated algo/adap [FB]
  16  *    Jan 2003: Fixed several bugs concerning interrupt handling [Kai-Uwe Bloem]
  17  *    Jan 2003: added limited signal handling [Kai-Uwe Bloem]
  18  *    Sep 2004: Major rework to ensure efficient bus handling [RMK]
  19  *    Dec 2004: Added support for PXA27x and slave device probing [Liam Girdwood]
  20  *    Feb 2005: Rework slave mode handling [RMK]
  21  */
  22 #include <linux/kernel.h>
  23 #include <linux/module.h>
  24 #include <linux/i2c.h>
  25 #include <linux/init.h>
  26 #include <linux/time.h>
  27 #include <linux/sched.h>
  28 #include <linux/delay.h>
  29 #include <linux/errno.h>
  30 #include <linux/interrupt.h>
  31 #include <linux/i2c-pxa.h>
  32 #include <linux/platform_device.h>
  33 #include <linux/err.h>
  34 #include <linux/clk.h>
  35 #include <linux/slab.h>
  36 #include <linux/io.h>
  37 #include <linux/i2c/pxa-i2c.h>
  38
  39 #include <asm/irq.h>
  40
  41 struct pxa_reg_layout {
  42         u32 ibmr;
  43         u32 idbr;
  44         u32 icr;
  45         u32 isr;
  46         u32 isar;
  47 };
  48
  49 enum pxa_i2c_types {
  50         REGS_PXA2XX,
  51         REGS_PXA3XX,
  52 };
  53
  54 /*
  55  * I2C registers definitions
  56  */
  57 static struct pxa_reg_layout pxa_reg_layout[] = {
  58         [REGS_PXA2XX] = {
  59                 .ibmr = 0x00,
  60                 .idbr = 0x10,
  61                 .icr =  0x20,
  62                 .isr =  0x30,
  63                 .isar = 0x40,
  64         },
  65         [REGS_PXA3XX] = {
  66                 .ibmr = 0x00,
  67                 .idbr = 0x08,
  68                 .icr =  0x10,
  69                 .isr =  0x18,
  70                 .isar = 0x20,
  71         },
  72 };
  73
  74 static const struct platform_device_id i2c_pxa_id_table[] = {
  75         { "pxa2xx-i2c",         REGS_PXA2XX },
  76         { "pxa3xx-pwri2c",      REGS_PXA3XX },
  77         { },
  78 };
  79 MODULE_DEVICE_TABLE(platform, i2c_pxa_id_table);
  80
  81 /*
  82  * I2C bit definitions
  83  */
  84
  85 #define ICR_START       (1 << 0)           /* start bit */
  86 #define ICR_STOP        (1 << 1)           /* stop bit */
  87 #define ICR_ACKNAK      (1 << 2)           /* send ACK(0) or NAK(1) */
  88 #define ICR_TB          (1 << 3)           /* transfer byte bit */
  89 #define ICR_MA          (1 << 4)           /* master abort */
  90 #define ICR_SCLE        (1 << 5)           /* master clock enable */
  91 #define ICR_IUE         (1 << 6)           /* unit enable */
  92 #define ICR_GCD         (1 << 7)           /* general call disable */
  93 #define ICR_ITEIE       (1 << 8)           /* enable tx interrupts */
  94 #define ICR_IRFIE       (1 << 9)           /* enable rx interrupts */
  95 #define ICR_BEIE        (1 << 10)          /* enable bus error ints */
  96 #define ICR_SSDIE       (1 << 11)          /* slave STOP detected int enable */
  97 #define ICR_ALDIE       (1 << 12)          /* enable arbitration interrupt */
  98 #define ICR_SADIE       (1 << 13)          /* slave address detected int enable */
  99 #define ICR_UR          (1 << 14)          /* unit reset */
 100 #define ICR_FM          (1 << 15)          /* fast mode */
 101
 102 #define ISR_RWM         (1 << 0)           /* read/write mode */
 103 #define ISR_ACKNAK      (1 << 1)           /* ack/nak status */
 104 #define ISR_UB          (1 << 2)           /* unit busy */
 105 #define ISR_IBB         (1 << 3)           /* bus busy */
 106 #define ISR_SSD         (1 << 4)           /* slave stop detected */
 107 #define ISR_ALD         (1 << 5)           /* arbitration loss detected */
 108 #define ISR_ITE         (1 << 6)           /* tx buffer empty */
 109 #define ISR_IRF         (1 << 7)           /* rx buffer full */
 110 #define ISR_GCAD        (1 << 8)           /* general call address detected */
 111 #define ISR_SAD         (1 << 9)           /* slave address detected */
 112 #define ISR_BED         (1 << 10)          /* bus error no ACK/NAK */
 113
 114 struct pxa_i2c {
 115         spinlock_t              lock;
 116         wait_queue_head_t       wait;
 117         struct i2c_msg          *msg;
 118         unsigned int            msg_num;
 119         unsigned int            msg_idx;
 120         unsigned int            msg_ptr;
 121         unsigned int            slave_addr;
 122
 123         struct i2c_adapter      adap;
 124         struct clk              *clk;
 125 #ifdef CONFIG_I2C_PXA_SLAVE
 126         struct i2c_slave_client *slave;
 127 #endif
 128
 129         unsigned int            irqlogidx;
 130         u32                     isrlog[32];
 131         u32                     icrlog[32];
 132
 133         void __iomem            *reg_base;
 134         void __iomem            *reg_ibmr;
 135         void __iomem            *reg_idbr;
 136         void __iomem            *reg_icr;
 137         void __iomem            *reg_isr;
 138         void __iomem            *reg_isar;
 139
 140         unsigned long           iobase;
 141         unsigned long           iosize;
 142
 143         int                     irq;
 144         unsigned int            use_pio :1;
 145         unsigned int            fast_mode :1;
 146 };
 147
 148 #define _IBMR(i2c)      ((i2c)->reg_ibmr)
 149 #define _IDBR(i2c)      ((i2c)->reg_idbr)
 150 #define _ICR(i2c)       ((i2c)->reg_icr)
 151 #define _ISR(i2c)       ((i2c)->reg_isr)
 152 #define _ISAR(i2c)      ((i2c)->reg_isar)
 153
 154 /*
 155  * I2C Slave mode address
 156  */
 157 #define I2C_PXA_SLAVE_ADDR      0x1
 158
 159 #ifdef DEBUG
 160
 161 struct bits {
 162         u32     mask;
 163         const char *set;
 164         const char *unset;
 165 };
 166 #define PXA_BIT(m, s, u)        { .mask = m, .set = s, .unset = u }
 167
 168 static inline void
 169 decode_bits(const char *prefix, const struct bits *bits, int num, u32 val)
 170 {
 171         printk("%s %08x: ", prefix, val);
 172         while (num--) {
 173                 const char *str = val & bits->mask ? bits->set : bits->unset;
 174                 if (str)
 175                         printk("%s ", str);
 176                 bits++;
 177         }
 178 }
 179
 180 static const struct bits isr_bits[] = {
 181         PXA_BIT(ISR_RWM,        "RX",           "TX"),
 182         PXA_BIT(ISR_ACKNAK,     "NAK",          "ACK"),
 183         PXA_BIT(ISR_UB,         "Bsy",          "Rdy"),
 184         PXA_BIT(ISR_IBB,        "BusBsy",       "BusRdy"),
 185         PXA_BIT(ISR_SSD,        "SlaveStop",    NULL),
 186         PXA_BIT(ISR_ALD,        "ALD",          NULL),
 187         PXA_BIT(ISR_ITE,        "TxEmpty",      NULL),
 188         PXA_BIT(ISR_IRF,        "RxFull",       NULL),
 189         PXA_BIT(ISR_GCAD,       "GenCall",      NULL),
 190         PXA_BIT(ISR_SAD,        "SlaveAddr",    NULL),
 191         PXA_BIT(ISR_BED,        "BusErr",       NULL),
 192 };
 193
 194 static void decode_ISR(unsigned int val)
 195 {
 196         decode_bits(KERN_DEBUG "ISR", isr_bits, ARRAY_SIZE(isr_bits), val);
 197         printk("\n");
 198 }
 199
 200 static const struct bits icr_bits[] = {
 201         PXA_BIT(ICR_START,  "START",    NULL),
 202         PXA_BIT(ICR_STOP,   "STOP",     NULL),
 203         PXA_BIT(ICR_ACKNAK, "ACKNAK",   NULL),
 204         PXA_BIT(ICR_TB,     "TB",       NULL),
 205         PXA_BIT(ICR_MA,     "MA",       NULL),
 206         PXA_BIT(ICR_SCLE,   "SCLE",     "scle"),
 207         PXA_BIT(ICR_IUE,    "IUE",      "iue"),
 208         PXA_BIT(ICR_GCD,    "GCD",      NULL),
 209         PXA_BIT(ICR_ITEIE,  "ITEIE",    NULL),
 210         PXA_BIT(ICR_IRFIE,  "IRFIE",    NULL),
 211         PXA_BIT(ICR_BEIE,   "BEIE",     NULL),
 212         PXA_BIT(ICR_SSDIE,  "SSDIE",    NULL),
 213         PXA_BIT(ICR_ALDIE,  "ALDIE",    NULL),
 214         PXA_BIT(ICR_SADIE,  "SADIE",    NULL),
 215         PXA_BIT(ICR_UR,     "UR",               "ur"),
 216 };
 217
 218 #ifdef CONFIG_I2C_PXA_SLAVE
 219 static void decode_ICR(unsigned int val)
 220 {
 221         decode_bits(KERN_DEBUG "ICR", icr_bits, ARRAY_SIZE(icr_bits), val);
 222         printk("\n");
 223 }
 224 #endif
 225
 226 static unsigned int i2c_debug = DEBUG;
 227
 228 static void i2c_pxa_show_state(struct pxa_i2c *i2c, int lno, const char *fname)
 229 {
 230         dev_dbg(&i2c->adap.dev, "state:%s:%d: ISR=%08x, ICR=%08x, IBMR=%02x\n", fname, lno,
 231                 readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 232 }
 233
 234 #define show_state(i2c) i2c_pxa_show_state(i2c, __LINE__, __func__)
 235
 236 static void i2c_pxa_scream_blue_murder(struct pxa_i2c *i2c, const char *why)
 237 {
 238         unsigned int i;
 239         printk(KERN_ERR "i2c: error: %s\n", why);
 240         printk(KERN_ERR "i2c: msg_num: %d msg_idx: %d msg_ptr: %d\n",
 241                 i2c->msg_num, i2c->msg_idx, i2c->msg_ptr);
 242         printk(KERN_ERR "i2c: ICR: %08x ISR: %08x\n",
 243                readl(_ICR(i2c)), readl(_ISR(i2c)));
 244         printk(KERN_DEBUG "i2c: log: ");
 245         for (i = 0; i < i2c->irqlogidx; i++)
 246                 printk("[%08x:%08x] ", i2c->isrlog[i], i2c->icrlog[i]);
 247         printk("\n");
 248 }
 249
 250 #else /* ifdef DEBUG */
 251
 252 #define i2c_debug       0
 253
 254 #define show_state(i2c) do { } while (0)
 255 #define decode_ISR(val) do { } while (0)
 256 #define decode_ICR(val) do { } while (0)
 257 #define i2c_pxa_scream_blue_murder(i2c, why) do { } while (0)
 258
 259 #endif /* ifdef DEBUG / else */
 260
 261 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret);
 262 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id);
 263
 264 static inline int i2c_pxa_is_slavemode(struct pxa_i2c *i2c)
 265 {
 266         return !(readl(_ICR(i2c)) & ICR_SCLE);
 267 }
 268
 269 static void i2c_pxa_abort(struct pxa_i2c *i2c)
 270 {
 271         int i = 250;
 272
 273         if (i2c_pxa_is_slavemode(i2c)) {
 274                 dev_dbg(&i2c->adap.dev, "%s: called in slave mode\n", __func__);
 275                 return;
 276         }
 277
 278         while ((i > 0) && (readl(_IBMR(i2c)) & 0x1) == 0) {
 279                 unsigned long icr = readl(_ICR(i2c));
 280
 281                 icr &= ~ICR_START;
 282                 icr |= ICR_ACKNAK | ICR_STOP | ICR_TB;
 283
 284                 writel(icr, _ICR(i2c));
 285
 286                 show_state(i2c);
 287
 288                 mdelay(1);
 289                 i --;
 290         }
 291
 292         writel(readl(_ICR(i2c)) & ~(ICR_MA | ICR_START | ICR_STOP),
 293                _ICR(i2c));
 294 }
 295
 296 static int i2c_pxa_wait_bus_not_busy(struct pxa_i2c *i2c)
 297 {
 298         int timeout = DEF_TIMEOUT;
 299
 300         while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
 301                 if ((readl(_ISR(i2c)) & ISR_SAD) != 0)
 302                         timeout += 4;
 303
 304                 msleep(2);
 305                 show_state(i2c);
 306         }
 307
 308         if (timeout < 0)
 309                 show_state(i2c);
 310
 311         return timeout < 0 ? I2C_RETRY : 0;
 312 }
 313
 314 static int i2c_pxa_wait_master(struct pxa_i2c *i2c)
 315 {
 316         unsigned long timeout = jiffies + HZ*4;
 317
 318         while (time_before(jiffies, timeout)) {
 319                 if (i2c_debug > 1)
 320                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 321                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 322
 323                 if (readl(_ISR(i2c)) & ISR_SAD) {
 324                         if (i2c_debug > 0)
 325                                 dev_dbg(&i2c->adap.dev, "%s: Slave detected\n", __func__);
 326                         goto out;
 327                 }
 328
 329                 /* wait for unit and bus being not busy, and we also do a
 330                  * quick check of the i2c lines themselves to ensure they've
 331                  * gone high...
 332                  */
 333                 if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) == 0 && readl(_IBMR(i2c)) == 3) {
 334                         if (i2c_debug > 0)
 335                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
 336                         return 1;
 337                 }
 338
 339                 msleep(1);
 340         }
 341
 342         if (i2c_debug > 0)
 343                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
 344  out:
 345         return 0;
 346 }
 347
 348 static int i2c_pxa_set_master(struct pxa_i2c *i2c)
 349 {
 350         if (i2c_debug)
 351                 dev_dbg(&i2c->adap.dev, "setting to bus master\n");
 352
 353         if ((readl(_ISR(i2c)) & (ISR_UB | ISR_IBB)) != 0) {
 354                 dev_dbg(&i2c->adap.dev, "%s: unit is busy\n", __func__);
 355                 if (!i2c_pxa_wait_master(i2c)) {
 356                         dev_dbg(&i2c->adap.dev, "%s: error: unit busy\n", __func__);
 357                         return I2C_RETRY;
 358                 }
 359         }
 360
 361         writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
 362         return 0;
 363 }
 364
 365 #ifdef CONFIG_I2C_PXA_SLAVE
 366 static int i2c_pxa_wait_slave(struct pxa_i2c *i2c)
 367 {
 368         unsigned long timeout = jiffies + HZ*1;
 369
 370         /* wait for stop */
 371
 372         show_state(i2c);
 373
 374         while (time_before(jiffies, timeout)) {
 375                 if (i2c_debug > 1)
 376                         dev_dbg(&i2c->adap.dev, "%s: %ld: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 377                                 __func__, (long)jiffies, readl(_ISR(i2c)), readl(_ICR(i2c)), readl(_IBMR(i2c)));
 378
 379                 if ((readl(_ISR(i2c)) & (ISR_UB|ISR_IBB)) == 0 ||
 380                     (readl(_ISR(i2c)) & ISR_SAD) != 0 ||
 381                     (readl(_ICR(i2c)) & ICR_SCLE) == 0) {
 382                         if (i2c_debug > 1)
 383                                 dev_dbg(&i2c->adap.dev, "%s: done\n", __func__);
 384                         return 1;
 385                 }
 386
 387                 msleep(1);
 388         }
 389
 390         if (i2c_debug > 0)
 391                 dev_dbg(&i2c->adap.dev, "%s: did not free\n", __func__);
 392         return 0;
 393 }
 394
 395 /*
 396  * clear the hold on the bus, and take of anything else
 397  * that has been configured
 398  */
 399 static void i2c_pxa_set_slave(struct pxa_i2c *i2c, int errcode)
 400 {
 401         show_state(i2c);
 402
 403         if (errcode < 0) {
 404                 udelay(100);   /* simple delay */
 405         } else {
 406                 /* we need to wait for the stop condition to end */
 407
 408                 /* if we where in stop, then clear... */
 409                 if (readl(_ICR(i2c)) & ICR_STOP) {
 410                         udelay(100);
 411                         writel(readl(_ICR(i2c)) & ~ICR_STOP, _ICR(i2c));
 412                 }
 413
 414                 if (!i2c_pxa_wait_slave(i2c)) {
 415                         dev_err(&i2c->adap.dev, "%s: wait timedout\n",
 416                                 __func__);
 417                         return;
 418                 }
 419         }
 420
 421         writel(readl(_ICR(i2c)) & ~(ICR_STOP|ICR_ACKNAK|ICR_MA), _ICR(i2c));
 422         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 423
 424         if (i2c_debug) {
 425                 dev_dbg(&i2c->adap.dev, "ICR now %08x, ISR %08x\n", readl(_ICR(i2c)), readl(_ISR(i2c)));
 426                 decode_ICR(readl(_ICR(i2c)));
 427         }
 428 }
 429 #else
 430 #define i2c_pxa_set_slave(i2c, err)     do { } while (0)
 431 #endif
 432
 433 static void i2c_pxa_reset(struct pxa_i2c *i2c)
 434 {
 435         pr_debug("Resetting I2C Controller Unit\n");
 436
 437         /* abort any transfer currently under way */
 438         i2c_pxa_abort(i2c);
 439
 440         /* reset according to 9.8 */
 441         writel(ICR_UR, _ICR(i2c));
 442         writel(I2C_ISR_INIT, _ISR(i2c));
 443         writel(readl(_ICR(i2c)) & ~ICR_UR, _ICR(i2c));
 444
 445         writel(i2c->slave_addr, _ISAR(i2c));
 446
 447         /* set control register values */
 448         writel(I2C_ICR_INIT | (i2c->fast_mode ? ICR_FM : 0), _ICR(i2c));
 449
 450 #ifdef CONFIG_I2C_PXA_SLAVE
 451         dev_info(&i2c->adap.dev, "Enabling slave mode\n");
 452         writel(readl(_ICR(i2c)) | ICR_SADIE | ICR_ALDIE | ICR_SSDIE, _ICR(i2c));
 453 #endif
 454
 455         i2c_pxa_set_slave(i2c, 0);
 456
 457         /* enable unit */
 458         writel(readl(_ICR(i2c)) | ICR_IUE, _ICR(i2c));
 459         udelay(100);
 460 }
 461
 462
 463 #ifdef CONFIG_I2C_PXA_SLAVE
 464 /*
 465  * PXA I2C Slave mode
 466  */
 467
 468 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
 469 {
 470         if (isr & ISR_BED) {
 471                 /* what should we do here? */
 472         } else {
 473                 int ret = 0;
 474
 475                 if (i2c->slave != NULL)
 476                         ret = i2c->slave->read(i2c->slave->data);
 477
 478                 writel(ret, _IDBR(i2c));
 479                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));   /* allow next byte */
 480         }
 481 }
 482
 483 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
 484 {
 485         unsigned int byte = readl(_IDBR(i2c));
 486
 487         if (i2c->slave != NULL)
 488                 i2c->slave->write(i2c->slave->data, byte);
 489
 490         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 491 }
 492
 493 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
 494 {
 495         int timeout;
 496
 497         if (i2c_debug > 0)
 498                 dev_dbg(&i2c->adap.dev, "SAD, mode is slave-%cx\n",
 499                        (isr & ISR_RWM) ? 'r' : 't');
 500
 501         if (i2c->slave != NULL)
 502                 i2c->slave->event(i2c->slave->data,
 503                                  (isr & ISR_RWM) ? I2C_SLAVE_EVENT_START_READ : I2C_SLAVE_EVENT_START_WRITE);
 504
 505         /*
 506          * slave could interrupt in the middle of us generating a
 507          * start condition... if this happens, we'd better back off
 508          * and stop holding the poor thing up
 509          */
 510         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
 511         writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 512
 513         timeout = 0x10000;
 514
 515         while (1) {
 516                 if ((readl(_IBMR(i2c)) & 2) == 2)
 517                         break;
 518
 519                 timeout--;
 520
 521                 if (timeout <= 0) {
 522                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
 523                         break;
 524                 }
 525         }
 526
 527         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 528 }
 529
 530 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
 531 {
 532         if (i2c_debug > 2)
 533                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop)\n");
 534
 535         if (i2c->slave != NULL)
 536                 i2c->slave->event(i2c->slave->data, I2C_SLAVE_EVENT_STOP);
 537
 538         if (i2c_debug > 2)
 539                 dev_dbg(&i2c->adap.dev, "ISR: SSD (Slave Stop) acked\n");
 540
 541         /*
 542          * If we have a master-mode message waiting,
 543          * kick it off now that the slave has completed.
 544          */
 545         if (i2c->msg)
 546                 i2c_pxa_master_complete(i2c, I2C_RETRY);
 547 }
 548 #else
 549 static void i2c_pxa_slave_txempty(struct pxa_i2c *i2c, u32 isr)
 550 {
 551         if (isr & ISR_BED) {
 552                 /* what should we do here? */
 553         } else {
 554                 writel(0, _IDBR(i2c));
 555                 writel(readl(_ICR(i2c)) | ICR_TB, _ICR(i2c));
 556         }
 557 }
 558
 559 static void i2c_pxa_slave_rxfull(struct pxa_i2c *i2c, u32 isr)
 560 {
 561         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
 562 }
 563
 564 static void i2c_pxa_slave_start(struct pxa_i2c *i2c, u32 isr)
 565 {
 566         int timeout;
 567
 568         /*
 569          * slave could interrupt in the middle of us generating a
 570          * start condition... if this happens, we'd better back off
 571          * and stop holding the poor thing up
 572          */
 573         writel(readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP), _ICR(i2c));
 574         writel(readl(_ICR(i2c)) | ICR_TB | ICR_ACKNAK, _ICR(i2c));
 575
 576         timeout = 0x10000;
 577
 578         while (1) {
 579                 if ((readl(_IBMR(i2c)) & 2) == 2)
 580                         break;
 581
 582                 timeout--;
 583
 584                 if (timeout <= 0) {
 585                         dev_err(&i2c->adap.dev, "timeout waiting for SCL high\n");
 586                         break;
 587                 }
 588         }
 589
 590         writel(readl(_ICR(i2c)) & ~ICR_SCLE, _ICR(i2c));
 591 }
 592
 593 static void i2c_pxa_slave_stop(struct pxa_i2c *i2c)
 594 {
 595         if (i2c->msg)
 596                 i2c_pxa_master_complete(i2c, I2C_RETRY);
 597 }
 598 #endif
 599
 600 /*
 601  * PXA I2C Master mode
 602  */
 603
 604 static inline unsigned int i2c_pxa_addr_byte(struct i2c_msg *msg)
 605 {
 606         unsigned int addr = (msg->addr & 0x7f) << 1;
 607
 608         if (msg->flags & I2C_M_RD)
 609                 addr |= 1;
 610
 611         return addr;
 612 }
 613
 614 static inline void i2c_pxa_start_message(struct pxa_i2c *i2c)
 615 {
 616         u32 icr;
 617
 618         /*
 619          * Step 1: target slave address into IDBR
 620          */
 621         writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
 622
 623         /*
 624          * Step 2: initiate the write.
 625          */
 626         icr = readl(_ICR(i2c)) & ~(ICR_STOP | ICR_ALDIE);
 627         writel(icr | ICR_START | ICR_TB, _ICR(i2c));
 628 }
 629
 630 static inline void i2c_pxa_stop_message(struct pxa_i2c *i2c)
 631 {
 632         u32 icr;
 633
 634         /*
 635          * Clear the STOP and ACK flags
 636          */
 637         icr = readl(_ICR(i2c));
 638         icr &= ~(ICR_STOP | ICR_ACKNAK);
 639         writel(icr, _ICR(i2c));
 640 }
 641
 642 static int i2c_pxa_pio_set_master(struct pxa_i2c *i2c)
 643 {
 644         /* make timeout the same as for interrupt based functions */
 645         long timeout = 2 * DEF_TIMEOUT;
 646
 647         /*
 648          * Wait for the bus to become free.
 649          */
 650         while (timeout-- && readl(_ISR(i2c)) & (ISR_IBB | ISR_UB)) {
 651                 udelay(1000);
 652                 show_state(i2c);
 653         }
 654
 655         if (timeout < 0) {
 656                 show_state(i2c);
 657                 dev_err(&i2c->adap.dev,
 658                         "i2c_pxa: timeout waiting for bus free\n");
 659                 return I2C_RETRY;
 660         }
 661
 662         /*
 663          * Set master mode.
 664          */
 665         writel(readl(_ICR(i2c)) | ICR_SCLE, _ICR(i2c));
 666
 667         return 0;
 668 }
 669
 670 static int i2c_pxa_do_pio_xfer(struct pxa_i2c *i2c,
 671                                struct i2c_msg *msg, int num)
 672 {
 673         unsigned long timeout = 500000; /* 5 seconds */
 674         int ret = 0;
 675
 676         ret = i2c_pxa_pio_set_master(i2c);
 677         if (ret)
 678                 goto out;
 679
 680         i2c->msg = msg;
 681         i2c->msg_num = num;
 682         i2c->msg_idx = 0;
 683         i2c->msg_ptr = 0;
 684         i2c->irqlogidx = 0;
 685
 686         i2c_pxa_start_message(i2c);
 687
 688         while (i2c->msg_num > 0 && --timeout) {
 689                 i2c_pxa_handler(0, i2c);
 690                 udelay(10);
 691         }
 692
 693         i2c_pxa_stop_message(i2c);
 694
 695         /*
 696          * We place the return code in i2c->msg_idx.
 697          */
 698         ret = i2c->msg_idx;
 699
 700 out:
 701         if (timeout == 0)
 702                 i2c_pxa_scream_blue_murder(i2c, "timeout");
 703
 704         return ret;
 705 }
 706
 707 /*
 708  * We are protected by the adapter bus mutex.
 709  */
 710 static int i2c_pxa_do_xfer(struct pxa_i2c *i2c, struct i2c_msg *msg, int num)
 711 {
 712         long timeout;
 713         int ret;
 714
 715         /*
 716          * Wait for the bus to become free.
 717          */
 718         ret = i2c_pxa_wait_bus_not_busy(i2c);
 719         if (ret) {
 720                 dev_err(&i2c->adap.dev, "i2c_pxa: timeout waiting for bus free\n");
 721                 goto out;
 722         }
 723
 724         /*
 725          * Set master mode.
 726          */
 727         ret = i2c_pxa_set_master(i2c);
 728         if (ret) {
 729                 dev_err(&i2c->adap.dev, "i2c_pxa_set_master: error %d\n", ret);
 730                 goto out;
 731         }
 732
 733         spin_lock_irq(&i2c->lock);
 734
 735         i2c->msg = msg;
 736         i2c->msg_num = num;
 737         i2c->msg_idx = 0;
 738         i2c->msg_ptr = 0;
 739         i2c->irqlogidx = 0;
 740
 741         i2c_pxa_start_message(i2c);
 742
 743         spin_unlock_irq(&i2c->lock);
 744
 745         /*
 746          * The rest of the processing occurs in the interrupt handler.
 747          */
 748         timeout = wait_event_timeout(i2c->wait, i2c->msg_num == 0, HZ * 5);
 749         i2c_pxa_stop_message(i2c);
 750
 751         /*
 752          * We place the return code in i2c->msg_idx.
 753          */
 754         ret = i2c->msg_idx;
 755
 756         if (timeout == 0)
 757                 i2c_pxa_scream_blue_murder(i2c, "timeout");
 758
 759  out:
 760         return ret;
 761 }
 762
 763 static int i2c_pxa_pio_xfer(struct i2c_adapter *adap,
 764                             struct i2c_msg msgs[], int num)
 765 {
 766         struct pxa_i2c *i2c = adap->algo_data;
 767         int ret, i;
 768
 769         /* If the I2C controller is disabled we need to reset it
 770           (probably due to a suspend/resume destroying state). We do
 771           this here as we can then avoid worrying about resuming the
 772           controller before its users. */
 773         if (!(readl(_ICR(i2c)) & ICR_IUE))
 774                 i2c_pxa_reset(i2c);
 775
 776         for (i = adap->retries; i >= 0; i--) {
 777                 ret = i2c_pxa_do_pio_xfer(i2c, msgs, num);
 778                 if (ret != I2C_RETRY)
 779                         goto out;
 780
 781                 if (i2c_debug)
 782                         dev_dbg(&adap->dev, "Retrying transmission\n");
 783                 udelay(100);
 784         }
 785         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
 786         ret = -EREMOTEIO;
 787  out:
 788         i2c_pxa_set_slave(i2c, ret);
 789         return ret;
 790 }
 791
 792 /*
 793  * i2c_pxa_master_complete - complete the message and wake up.
 794  */
 795 static void i2c_pxa_master_complete(struct pxa_i2c *i2c, int ret)
 796 {
 797         i2c->msg_ptr = 0;
 798         i2c->msg = NULL;
 799         i2c->msg_idx ++;
 800         i2c->msg_num = 0;
 801         if (ret)
 802                 i2c->msg_idx = ret;
 803         if (!i2c->use_pio)
 804                 wake_up(&i2c->wait);
 805 }
 806
 807 static void i2c_pxa_irq_txempty(struct pxa_i2c *i2c, u32 isr)
 808 {
 809         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
 810
 811  again:
 812         /*
 813          * If ISR_ALD is set, we lost arbitration.
 814          */
 815         if (isr & ISR_ALD) {
 816                 /*
 817                  * Do we need to do anything here?  The PXA docs
 818                  * are vague about what happens.
 819                  */
 820                 i2c_pxa_scream_blue_murder(i2c, "ALD set");
 821
 822                 /*
 823                  * We ignore this error.  We seem to see spurious ALDs
 824                  * for seemingly no reason.  If we handle them as I think
 825                  * they should, we end up causing an I2C error, which
 826                  * is painful for some systems.
 827                  */
 828                 return; /* ignore */
 829         }
 830
 831         if (isr & ISR_BED) {
 832                 int ret = BUS_ERROR;
 833
 834                 /*
 835                  * I2C bus error - either the device NAK'd us, or
 836                  * something more serious happened.  If we were NAK'd
 837                  * on the initial address phase, we can retry.
 838                  */
 839                 if (isr & ISR_ACKNAK) {
 840                         if (i2c->msg_ptr == 0 && i2c->msg_idx == 0)
 841                                 ret = I2C_RETRY;
 842                         else
 843                                 ret = XFER_NAKED;
 844                 }
 845                 i2c_pxa_master_complete(i2c, ret);
 846         } else if (isr & ISR_RWM) {
 847                 /*
 848                  * Read mode.  We have just sent the address byte, and
 849                  * now we must initiate the transfer.
 850                  */
 851                 if (i2c->msg_ptr == i2c->msg->len - 1 &&
 852                     i2c->msg_idx == i2c->msg_num - 1)
 853                         icr |= ICR_STOP | ICR_ACKNAK;
 854
 855                 icr |= ICR_ALDIE | ICR_TB;
 856         } else if (i2c->msg_ptr < i2c->msg->len) {
 857                 /*
 858                  * Write mode.  Write the next data byte.
 859                  */
 860                 writel(i2c->msg->buf[i2c->msg_ptr++], _IDBR(i2c));
 861
 862                 icr |= ICR_ALDIE | ICR_TB;
 863
 864                 /*
 865                  * If this is the last byte of the last message, send
 866                  * a STOP.
 867                  */
 868                 if (i2c->msg_ptr == i2c->msg->len &&
 869                     i2c->msg_idx == i2c->msg_num - 1)
 870                         icr |= ICR_STOP;
 871         } else if (i2c->msg_idx < i2c->msg_num - 1) {
 872                 /*
 873                  * Next segment of the message.
 874                  */
 875                 i2c->msg_ptr = 0;
 876                 i2c->msg_idx ++;
 877                 i2c->msg++;
 878
 879                 /*
 880                  * If we aren't doing a repeated start and address,
 881                  * go back and try to send the next byte.  Note that
 882                  * we do not support switching the R/W direction here.
 883                  */
 884                 if (i2c->msg->flags & I2C_M_NOSTART)
 885                         goto again;
 886
 887                 /*
 888                  * Write the next address.
 889                  */
 890                 writel(i2c_pxa_addr_byte(i2c->msg), _IDBR(i2c));
 891
 892                 /*
 893                  * And trigger a repeated start, and send the byte.
 894                  */
 895                 icr &= ~ICR_ALDIE;
 896                 icr |= ICR_START | ICR_TB;
 897         } else {
 898                 if (i2c->msg->len == 0) {
 899                         /*
 900                          * Device probes have a message length of zero
 901                          * and need the bus to be reset before it can
 902                          * be used again.
 903                          */
 904                         i2c_pxa_reset(i2c);
 905                 }
 906                 i2c_pxa_master_complete(i2c, 0);
 907         }
 908
 909         i2c->icrlog[i2c->irqlogidx-1] = icr;
 910
 911         writel(icr, _ICR(i2c));
 912         show_state(i2c);
 913 }
 914
 915 static void i2c_pxa_irq_rxfull(struct pxa_i2c *i2c, u32 isr)
 916 {
 917         u32 icr = readl(_ICR(i2c)) & ~(ICR_START|ICR_STOP|ICR_ACKNAK|ICR_TB);
 918
 919         /*
 920          * Read the byte.
 921          */
 922         i2c->msg->buf[i2c->msg_ptr++] = readl(_IDBR(i2c));
 923
 924         if (i2c->msg_ptr < i2c->msg->len) {
 925                 /*
 926                  * If this is the last byte of the last
 927                  * message, send a STOP.
 928                  */
 929                 if (i2c->msg_ptr == i2c->msg->len - 1)
 930                         icr |= ICR_STOP | ICR_ACKNAK;
 931
 932                 icr |= ICR_ALDIE | ICR_TB;
 933         } else {
 934                 i2c_pxa_master_complete(i2c, 0);
 935         }
 936
 937         i2c->icrlog[i2c->irqlogidx-1] = icr;
 938
 939         writel(icr, _ICR(i2c));
 940 }
 941
 942 static irqreturn_t i2c_pxa_handler(int this_irq, void *dev_id)
 943 {
 944         struct pxa_i2c *i2c = dev_id;
 945         u32 isr = readl(_ISR(i2c));
 946
 947         if (i2c_debug > 2 && 0) {
 948                 dev_dbg(&i2c->adap.dev, "%s: ISR=%08x, ICR=%08x, IBMR=%02x\n",
 949                         __func__, isr, readl(_ICR(i2c)), readl(_IBMR(i2c)));
 950                 decode_ISR(isr);
 951         }
 952
 953         if (i2c->irqlogidx < ARRAY_SIZE(i2c->isrlog))
 954                 i2c->isrlog[i2c->irqlogidx++] = isr;
 955
 956         show_state(i2c);
 957
 958         /*
 959          * Always clear all pending IRQs.
 960          */
 961         writel(isr & (ISR_SSD|ISR_ALD|ISR_ITE|ISR_IRF|ISR_SAD|ISR_BED), _ISR(i2c));
 962
 963         if (isr & ISR_SAD)
 964                 i2c_pxa_slave_start(i2c, isr);
 965         if (isr & ISR_SSD)
 966                 i2c_pxa_slave_stop(i2c);
 967
 968         if (i2c_pxa_is_slavemode(i2c)) {
 969                 if (isr & ISR_ITE)
 970                         i2c_pxa_slave_txempty(i2c, isr);
 971                 if (isr & ISR_IRF)
 972                         i2c_pxa_slave_rxfull(i2c, isr);
 973         } else if (i2c->msg) {
 974                 if (isr & ISR_ITE)
 975                         i2c_pxa_irq_txempty(i2c, isr);
 976                 if (isr & ISR_IRF)
 977                         i2c_pxa_irq_rxfull(i2c, isr);
 978         } else {
 979                 i2c_pxa_scream_blue_murder(i2c, "spurious irq");
 980         }
 981
 982         return IRQ_HANDLED;
 983 }
 984
 985
 986 static int i2c_pxa_xfer(struct i2c_adapter *adap, struct i2c_msg msgs[], int num)
 987 {
 988         struct pxa_i2c *i2c = adap->algo_data;
 989         int ret, i;
 990
 991         for (i = adap->retries; i >= 0; i--) {
 992                 ret = i2c_pxa_do_xfer(i2c, msgs, num);
 993                 if (ret != I2C_RETRY)
 994                         goto out;
 995
 996                 if (i2c_debug)
 997                         dev_dbg(&adap->dev, "Retrying transmission\n");
 998                 udelay(100);
 999         }
1000         i2c_pxa_scream_blue_murder(i2c, "exhausted retries");
1001         ret = -EREMOTEIO;
1002  out:
1003         i2c_pxa_set_slave(i2c, ret);
1004         return ret;
1005 }
1006
1007 static u32 i2c_pxa_functionality(struct i2c_adapter *adap)
1008 {
1009         return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
1010 }
1011
1012 static const struct i2c_algorithm i2c_pxa_algorithm = {
1013         .master_xfer    = i2c_pxa_xfer,
1014         .functionality  = i2c_pxa_functionality,
1015 };
1016
1017 static const struct i2c_algorithm i2c_pxa_pio_algorithm = {
1018         .master_xfer    = i2c_pxa_pio_xfer,
1019         .functionality  = i2c_pxa_functionality,
1020 };
1021
1022 static int i2c_pxa_probe(struct platform_device *dev)
1023 {
1024         struct pxa_i2c *i2c;
1025         struct resource *res;
1026         struct i2c_pxa_platform_data *plat = dev->dev.platform_data;
1027         const struct platform_device_id *id = platform_get_device_id(dev);
1028         enum pxa_i2c_types i2c_type = id->driver_data;
1029         int ret;
1030         int irq;
1031
1032         res = platform_get_resource(dev, IORESOURCE_MEM, 0);
1033         irq = platform_get_irq(dev, 0);
1034         if (res == NULL || irq < 0)
1035                 return -ENODEV;
1036
1037         if (!request_mem_region(res->start, resource_size(res), res->name))
1038                 return -ENOMEM;
1039
1040         i2c = kzalloc(sizeof(struct pxa_i2c), GFP_KERNEL);
1041         if (!i2c) {
1042                 ret = -ENOMEM;
1043                 goto emalloc;
1044         }
1045
1046         i2c->adap.owner   = THIS_MODULE;
1047         i2c->adap.retries = 5;
1048
1049         spin_lock_init(&i2c->lock);
1050         init_waitqueue_head(&i2c->wait);
1051
1052         /*
1053          * If "dev->id" is negative we consider it as zero.
1054          * The reason to do so is to avoid sysfs names that only make
1055          * sense when there are multiple adapters.
1056          */
1057         i2c->adap.nr = dev->id != -1 ? dev->id : 0;
1058         snprintf(i2c->adap.name, sizeof(i2c->adap.name), "pxa_i2c-i2c.%u",
1059                  i2c->adap.nr);
1060
1061         i2c->clk = clk_get(&dev->dev, NULL);
1062         if (IS_ERR(i2c->clk)) {
1063                 ret = PTR_ERR(i2c->clk);
1064                 goto eclk;
1065         }
1066
1067         i2c->reg_base = ioremap(res->start, resource_size(res));
1068         if (!i2c->reg_base) {
1069                 ret = -EIO;
1070                 goto eremap;
1071         }
1072
1073         i2c->reg_ibmr = i2c->reg_base + pxa_reg_layout[i2c_type].ibmr;
1074         i2c->reg_idbr = i2c->reg_base + pxa_reg_layout[i2c_type].idbr;
1075         i2c->reg_icr = i2c->reg_base + pxa_reg_layout[i2c_type].icr;
1076         i2c->reg_isr = i2c->reg_base + pxa_reg_layout[i2c_type].isr;
1077         i2c->reg_isar = i2c->reg_base + pxa_reg_layout[i2c_type].isar;
1078
1079         i2c->iobase = res->start;
1080         i2c->iosize = resource_size(res);
1081
1082         i2c->irq = irq;
1083
1084         i2c->slave_addr = I2C_PXA_SLAVE_ADDR;
1085
1086 #ifdef CONFIG_I2C_PXA_SLAVE
1087         if (plat) {
1088                 i2c->slave_addr = plat->slave_addr;
1089                 i2c->slave = plat->slave;
1090         }
1091 #endif
1092
1093         clk_enable(i2c->clk);
1094
1095         if (plat) {
1096                 i2c->adap.class = plat->class;
1097                 i2c->use_pio = plat->use_pio;
1098                 i2c->fast_mode = plat->fast_mode;
1099         }
1100
1101         if (i2c->use_pio) {
1102                 i2c->adap.algo = &i2c_pxa_pio_algorithm;
1103         } else {
1104                 i2c->adap.algo = &i2c_pxa_algorithm;
1105                 ret = request_irq(irq, i2c_pxa_handler, IRQF_DISABLED,
1106                                   i2c->adap.name, i2c);
1107                 if (ret)
1108                         goto ereqirq;
1109         }
1110
1111         i2c_pxa_reset(i2c);
1112
1113         i2c->adap.algo_data = i2c;
1114         i2c->adap.dev.parent = &dev->dev;
1115
1116         ret = i2c_add_numbered_adapter(&i2c->adap);
1117         if (ret < 0) {
1118                 printk(KERN_INFO "I2C: Failed to add bus\n");
1119                 goto eadapt;
1120         }
1121
1122         platform_set_drvdata(dev, i2c);
1123
1124 #ifdef CONFIG_I2C_PXA_SLAVE
1125         printk(KERN_INFO "I2C: %s: PXA I2C adapter, slave address %d\n",
1126                dev_name(&i2c->adap.dev), i2c->slave_addr);
1127 #else
1128         printk(KERN_INFO "I2C: %s: PXA I2C adapter\n",
1129                dev_name(&i2c->adap.dev));
1130 #endif
1131         return 0;
1132
1133 eadapt:
1134         if (!i2c->use_pio)
1135                 free_irq(irq, i2c);
1136 ereqirq:
1137         clk_disable(i2c->clk);
1138         iounmap(i2c->reg_base);
1139 eremap:
1140         clk_put(i2c->clk);
1141 eclk:
1142         kfree(i2c);
1143 emalloc:
1144         release_mem_region(res->start, resource_size(res));
1145         return ret;
1146 }
1147
1148 static int __exit i2c_pxa_remove(struct platform_device *dev)
1149 {
1150         struct pxa_i2c *i2c = platform_get_drvdata(dev);
1151
1152         platform_set_drvdata(dev, NULL);
1153
1154         i2c_del_adapter(&i2c->adap);
1155         if (!i2c->use_pio)
1156                 free_irq(i2c->irq, i2c);
1157
1158         clk_disable(i2c->clk);
1159         clk_put(i2c->clk);
1160
1161         iounmap(i2c->reg_base);
1162         release_mem_region(i2c->iobase, i2c->iosize);
1163         kfree(i2c);
1164
1165         return 0;
1166 }
1167
1168 #ifdef CONFIG_PM
1169 static int i2c_pxa_suspend_noirq(struct device *dev)
1170 {
1171         struct platform_device *pdev = to_platform_device(dev);
1172         struct pxa_i2c *i2c = platform_get_drvdata(pdev);
1173
1174         clk_disable(i2c->clk);
1175
1176         return 0;
1177 }
1178
1179 static int i2c_pxa_resume_noirq(struct device *dev)
1180 {
1181         struct platform_device *pdev = to_platform_device(dev);
1182         struct pxa_i2c *i2c = platform_get_drvdata(pdev);
1183
1184         clk_enable(i2c->clk);
1185         i2c_pxa_reset(i2c);
1186
1187         return 0;
1188 }
1189
1190 static const struct dev_pm_ops i2c_pxa_dev_pm_ops = {
1191         .suspend_noirq = i2c_pxa_suspend_noirq,
1192         .resume_noirq = i2c_pxa_resume_noirq,
1193 };
1194
1195 #define I2C_PXA_DEV_PM_OPS (&i2c_pxa_dev_pm_ops)
1196 #else
1197 #define I2C_PXA_DEV_PM_OPS NULL
1198 #endif
1199
1200 static struct platform_driver i2c_pxa_driver = {
1201         .probe          = i2c_pxa_probe,
1202         .remove         = __exit_p(i2c_pxa_remove),
1203         .driver         = {
1204                 .name   = "pxa2xx-i2c",
1205                 .owner  = THIS_MODULE,
1206                 .pm     = I2C_PXA_DEV_PM_OPS,
1207         },
1208         .id_table       = i2c_pxa_id_table,
1209 };
1210
1211 static int __init i2c_adap_pxa_init(void)
1212 {
1213         return platform_driver_register(&i2c_pxa_driver);
1214 }
1215
1216 static void __exit i2c_adap_pxa_exit(void)
1217 {
1218         platform_driver_unregister(&i2c_pxa_driver);
1219 }
1220
1221 MODULE_LICENSE("GPL");
1222 MODULE_ALIAS("platform:pxa2xx-i2c");
1223
1224 subsys_initcall(i2c_adap_pxa_init);
1225 module_exit(i2c_adap_pxa_exit);